blob: 6c365910011d916200c39ce26c885fb7b733a269 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simekf22651c2012-09-28 09:56:37 +00002/*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
Michal Simek3e1b61d2018-01-17 07:37:47 +01004 * (C) Copyright 2013 - 2018 Xilinx, Inc.
Michal Simekf22651c2012-09-28 09:56:37 +00005 */
6
7#include <common.h>
Algapally Santosh Sagar340760e2023-06-14 03:03:59 -06008#include <debug_uart.h>
9#include <dfu.h>
Simon Glass52559322019-11-14 12:57:46 -070010#include <init.h>
Michal Simek62b96262020-07-28 12:45:47 +020011#include <log.h>
Michal Simeke6cc3b22018-02-21 17:04:28 +010012#include <dm/uclass.h>
Simon Glass9fb625c2019-08-01 09:46:51 -060013#include <env.h>
Ashok Reddy Somacd085132021-02-23 08:07:45 -070014#include <env_internal.h>
Michal Simek9e0e37a2014-02-24 11:16:32 +010015#include <fdtdec.h>
Michal Simek5b73caf2014-04-25 13:51:17 +020016#include <fpga.h>
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053017#include <malloc.h>
Michal Simekc67fecd2021-08-27 12:53:32 +020018#include <memalign.h>
Michal Simek5b73caf2014-04-25 13:51:17 +020019#include <mmc.h>
Michal Simek0ecd14e2018-06-08 13:45:14 +020020#include <watchdog.h>
Michal Simeke6cc3b22018-02-21 17:04:28 +010021#include <wdt.h>
Michal Simekd5dae852013-04-22 15:43:02 +020022#include <zynqpl.h>
Simon Glass401d1c42020-10-30 21:38:53 -060023#include <asm/global_data.h>
Michal Simek71936532013-04-12 16:33:08 +020024#include <asm/arch/hardware.h>
25#include <asm/arch/sys_proto.h>
Michal Simek80fdef12020-03-31 12:39:37 +020026#include "../common/board.h"
Michal Simekf22651c2012-09-28 09:56:37 +000027
28DECLARE_GLOBAL_DATA_PTR;
29
Michal Simek05f0f262022-02-17 14:28:41 +010030#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT)
31void board_debug_uart_init(void)
32{
33 /* Add initialization sequence if UART is not configured */
34}
35#endif
36
Michal Simekf22651c2012-09-28 09:56:37 +000037int board_init(void)
38{
Michal Simek98757d82021-02-02 16:34:48 +010039 if (IS_ENABLED(CONFIG_SPL_BUILD))
40 printf("Silicon version:\t%d\n", zynq_get_silicon_version());
41
Michal Simek2fe55d12022-09-27 09:55:46 +020042 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
43 xilinx_read_eeprom();
44
Michal Simekf22651c2012-09-28 09:56:37 +000045 return 0;
46}
47
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053048int board_late_init(void)
49{
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053050 int env_targets_len = 0;
51 const char *mode;
52 char *new_targets;
53 char *env_targets;
54
Michal Simek62b96262020-07-28 12:45:47 +020055 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
56 debug("Saved variables - Skipping\n");
57 return 0;
58 }
59
Simon Glassb2561c52023-02-05 15:39:49 -070060 if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
Michal Simek62b96262020-07-28 12:45:47 +020061 return 0;
62
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053063 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Michal Simek085b2b82016-12-16 13:16:14 +010064 case ZYNQ_BM_QSPI:
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053065 mode = "qspi";
Simon Glass382bee52017-08-03 12:22:09 -060066 env_set("modeboot", "qspiboot");
Michal Simek085b2b82016-12-16 13:16:14 +010067 break;
68 case ZYNQ_BM_NAND:
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053069 mode = "nand";
Simon Glass382bee52017-08-03 12:22:09 -060070 env_set("modeboot", "nandboot");
Michal Simek085b2b82016-12-16 13:16:14 +010071 break;
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053072 case ZYNQ_BM_NOR:
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053073 mode = "nor";
Simon Glass382bee52017-08-03 12:22:09 -060074 env_set("modeboot", "norboot");
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053075 break;
76 case ZYNQ_BM_SD:
Michal Simek7712fb12019-09-11 12:51:49 +020077 mode = "mmc0";
Simon Glass382bee52017-08-03 12:22:09 -060078 env_set("modeboot", "sdboot");
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053079 break;
80 case ZYNQ_BM_JTAG:
T Karthik Reddyc352f1e2019-11-13 21:13:44 -070081 mode = "jtag pxe dhcp";
Simon Glass382bee52017-08-03 12:22:09 -060082 env_set("modeboot", "jtagboot");
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053083 break;
84 default:
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053085 mode = "";
Simon Glass382bee52017-08-03 12:22:09 -060086 env_set("modeboot", "");
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053087 break;
88 }
89
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053090 /*
91 * One terminating char + one byte for space between mode
92 * and default boot_targets
93 */
94 env_targets = env_get("boot_targets");
95 if (env_targets)
96 env_targets_len = strlen(env_targets);
97
98 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
99 if (!new_targets)
100 return -ENOMEM;
101
102 sprintf(new_targets, "%s %s", mode,
103 env_targets ? env_targets : "");
104
105 env_set("boot_targets", new_targets);
106
Michal Simek80fdef12020-03-31 12:39:37 +0200107 return board_late_init_xilinx();
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +0530108}
Michal Simekf22651c2012-09-28 09:56:37 +0000109
Tom Riniaa6e94d2022-11-16 13:10:37 -0500110#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
Simon Glass76b00ac2017-03-31 08:40:32 -0600111int dram_init_banksize(void)
Tom Rini361a8792016-12-09 07:56:54 -0500112{
Michal Simekda3f0032017-11-03 15:25:51 +0100113 return fdtdec_setup_memory_banksize();
Michal Simek758f29d2016-04-01 15:56:33 +0200114}
115
Michal Simek8a5db0a2016-12-06 16:31:53 +0100116int dram_init(void)
117{
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +0530118 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rosside9bf1b2016-12-19 00:03:34 +1000119 return -EINVAL;
Michal Simek8a5db0a2016-12-06 16:31:53 +0100120
121 zynq_ddrc_init();
122
123 return 0;
124}
Michal Simek758f29d2016-04-01 15:56:33 +0200125#else
126int dram_init(void)
127{
Tom Riniaa6e94d2022-11-16 13:10:37 -0500128 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
129 CFG_SYS_SDRAM_SIZE);
Michal Simek758f29d2016-04-01 15:56:33 +0200130
131 zynq_ddrc_init();
132
133 return 0;
134}
135#endif
Ashok Reddy Somacd085132021-02-23 08:07:45 -0700136
137enum env_location env_get_location(enum env_operation op, int prio)
138{
139 u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK;
140
141 if (prio)
142 return ENVL_UNKNOWN;
143
144 switch (bootmode) {
145 case ZYNQ_BM_SD:
146 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
147 return ENVL_FAT;
148 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
149 return ENVL_EXT4;
Mike Looijmans50918d02021-07-02 10:28:36 +0200150 return ENVL_NOWHERE;
Ashok Reddy Somacd085132021-02-23 08:07:45 -0700151 case ZYNQ_BM_NAND:
152 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
153 return ENVL_NAND;
154 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
155 return ENVL_UBI;
Mike Looijmans50918d02021-07-02 10:28:36 +0200156 return ENVL_NOWHERE;
Ashok Reddy Somacd085132021-02-23 08:07:45 -0700157 case ZYNQ_BM_NOR:
158 case ZYNQ_BM_QSPI:
159 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
160 return ENVL_SPI_FLASH;
Mike Looijmans50918d02021-07-02 10:28:36 +0200161 return ENVL_NOWHERE;
Ashok Reddy Somacd085132021-02-23 08:07:45 -0700162 case ZYNQ_BM_JTAG:
163 default:
164 return ENVL_NOWHERE;
165 }
166}
Michal Simekc67fecd2021-08-27 12:53:32 +0200167
168#if defined(CONFIG_SET_DFU_ALT_INFO)
169
170#define DFU_ALT_BUF_LEN SZ_1K
171
172void set_dfu_alt_info(char *interface, char *devstr)
173{
174 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
175
Michal Simekce183fd2022-08-09 16:32:52 +0200176 if (env_get("dfu_alt_info"))
Michal Simekc67fecd2021-08-27 12:53:32 +0200177 return;
178
179 memset(buf, 0, sizeof(buf));
180
181 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
182 case ZYNQ_BM_SD:
183 snprintf(buf, DFU_ALT_BUF_LEN,
Michal Simek88eaca22022-08-09 16:32:54 +0200184 "mmc 0=boot.bin fat 0 1;"
Michal Simek93020aa2022-08-09 16:32:53 +0200185 "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
Michal Simekc67fecd2021-08-27 12:53:32 +0200186 break;
Michal Simek1cd876b2023-11-13 10:05:27 +0100187#if defined(CONFIG_SPL_SPI_LOAD)
Michal Simekc67fecd2021-08-27 12:53:32 +0200188 case ZYNQ_BM_QSPI:
189 snprintf(buf, DFU_ALT_BUF_LEN,
190 "sf 0:0=boot.bin raw 0 0x1500000;"
Michal Simek93020aa2022-08-09 16:32:53 +0200191 "%s raw 0x%x 0x500000",
192 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
Michal Simekc67fecd2021-08-27 12:53:32 +0200193 CONFIG_SYS_SPI_U_BOOT_OFFS);
194 break;
Michal Simek1cd876b2023-11-13 10:05:27 +0100195#endif
Michal Simekc67fecd2021-08-27 12:53:32 +0200196 default:
197 return;
198 }
199
200 env_set("dfu_alt_info", buf);
201 puts("DFU alt info setting: done\n");
202}
203#endif