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Tom Warren74652cf2011-04-14 12:18:06 +00001/*
Tom Warren7aaa5a62015-03-04 16:36:00 -07002* (C) Copyright 2010-2015
Tom Warren74652cf2011-04-14 12:18:06 +00003* NVIDIA Corporation <www.nvidia.com>
4*
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Tom Warren74652cf2011-04-14 12:18:06 +00006*/
Tom Warrenb2871032012-12-11 13:34:15 +00007
8/* Tegra AP (Application Processor) code */
9
Tom Warren74652cf2011-04-14 12:18:06 +000010#include <common.h>
Tom Warren150c2492012-09-19 15:50:56 -070011#include <asm/io.h>
12#include <asm/arch/gp_padctrl.h>
Ian Campbell73169872015-04-21 07:18:36 +020013#include <asm/arch/mc.h>
Tom Warren150c2492012-09-19 15:50:56 -070014#include <asm/arch-tegra/ap.h>
Tom Warrenb2871032012-12-11 13:34:15 +000015#include <asm/arch-tegra/clock.h>
Tom Warren150c2492012-09-19 15:50:56 -070016#include <asm/arch-tegra/fuse.h>
17#include <asm/arch-tegra/pmc.h>
18#include <asm/arch-tegra/scu.h>
Tom Warrene23bb6a2013-01-28 13:32:10 +000019#include <asm/arch-tegra/tegra.h>
Tom Warren150c2492012-09-19 15:50:56 -070020#include <asm/arch-tegra/warmboot.h>
Tom Warren74652cf2011-04-14 12:18:06 +000021
Tom Warren49493cb2013-04-10 10:32:32 -070022int tegra_get_chip(void)
Simon Glassd5153622012-04-02 13:18:50 +000023{
Tom Warren49493cb2013-04-10 10:32:32 -070024 int rev;
25 struct apb_misc_gp_ctlr *gp =
26 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
Simon Glassd5153622012-04-02 13:18:50 +000027
28 /*
29 * This is undocumented, Chip ID is bits 15:8 of the register
30 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
Tom Warren2f5dac92014-01-24 12:46:16 -070031 * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
Simon Glassd5153622012-04-02 13:18:50 +000032 */
Simon Glassd5153622012-04-02 13:18:50 +000033 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
Tom Warren49493cb2013-04-10 10:32:32 -070034 debug("%s: CHIPID is 0x%02X\n", __func__, rev);
Simon Glassd5153622012-04-02 13:18:50 +000035
Tom Warren49493cb2013-04-10 10:32:32 -070036 return rev;
37}
Simon Glassd5153622012-04-02 13:18:50 +000038
Tom Warren49493cb2013-04-10 10:32:32 -070039int tegra_get_sku_info(void)
40{
41 int sku_id;
42 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
43
44 sku_id = readl(&fuse->sku_info) & 0xff;
45 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
46
47 return sku_id;
48}
49
50int tegra_get_chip_sku(void)
51{
52 uint sku_id, chip_id;
53
54 chip_id = tegra_get_chip();
55 sku_id = tegra_get_sku_info();
56
57 switch (chip_id) {
Allen Martin00a27492012-08-31 08:30:00 +000058 case CHIPID_TEGRA20:
Tom Warren49493cb2013-04-10 10:32:32 -070059 switch (sku_id) {
Stephen Warren20583d02013-05-17 14:10:15 +000060 case SKU_ID_T20_7:
Simon Glassd5153622012-04-02 13:18:50 +000061 case SKU_ID_T20:
62 return TEGRA_SOC_T20;
63 case SKU_ID_T25SE:
64 case SKU_ID_AP25:
65 case SKU_ID_T25:
66 case SKU_ID_AP25E:
67 case SKU_ID_T25E:
68 return TEGRA_SOC_T25;
69 }
70 break;
Tom Warrenb2871032012-12-11 13:34:15 +000071 case CHIPID_TEGRA30:
Tom Warren49493cb2013-04-10 10:32:32 -070072 switch (sku_id) {
Stephen Warreneb222d12013-03-27 09:37:02 +000073 case SKU_ID_T33:
Tom Warrenb2871032012-12-11 13:34:15 +000074 case SKU_ID_T30:
Alban Bedel3346cbb2013-11-13 17:27:18 +010075 case SKU_ID_TM30MQS_P_A3:
Stephen Warren86b65782014-01-21 17:19:19 -070076 default:
Tom Warrenb2871032012-12-11 13:34:15 +000077 return TEGRA_SOC_T30;
78 }
79 break;
Tom Warrene23bb6a2013-01-28 13:32:10 +000080 case CHIPID_TEGRA114:
Tom Warren49493cb2013-04-10 10:32:32 -070081 switch (sku_id) {
Tom Warrene23bb6a2013-01-28 13:32:10 +000082 case SKU_ID_T114_ENG:
Stephen Warren840167c2013-05-17 14:10:14 +000083 case SKU_ID_T114_1:
Stephen Warren86b65782014-01-21 17:19:19 -070084 default:
Tom Warrene23bb6a2013-01-28 13:32:10 +000085 return TEGRA_SOC_T114;
86 }
87 break;
Tom Warren2f5dac92014-01-24 12:46:16 -070088 case CHIPID_TEGRA124:
89 switch (sku_id) {
90 case SKU_ID_T124_ENG:
91 default:
92 return TEGRA_SOC_T124;
93 }
94 break;
Tom Warren7aaa5a62015-03-04 16:36:00 -070095 case CHIPID_TEGRA210:
96 switch (sku_id) {
97 case SKU_ID_T210_ENG:
98 default:
99 return TEGRA_SOC_T210;
100 }
101 break;
Simon Glassd5153622012-04-02 13:18:50 +0000102 }
Tom Warren2f5dac92014-01-24 12:46:16 -0700103
Tom Warren49493cb2013-04-10 10:32:32 -0700104 /* unknown chip/sku id */
105 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
106 __func__, chip_id, sku_id);
Simon Glassd5153622012-04-02 13:18:50 +0000107 return TEGRA_SOC_UNKNOWN;
108}
109
Tom Warren7aaa5a62015-03-04 16:36:00 -0700110#ifndef CONFIG_ARM64
Allen Martin12b7b702012-08-31 08:30:12 +0000111static void enable_scu(void)
Tom Warren74652cf2011-04-14 12:18:06 +0000112{
113 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
114 u32 reg;
115
Tom Warrendbc000b2013-05-23 12:26:18 +0000116 /* Only enable the SCU on T20/T25 */
117 if (tegra_get_chip() != CHIPID_TEGRA20)
118 return;
119
Tom Warren74652cf2011-04-14 12:18:06 +0000120 /* If SCU already setup/enabled, return */
121 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
122 return;
123
124 /* Invalidate all ways for all processors */
125 writel(0xFFFF, &scu->scu_inv_all);
126
127 /* Enable SCU - bit 0 */
128 reg = readl(&scu->scu_ctrl);
129 reg |= SCU_CTRL_ENABLE;
130 writel(reg, &scu->scu_ctrl);
131}
132
Tom Warren76e350b2012-05-30 14:06:09 -0700133static u32 get_odmdata(void)
134{
135 /*
136 * ODMDATA is stored in the BCT in IRAM by the BootROM.
137 * The BCT start and size are stored in the BIT in IRAM.
138 * Read the data @ bct_start + (bct_size - 12). This works
Tom Warren2f5dac92014-01-24 12:46:16 -0700139 * on BCTs for currently supported SoCs, which are locked down.
140 * If this changes in new chips, we can revisit this algorithm.
Tom Warren76e350b2012-05-30 14:06:09 -0700141 */
Thierry Redingf49357b2015-07-22 15:58:05 -0600142 unsigned long bct_start;
143 u32 odmdata;
Tom Warren76e350b2012-05-30 14:06:09 -0700144
Tom Warrenb2871032012-12-11 13:34:15 +0000145 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
Tom Warren76e350b2012-05-30 14:06:09 -0700146 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
147
148 return odmdata;
149}
150
Allen Martin12b7b702012-08-31 08:30:12 +0000151static void init_pmc_scratch(void)
Tom Warren74652cf2011-04-14 12:18:06 +0000152{
Tom Warren29f3e3f2012-09-04 17:00:24 -0700153 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
Tom Warren76e350b2012-05-30 14:06:09 -0700154 u32 odmdata;
Tom Warren74652cf2011-04-14 12:18:06 +0000155 int i;
156
157 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
158 for (i = 0; i < 23; i++)
159 writel(0, &pmc->pmc_scratch1+i);
160
161 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
Tom Warren76e350b2012-05-30 14:06:09 -0700162 odmdata = get_odmdata();
163 writel(odmdata, &pmc->pmc_scratch20);
Tom Warren74652cf2011-04-14 12:18:06 +0000164}
165
Ian Campbell73169872015-04-21 07:18:36 +0200166#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
167void protect_secure_section(void)
168{
169 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
170
171 /* Must be MB aligned */
172 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF);
173 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF);
174
175 writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0);
176 writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1);
177}
178#endif
179
Thierry Reding79cf6442015-04-21 07:18:38 +0200180#if defined(CONFIG_ARMV7_NONSEC)
181static void smmu_flush(struct mc_ctlr *mc)
182{
183 (void)readl(&mc->mc_smmu_config);
184}
185
186static void smmu_enable(void)
187{
188 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
189 u32 value;
190
191 /*
192 * Enable translation for all clients since access to this register
193 * is restricted to TrustZone-secured requestors. The kernel will use
194 * the per-SWGROUP enable bits to enable or disable translations.
195 */
196 writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
197 writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
198 writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
199 writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
200
201 /*
202 * Enable SMMU globally since access to this register is restricted
203 * to TrustZone-secured requestors.
204 */
205 value = readl(&mc->mc_smmu_config);
206 value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
207 writel(value, &mc->mc_smmu_config);
208
209 smmu_flush(mc);
210}
211#else
212static void smmu_enable(void)
213{
214}
215#endif
216
Allen Martin12b7b702012-08-31 08:30:12 +0000217void s_init(void)
Tom Warren74652cf2011-04-14 12:18:06 +0000218{
Simon Glass210576f2011-11-05 03:56:50 +0000219 /* Init PMC scratch memory */
220 init_pmc_scratch();
Tom Warren74652cf2011-04-14 12:18:06 +0000221
Simon Glass210576f2011-11-05 03:56:50 +0000222 enable_scu();
223
Tom Warrend0edce42013-03-25 16:22:26 -0700224 /* init the cache */
225 config_cache();
Bryan Wudf3443d2014-06-24 11:45:29 +0900226
Thierry Reding79cf6442015-04-21 07:18:38 +0200227 /* enable SMMU */
228 smmu_enable();
Tom Warren74652cf2011-04-14 12:18:06 +0000229}
Tom Warren7aaa5a62015-03-04 16:36:00 -0700230#endif