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Michal Simek6ded73a2016-09-19 10:41:55 +02001menu "FPGA support"
2
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05303config FPGA
4 bool
5
Patrick Bruenn98d62e62016-11-04 11:57:02 +01006config FPGA_ALTERA
7 bool "Enable Altera FPGA drivers"
8 select FPGA
9 help
10 Say Y here to enable the Altera FPGA driver
11
12 This provides basic infrastructure to support Altera FPGA devices.
13 Enable Altera FPGA specific functions which includes bitstream
14 (in BIT format), fpga and device validation.
15
Tien Fong Cheefa23ba12017-07-26 13:05:40 +080016config FPGA_SOCFPGA
17 bool "Enable Gen5 and Arria10 common FPGA drivers"
18 select FPGA_ALTERA
19 help
20 Say Y here to enable the Gen5 and Arria10 common FPGA driver
21
22 This provides common functionality for Gen5 and Arria10 devices.
23
Tom Rini6e52cb22022-06-12 20:02:00 -040024config FPGA_STRATIX_V
25 bool "Enable Stratix V FPGA drivers"
26 depends on FPGA_ALTERA
27 help
28 Say Y here to enable the Altera Stratix V FPGA specific driver.
29
Patrick Bruenn98d62e62016-11-04 11:57:02 +010030config FPGA_CYCLON2
31 bool "Enable Altera FPGA driver for Cyclone II"
32 depends on FPGA_ALTERA
33 help
34 Say Y here to enable the Altera Cyclone II FPGA specific driver
35
36 This provides common functionality for Altera Cyclone II devices.
37 Enable FPGA driver for loading bitstream in BIT and BIN format
38 on Altera Cyclone II device.
39
Chee Hong Angd2170162020-08-07 11:50:03 +080040config FPGA_INTEL_SDM_MAILBOX
41 bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
Siew Chin Lim9a5bbdf2021-03-01 20:04:10 +080042 depends on TARGET_SOCFPGA_SOC64
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080043 select FPGA_ALTERA
44 help
Chee Hong Angd2170162020-08-07 11:50:03 +080045 Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080046
Chee Hong Angd2170162020-08-07 11:50:03 +080047 This provides common functionality for Intel FPGA devices.
48 Enable FPGA driver for writing full bitstream into Intel FPGA
49 devices through SDM (Secure Device Manager) Mailbox.
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080050
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053051config FPGA_XILINX
52 bool "Enable Xilinx FPGA drivers"
53 select FPGA
54 help
55 Enable Xilinx FPGA specific functions which includes bitstream
56 (in BIT format), fpga and device validation.
57
58config FPGA_ZYNQMPPL
59 bool "Enable Xilinx FPGA driver for ZynqMP"
60 depends on FPGA_XILINX
61 help
62 Enable FPGA driver for loading bitstream in BIT and BIN format
63 on Xilinx Zynq UltraScale+ (ZynqMP) device.
64
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053065config FPGA_VERSALPL
66 bool "Enable Xilinx FPGA driver for Versal"
67 depends on FPGA_XILINX
68 help
69 Enable FPGA driver for loading bitstream in PDI format on Xilinx
70 Versal device. PDI is a new programmable device image format for
71 Versal. The bitstream will only be generated as PDI for Versal
72 platform.
73
Vipul Kumarf4158342018-02-16 18:02:49 +053074config FPGA_SPARTAN3
Michal Simeka225f812018-07-23 15:59:55 +020075 bool "Enable Spartan3 FPGA driver"
Robert Hancock25d63a32019-06-18 09:47:13 -060076 depends on FPGA_XILINX
Michal Simeka225f812018-07-23 15:59:55 +020077 help
78 Enable Spartan3 FPGA driver for loading in BIT format.
Vipul Kumarf4158342018-02-16 18:02:49 +053079
Robert Hancock25d63a32019-06-18 09:47:13 -060080config FPGA_VIRTEX2
81 bool "Enable Xilinx Virtex-II and later FPGA driver"
82 depends on FPGA_XILINX
83 help
84 Enable Virtex-II FPGA driver for loading in BIT format. This driver
85 also supports many newer Xilinx FPGA families.
86
Vipul Kumar3990c9d2018-02-16 18:02:51 +053087config FPGA_ZYNQPL
Michal Simeka225f812018-07-23 15:59:55 +020088 bool "Enable Xilinx FPGA for Zynq"
89 depends on ARCH_ZYNQ
90 help
91 Enable FPGA driver for loading bitstream in BIT and BIN format
92 on Xilinx Zynq devices.
Vipul Kumar3990c9d2018-02-16 18:02:51 +053093
Alexander Dahle8ffc1d2022-07-21 15:31:21 +020094config SYS_FPGA_CHECK_CTRLC
95 bool "Allow Control-C to interrupt FPGA configuration"
96 depends on FPGA
97 help
98 User can interrupt FPGA configuration by pressing CTRL+C.
99
Alexander Dahl8c09cb62022-07-21 15:31:22 +0200100config SYS_FPGA_PROG_FEEDBACK
101 bool "Progress output during FPGA configuration"
102 depends on FPGA
103 default y if FPGA_VIRTEX2
104 help
105 Enable printing of hash marks during FPGA configuration.
106
Oleksandr Suvorovfb2b8852022-07-22 17:16:02 +0300107config FPGA_LOAD_SECURE
108 bool "Enable loading secure bitstreams"
109 depends on FPGA
110 help
111 Enables the fpga loads() functions that are used to load secure
112 (authenticated or encrypted or both) bitstreams on to FPGA.
113
114config SPL_FPGA_LOAD_SECURE
115 bool "Enable loading secure bitstreams for SPL"
116 depends on SPL_FPGA
117 help
118 Enables the fpga loads() functions that are used to load secure
119 (authenticated or encrypted or both) bitstreams on to FPGA.
120
Michal Simek6ded73a2016-09-19 10:41:55 +0200121endmenu