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Masahiro Yamada238bd0b2015-01-13 12:44:37 +09001/*
Masahiro Yamada4e3d8402016-07-19 21:56:13 +09002 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada238bd0b2015-01-13 12:44:37 +09005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +09009#include <linux/errno.h>
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +090010#include <linux/io.h>
Masahiro Yamada68578582017-01-28 06:53:56 +090011#include <linux/iopoll.h>
Masahiro Yamada336399f2016-03-24 22:32:40 +090012#include <linux/sizes.h>
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +090013#include <linux/types.h>
14#include <dm.h>
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090015#include <i2c.h>
16#include <fdtdec.h>
17
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090018struct uniphier_fi2c_regs {
19 u32 cr; /* control register */
20#define I2C_CR_MST (1 << 3) /* master mode */
21#define I2C_CR_STA (1 << 2) /* start condition */
22#define I2C_CR_STO (1 << 1) /* stop condition */
23#define I2C_CR_NACK (1 << 0) /* not ACK */
24 u32 dttx; /* send FIFO (write-only) */
25#define dtrx dttx /* receive FIFO (read-only) */
26#define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
27#define I2C_DTTX_RD (1 << 0) /* read */
28 u32 __reserved; /* no register at offset 0x08 */
29 u32 slad; /* slave address */
30 u32 cyc; /* clock cycle control */
31 u32 lctl; /* clock low period control */
32 u32 ssut; /* restart/stop setup time control */
33 u32 dsut; /* data setup time control */
34 u32 intr; /* interrupt status */
35 u32 ie; /* interrupt enable */
36 u32 ic; /* interrupt clear */
37#define I2C_INT_TE (1 << 9) /* TX FIFO empty */
38#define I2C_INT_RB (1 << 4) /* received specified bytes */
39#define I2C_INT_NA (1 << 2) /* no answer */
40#define I2C_INT_AL (1 << 1) /* arbitration lost */
41 u32 sr; /* status register */
42#define I2C_SR_DB (1 << 12) /* device busy */
43#define I2C_SR_BB (1 << 8) /* bus busy */
44#define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
45#define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
46#define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
47#define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
48 u32 __reserved2; /* no register at offset 0x30 */
49 u32 rst; /* reset control */
50#define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
51#define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
52#define I2C_RST_RST (1 << 0) /* forcible bus reset */
53 u32 bm; /* bus monitor */
54 u32 noise; /* noise filter control */
55 u32 tbc; /* Tx byte count setting */
56 u32 rbc; /* Rx byte count setting */
57 u32 tbcm; /* Tx byte count monitor */
58 u32 rbcm; /* Rx byte count monitor */
59 u32 brst; /* bus reset */
60#define I2C_BRST_FOEN (1 << 1) /* normal operation */
61#define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
62};
63
64#define FIOCLK 50000000
65
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +090066struct uniphier_fi2c_priv {
67 struct udevice *dev;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090068 struct uniphier_fi2c_regs __iomem *regs; /* register base */
69 unsigned long fioclk; /* internal operation clock */
70 unsigned long timeout; /* time out (us) */
71};
72
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +090073static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090074{
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +090075 writel(I2C_RST_RST, &priv->regs->rst);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090076}
77
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +090078static int uniphier_fi2c_check_bus_busy(struct uniphier_fi2c_priv *priv)
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090079{
Masahiro Yamada68578582017-01-28 06:53:56 +090080 u32 val;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090081 int ret;
82
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +090083 ret = readl_poll_timeout(&priv->regs->sr, val, !(val & I2C_SR_DB), 100);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090084 if (ret < 0) {
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +090085 dev_dbg(priv->dev, "error: device busy too long. reset...\n");
86 uniphier_fi2c_reset(priv);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090087 }
88
89 return ret;
90}
91
92static int uniphier_fi2c_probe(struct udevice *dev)
93{
94 fdt_addr_t addr;
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +090095 struct uniphier_fi2c_priv *priv = dev_get_priv(dev);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090096
Simon Glassa821c4a2017-05-17 17:18:05 -060097 addr = devfdt_get_addr(dev);
Masahiro Yamada336399f2016-03-24 22:32:40 +090098 if (addr == FDT_ADDR_T_NONE)
99 return -EINVAL;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900100
Masahiro Yamada4e3d8402016-07-19 21:56:13 +0900101 priv->regs = devm_ioremap(dev, addr, SZ_128);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900102 if (!priv->regs)
103 return -ENOMEM;
104
105 priv->fioclk = FIOCLK;
106
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900107 priv->dev = dev;
108
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900109 /* bus forcible reset */
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900110 uniphier_fi2c_reset(priv);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900111
112 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
113
114 return 0;
115}
116
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900117static int wait_for_irq(struct uniphier_fi2c_priv *priv, u32 flags,
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900118 bool *stop)
119{
120 u32 irq;
Masahiro Yamada68578582017-01-28 06:53:56 +0900121 int ret;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900122
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900123 ret = readl_poll_timeout(&priv->regs->intr, irq, irq & flags,
124 priv->timeout);
Masahiro Yamada68578582017-01-28 06:53:56 +0900125 if (ret < 0) {
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900126 dev_dbg(priv->dev, "error: time out\n");
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900127 return ret;
128 }
129
130 if (irq & I2C_INT_AL) {
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900131 dev_dbg(priv->dev, "error: arbitration lost\n");
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900132 *stop = false;
133 return ret;
134 }
135
136 if (irq & I2C_INT_NA) {
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900137 dev_dbg(priv->dev, "error: no answer\n");
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900138 return ret;
139 }
140
141 return 0;
142}
143
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900144static int issue_stop(struct uniphier_fi2c_priv *priv, int old_ret)
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900145{
146 int ret;
147
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900148 dev_dbg(priv->dev, "stop condition\n");
149 writel(I2C_CR_MST | I2C_CR_STO, &priv->regs->cr);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900150
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900151 ret = uniphier_fi2c_check_bus_busy(priv);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900152 if (ret < 0)
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900153 dev_dbg(priv->dev, "error: device busy after operation\n");
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900154
155 return old_ret ? old_ret : ret;
156}
157
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900158static int uniphier_fi2c_transmit(struct uniphier_fi2c_priv *priv, uint addr,
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900159 uint len, const u8 *buf, bool *stop)
160{
161 int ret;
162 const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900163 struct uniphier_fi2c_regs __iomem *regs = priv->regs;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900164
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900165 dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900166
167 writel(I2C_DTTX_CMD | addr << 1, &regs->dttx);
168
169 writel(irq_flags, &regs->ie);
170 writel(irq_flags, &regs->ic);
171
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900172 dev_dbg(priv->dev, "start condition\n");
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900173 writel(I2C_CR_MST | I2C_CR_STA, &regs->cr);
174
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900175 ret = wait_for_irq(priv, irq_flags, stop);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900176 if (ret < 0)
177 goto error;
178
179 while (len--) {
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900180 dev_dbg(priv->dev, "sending %x\n", *buf);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900181 writel(*buf++, &regs->dttx);
182
183 writel(irq_flags, &regs->ic);
184
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900185 ret = wait_for_irq(priv, irq_flags, stop);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900186 if (ret < 0)
187 goto error;
188 }
189
190error:
191 writel(irq_flags, &regs->ic);
192
193 if (*stop)
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900194 ret = issue_stop(priv, ret);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900195
196 return ret;
197}
198
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900199static int uniphier_fi2c_receive(struct uniphier_fi2c_priv *priv, uint addr,
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900200 uint len, u8 *buf, bool *stop)
201{
202 int ret = 0;
203 const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900204 struct uniphier_fi2c_regs __iomem *regs = priv->regs;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900205
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900206 dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900207
208 /*
209 * In case 'len == 0', only the slave address should be sent
210 * for probing, which is covered by the transmit function.
211 */
212 if (len == 0)
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900213 return uniphier_fi2c_transmit(priv, addr, len, buf, stop);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900214
215 writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, &regs->dttx);
216
217 writel(0, &regs->rbc);
218 writel(irq_flags, &regs->ie);
219 writel(irq_flags, &regs->ic);
220
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900221 dev_dbg(priv->dev, "start condition\n");
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900222 writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
223 &regs->cr);
224
225 while (len--) {
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900226 ret = wait_for_irq(priv, irq_flags, stop);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900227 if (ret < 0)
228 goto error;
229
230 *buf++ = readl(&regs->dtrx);
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900231 dev_dbg(priv->dev, "received %x\n", *(buf - 1));
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900232
233 if (len == 1)
234 writel(I2C_CR_MST | I2C_CR_NACK, &regs->cr);
235
236 writel(irq_flags, &regs->ic);
237 }
238
239error:
240 writel(irq_flags, &regs->ic);
241
242 if (*stop)
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900243 ret = issue_stop(priv, ret);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900244
245 return ret;
246}
247
248static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
249 int nmsgs)
250{
251 int ret;
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900252 struct uniphier_fi2c_priv *priv = dev_get_priv(bus);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900253 bool stop;
254
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900255 ret = uniphier_fi2c_check_bus_busy(priv);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900256 if (ret < 0)
257 return ret;
258
259 for (; nmsgs > 0; nmsgs--, msg++) {
260 /* If next message is read, skip the stop condition */
261 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
262
263 if (msg->flags & I2C_M_RD)
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900264 ret = uniphier_fi2c_receive(priv, msg->addr, msg->len,
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900265 msg->buf, &stop);
266 else
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900267 ret = uniphier_fi2c_transmit(priv, msg->addr, msg->len,
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900268 msg->buf, &stop);
269
270 if (ret < 0)
271 break;
272 }
273
274 return ret;
275}
276
277static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
278{
279 int ret;
280 unsigned int clk_count;
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900281 struct uniphier_fi2c_priv *priv = dev_get_priv(bus);
282 struct uniphier_fi2c_regs __iomem *regs = priv->regs;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900283
284 /* max supported frequency is 400 kHz */
285 if (speed > 400000)
286 return -EINVAL;
287
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900288 ret = uniphier_fi2c_check_bus_busy(priv);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900289 if (ret < 0)
290 return ret;
291
292 /* make sure the bus is idle when changing the frequency */
293 writel(I2C_BRST_RSCLO, &regs->brst);
294
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900295 clk_count = priv->fioclk / speed;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900296
297 writel(clk_count, &regs->cyc);
298 writel(clk_count / 2, &regs->lctl);
299 writel(clk_count / 2, &regs->ssut);
300 writel(clk_count / 16, &regs->dsut);
301
302 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &regs->brst);
303
304 /*
305 * Theoretically, each byte can be transferred in
306 * 1000000 * 9 / speed usec.
307 * This time out value is long enough.
308 */
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900309 priv->timeout = 100000000L / speed;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900310
311 return 0;
312}
313
314static const struct dm_i2c_ops uniphier_fi2c_ops = {
315 .xfer = uniphier_fi2c_xfer,
316 .set_bus_speed = uniphier_fi2c_set_bus_speed,
317};
318
319static const struct udevice_id uniphier_fi2c_of_match[] = {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900320 { .compatible = "socionext,uniphier-fi2c" },
321 { /* sentinel */ }
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900322};
323
324U_BOOT_DRIVER(uniphier_fi2c) = {
325 .name = "uniphier-fi2c",
326 .id = UCLASS_I2C,
327 .of_match = uniphier_fi2c_of_match,
328 .probe = uniphier_fi2c_probe,
Masahiro Yamada2b7b2df2017-10-13 19:21:58 +0900329 .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_priv),
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900330 .ops = &uniphier_fi2c_ops,
331};