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Shaohui Xie02b5d2e2015-11-11 17:58:37 +08001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1043AQDS_H__
8#define __LS1043AQDS_H__
9
10#include "ls1043a_common.h"
11
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080012#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13#define CONFIG_SYS_TEXT_BASE 0x82000000
Qianyu Gongb0f20ca2016-01-25 15:16:07 +080014#elif defined(CONFIG_QSPI_BOOT)
Alison Wanga9a5cef2017-05-16 10:45:58 +080015#define CONFIG_SYS_TEXT_BASE 0x40100000
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080016#else
17#define CONFIG_SYS_TEXT_BASE 0x60100000
18#endif
19
20#ifndef __ASSEMBLY__
21unsigned long get_board_sys_clk(void);
22unsigned long get_board_ddr_clk(void);
23#endif
24
Qianyu Gong581ff002016-06-13 11:20:31 +080025#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
26#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080027
28#define CONFIG_SKIP_LOWLEVEL_INIT
29
30#define CONFIG_LAYERSCAPE_NS_ACCESS
31
32#define CONFIG_DIMM_SLOTS_PER_CTLR 1
33/* Physical Memory Map */
34#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Shaohui Xie58e4ad12016-01-04 11:03:44 +080035#define CONFIG_NR_DRAM_BANKS 2
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080036
37#define CONFIG_DDR_SPD
38#define SPD_EEPROM_ADDRESS 0x51
39#define CONFIG_SYS_SPD_BUS_NUM 0
40
Hou Zhiqiangdc760ae2017-02-06 11:29:00 +080041#ifndef CONFIG_SPL
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080042#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
Hou Zhiqiangdc760ae2017-02-06 11:29:00 +080043#endif
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080044
45#define CONFIG_DDR_ECC
46#ifdef CONFIG_DDR_ECC
47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49#endif
50
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080051#ifdef CONFIG_SYS_DPAA_FMAN
52#define CONFIG_FMAN_ENET
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080053#define CONFIG_PHY_VITESSE
54#define CONFIG_PHY_REALTEK
55#define CONFIG_PHYLIB_10G
56#define RGMII_PHY1_ADDR 0x1
57#define RGMII_PHY2_ADDR 0x2
58#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
59#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
60#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
61#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
62/* PHY address on QSGMII riser card on slot 1 */
63#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
64#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
65#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
66#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
67/* PHY address on QSGMII riser card on slot 2 */
68#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
69#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
70#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
71#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
72#endif
73
74#ifdef CONFIG_RAMBOOT_PBL
75#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
76#endif
77
78#ifdef CONFIG_NAND_BOOT
79#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
80#endif
81
82#ifdef CONFIG_SD_BOOT
Gong Qianyu166ef1e2016-01-25 15:16:06 +080083#ifdef CONFIG_SD_BOOT_QSPI
84#define CONFIG_SYS_FSL_PBL_RCW \
85 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
86#else
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080087#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
88#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +080089#endif
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080090
Wenbin Song2970e142016-01-21 17:14:55 +080091/* LPUART */
92#ifdef CONFIG_LPUART
93#define CONFIG_LPUART_32B_REG
94#endif
95
Tang Yuantian989c5f02015-12-09 15:32:18 +080096/* SATA */
Tang Yuantian989c5f02015-12-09 15:32:18 +080097#define CONFIG_SCSI_AHCI_PLAT
Tang Yuantian989c5f02015-12-09 15:32:18 +080098
Wenbin Songceded372016-03-09 13:38:25 +080099/* EEPROM */
100#define CONFIG_ID_EEPROM
101#define CONFIG_SYS_I2C_EEPROM_NXID
102#define CONFIG_SYS_EEPROM_BUS_NUM 0
103#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
104#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
105#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
106#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
107
Tang Yuantian989c5f02015-12-09 15:32:18 +0800108#define CONFIG_SYS_SATA AHCI_BASE_ADDR
109
110#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
111#define CONFIG_SYS_SCSI_MAX_LUN 1
112#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
113 CONFIG_SYS_SCSI_MAX_LUN)
114
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800115/*
116 * IFC Definitions
117 */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800118#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800119#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
120#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
121 CSPR_PORT_SIZE_16 | \
122 CSPR_MSEL_NOR | \
123 CSPR_V)
124#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
125#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
126 + 0x8000000) | \
127 CSPR_PORT_SIZE_16 | \
128 CSPR_MSEL_NOR | \
129 CSPR_V)
130#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
131
132#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
133 CSOR_NOR_TRHZ_80)
134#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
135 FTIM0_NOR_TEADC(0x5) | \
136 FTIM0_NOR_TEAHC(0x5))
137#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
138 FTIM1_NOR_TRAD_NOR(0x1a) | \
139 FTIM1_NOR_TSEQRAD_NOR(0x13))
140#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
141 FTIM2_NOR_TCH(0x4) | \
142 FTIM2_NOR_TWPH(0xe) | \
143 FTIM2_NOR_TWP(0x1c))
144#define CONFIG_SYS_NOR_FTIM3 0
145
Wenbin Song1b245d92016-04-01 17:28:41 +0800146#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800147#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
148#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
150
151#define CONFIG_SYS_FLASH_EMPTY_INFO
152#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
153 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
154
155#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
156#define CONFIG_SYS_WRITE_SWAPPED_DATA
157
158/*
159 * NAND Flash Definitions
160 */
161#define CONFIG_NAND_FSL_IFC
162
163#define CONFIG_SYS_NAND_BASE 0x7e800000
164#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
165
166#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
167
168#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
169 | CSPR_PORT_SIZE_8 \
170 | CSPR_MSEL_NAND \
171 | CSPR_V)
172#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
173#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
174 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
175 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
176 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
177 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
178 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
179 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
180
181#define CONFIG_SYS_NAND_ONFI_DETECTION
182
183#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
184 FTIM0_NAND_TWP(0x18) | \
185 FTIM0_NAND_TWCHT(0x7) | \
186 FTIM0_NAND_TWH(0xa))
187#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
188 FTIM1_NAND_TWBE(0x39) | \
189 FTIM1_NAND_TRR(0xe) | \
190 FTIM1_NAND_TRP(0x18))
191#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
192 FTIM2_NAND_TREH(0xa) | \
193 FTIM2_NAND_TWHRE(0x1e))
194#define CONFIG_SYS_NAND_FTIM3 0x0
195
196#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
197#define CONFIG_SYS_MAX_NAND_DEVICE 1
198#define CONFIG_MTD_NAND_VERIFY_WRITE
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800199
200#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800201#endif
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800202
203#ifdef CONFIG_NAND_BOOT
204#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
205#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
206#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
207#endif
208
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800209#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800210#define CONFIG_QIXIS_I2C_ACCESS
Qianyu Gong581ff002016-06-13 11:20:31 +0800211#define CONFIG_SYS_I2C_EARLY_INIT
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800212#endif
213
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800214/*
215 * QIXIS Definitions
216 */
217#define CONFIG_FSL_QIXIS
218
219#ifdef CONFIG_FSL_QIXIS
220#define QIXIS_BASE 0x7fb00000
221#define QIXIS_BASE_PHYS QIXIS_BASE
222#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
223#define QIXIS_LBMAP_SWITCH 6
224#define QIXIS_LBMAP_MASK 0x0f
225#define QIXIS_LBMAP_SHIFT 0
226#define QIXIS_LBMAP_DFLTBANK 0x00
227#define QIXIS_LBMAP_ALTBANK 0x04
Gong Qianyuee2a4ee2015-12-31 18:29:04 +0800228#define QIXIS_LBMAP_NAND 0x09
229#define QIXIS_LBMAP_SD 0x00
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800230#define QIXIS_LBMAP_SD_QSPI 0xff
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800231#define QIXIS_LBMAP_QSPI 0xff
Gong Qianyuee2a4ee2015-12-31 18:29:04 +0800232#define QIXIS_RCW_SRC_NAND 0x106
233#define QIXIS_RCW_SRC_SD 0x040
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800234#define QIXIS_RCW_SRC_QSPI 0x045
Gong Qianyua4b7d682015-12-31 18:29:03 +0800235#define QIXIS_RST_CTL_RESET 0x41
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800236#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
237#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
238#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
239
240#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
241#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
242 CSPR_PORT_SIZE_8 | \
243 CSPR_MSEL_GPCM | \
244 CSPR_V)
245#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
246#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
247 CSOR_NOR_NOR_MODE_AVD_NOR | \
248 CSOR_NOR_TRHZ_80)
249
250/*
251 * QIXIS Timing parameters for IFC GPCM
252 */
253#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
254 FTIM0_GPCM_TEADC(0x20) | \
255 FTIM0_GPCM_TEAHC(0x10))
256#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
257 FTIM1_GPCM_TRAD(0x1f))
258#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
259 FTIM2_GPCM_TCH(0x8) | \
260 FTIM2_GPCM_TWP(0xf0))
261#define CONFIG_SYS_FPGA_FTIM3 0x0
262#endif
263
264#ifdef CONFIG_NAND_BOOT
265#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
266#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
267#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
268#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
269#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
270#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
271#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
272#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
273#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
274#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
275#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
276#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
277#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
278#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
279#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
280#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
281#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
282#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
283#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
284#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
285#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
286#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
287#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
288#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
289#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
290#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
291#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
292#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
293#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
294#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
295#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
296#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
297#else
298#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
299#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
300#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
301#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
302#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
303#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
304#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
305#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
306#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
307#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
308#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
309#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
310#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
311#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
312#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
313#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
314#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
315#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
316#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
317#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
318#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
319#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
320#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
321#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
322#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
323#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
324#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
325#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
326#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
327#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
328#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
329#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
330#endif
331
332/*
333 * I2C bus multiplexer
334 */
335#define I2C_MUX_PCA_ADDR_PRI 0x77
336#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
337#define I2C_RETIMER_ADDR 0x18
338#define I2C_MUX_CH_DEFAULT 0x8
339#define I2C_MUX_CH_CH7301 0xC
340#define I2C_MUX_CH5 0xD
341#define I2C_MUX_CH7 0xF
342
343#define I2C_MUX_CH_VOL_MONITOR 0xa
344
345/* Voltage monitor on channel 2*/
346#define I2C_VOL_MONITOR_ADDR 0x40
347#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
348#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
349#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
350
351#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
352#ifndef CONFIG_SPL_BUILD
353#define CONFIG_VID
354#endif
355#define CONFIG_VOL_MONITOR_IR36021_SET
356#define CONFIG_VOL_MONITOR_INA220
357/* The lowest and highest voltage allowed for LS1043AQDS */
358#define VDD_MV_MIN 819
359#define VDD_MV_MAX 1212
360
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800361/* QSPI device */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800362#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800363#define CONFIG_FSL_QSPI
364#ifdef CONFIG_FSL_QSPI
365#define CONFIG_SPI_FLASH_SPANSION
366#define FSL_QSPI_FLASH_SIZE (1 << 24)
367#define FSL_QSPI_FLASH_NUM 2
368#endif
369#endif
370
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800371/*
372 * Miscellaneous configurable options
373 */
374#define CONFIG_MISC_INIT_R
375#define CONFIG_SYS_LONGHELP /* undef to save memory */
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800376#define CONFIG_AUTO_COMPLETE
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800377
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800378#define CONFIG_SYS_MEMTEST_START 0x80000000
379#define CONFIG_SYS_MEMTEST_END 0x9fffffff
380
381#define CONFIG_SYS_HZ 1000
382
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800383#define CONFIG_SYS_INIT_SP_OFFSET \
384 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
385
386#ifdef CONFIG_SPL_BUILD
387#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
388#else
389#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
390#endif
391
392/*
393 * Environment
394 */
395#define CONFIG_ENV_OVERWRITE
396
397#ifdef CONFIG_NAND_BOOT
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800398#define CONFIG_ENV_SIZE 0x2000
Alison Wanga9a5cef2017-05-16 10:45:58 +0800399#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800400#elif defined(CONFIG_SD_BOOT)
Alison Wanga9a5cef2017-05-16 10:45:58 +0800401#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800402#define CONFIG_SYS_MMC_ENV_DEV 0
403#define CONFIG_ENV_SIZE 0x2000
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800404#elif defined(CONFIG_QSPI_BOOT)
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800405#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Alison Wanga9a5cef2017-05-16 10:45:58 +0800406#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800407#define CONFIG_ENV_SECT_SIZE 0x10000
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800408#else
Alison Wanga9a5cef2017-05-16 10:45:58 +0800409#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800410#define CONFIG_ENV_SECT_SIZE 0x20000
411#define CONFIG_ENV_SIZE 0x20000
412#endif
413
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800414#define CONFIG_CMDLINE_TAG
415
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530416#include <asm/fsl_secure_boot.h>
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Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800418#endif /* __LS1043AQDS_H__ */