blob: d5a398d1110c23b9b00106fcf92d32ef59d8c3ef [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the CU824 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8245 1
46#define CONFIG_BMW 1
47
wdenkc837dcb2004-01-20 23:12:12 +000048#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
49
50#define CONFIG_BCM570x 1 /* Use Broadcom BCM570x Ethernet Driver */
wdenkc6097192002-11-03 00:24:07 +000051#define CONFIG_TIGON3 1
52
53#define CONFIG_CONS_INDEX 1
54#define CONFIG_BAUDRATE 9600
55#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
56
57#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
58
59#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
60#define CONFIG_BOOTDELAY 5
61
62#define CFG_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */
63#define DOC_PASSIVE_PROBE 1
64#define CFG_DOC_SUPPORT_2000 1
65#define CFG_DOC_SUPPORT_MILLENNIUM 1
66#define CFG_DOC_SHORT_TIMEOUT 1
Jon Loeligerde8b2a62007-07-05 19:32:07 -050067
68
69/*
Jon Loeliger11799432007-07-10 09:02:57 -050070 * BOOTP options
71 */
72#define CONFIG_BOOTP_BOOTFILESIZE
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76
77
78/*
Jon Loeligerde8b2a62007-07-05 19:32:07 -050079 * Command line configuration.
80 */
81#include <config_cmd_default.h>
82
83#define CONFIG_CMD_DATE
84#define CONFIG_CMD_DOC
85#define CONFIG_CMD_ELF
86
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010087
Jon Loeliger11799432007-07-10 09:02:57 -050088/* CONFIG_CMD_DOC required legacy NAND support */
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +020089#define CONFIG_NAND_LEGACY
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010090
wdenkc6097192002-11-03 00:24:07 +000091#if 0
wdenkc6097192002-11-03 00:24:07 +000092#define CONFIG_PCI 1
93#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
94#endif
95
wdenkc6097192002-11-03 00:24:07 +000096/*
97 * Miscellaneous configurable options
98 */
99#define CFG_LONGHELP /* undef to save memory */
100#define CFG_PROMPT "=>" /* Monitor Command Prompt */
101#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
102
103/* Print Buffer Size
104 */
105#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
106
107#define CFG_MAXARGS 8 /* Max number of command args */
108#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
109#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
110
111/*-----------------------------------------------------------------------
112 * Start addresses for the final memory configuration
113 * (Set up by the startup code)
114 * Please note that CFG_SDRAM_BASE _must_ start at 0
115 */
116#define CFG_SDRAM_BASE 0x00000000
117
118#define CFG_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */
119#define CFG_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */
120#define CFG_FLASH_BASE CFG_MONITOR_BASE
121#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM }
122
123/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
124 * reset vector is actually located at FFB00100, but the 8245
125 * takes care of us.
126 */
127#define CFG_RESET_ADDRESS 0xFFF00100
128
129#define CFG_EUMB_ADDR 0xFC000000
130
131#define CFG_MONITOR_BASE TEXT_BASE
132
133#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
134#define CFG_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
135
136#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
137#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
138
139 /* Maximum amount of RAM.
140 */
141#define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */
142
143
144#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
145#undef CFG_RAMBOOT
146#else
147#define CFG_RAMBOOT
148#endif
149
150
151/*-----------------------------------------------------------------------
152 * Definitions for initial stack pointer and data area
153 */
154#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
155#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
156#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
157#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
158#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
159
160/*
161 * Low Level Configuration Settings
162 * (address mappings, register initial values, etc.)
163 * You should know what you are doing if you make changes here.
164 * For the detail description refer to the MPC8240 user's manual.
165 */
166
167#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
168#define CFG_HZ 1000
169
170#define CFG_ETH_DEV_FN 0x7800
171#define CFG_ETH_IOBASE 0x00104000
172
173 /* Bit-field values for MCCR1.
174 */
175#define CFG_ROMNAL 0xf
176#define CFG_ROMFAL 0x1f
177#define CFG_DBUS_SIZE 0x3
178
179 /* Bit-field values for MCCR2.
180 */
181#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
182#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
183
184 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
185 */
186#define CFG_BSTOPRE 0 /* FIXME: was 192 */
187
188 /* Bit-field values for MCCR3.
189 */
190#define CFG_REFREC 2 /* Refresh to activate interval */
191
192 /* Bit-field values for MCCR4.
193 */
194#define CFG_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
195#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
196#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
197#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
198#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
199#define CFG_ACTORW 0xa /* FIXME was 2 */
200#define CFG_REGISTERD_TYPE_BUFFER 1
201
202#define CFG_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
203
204#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
205
206/* Memory bank settings.
207 * Only bits 20-29 are actually used from these vales to set the
208 * start/end addresses. The upper two bits will always be 0, and the lower
209 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
210 * address. Refer to the MPC8240 book.
211 */
212
213#define CFG_BANK0_START 0x00000000
214#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
215#define CFG_BANK0_ENABLE 1
216#define CFG_BANK1_START 0x3ff00000
217#define CFG_BANK1_END 0x3fffffff
218#define CFG_BANK1_ENABLE 0
219#define CFG_BANK2_START 0x3ff00000
220#define CFG_BANK2_END 0x3fffffff
221#define CFG_BANK2_ENABLE 0
222#define CFG_BANK3_START 0x3ff00000
223#define CFG_BANK3_END 0x3fffffff
224#define CFG_BANK3_ENABLE 0
225#define CFG_BANK4_START 0x3ff00000
226#define CFG_BANK4_END 0x3fffffff
227#define CFG_BANK4_ENABLE 0
228#define CFG_BANK5_START 0x3ff00000
229#define CFG_BANK5_END 0x3fffffff
230#define CFG_BANK5_ENABLE 0
231#define CFG_BANK6_START 0x3ff00000
232#define CFG_BANK6_END 0x3fffffff
233#define CFG_BANK6_ENABLE 0
234#define CFG_BANK7_START 0x3ff00000
235#define CFG_BANK7_END 0x3fffffff
236#define CFG_BANK7_ENABLE 0
237
238#define CFG_ODCR 0xff
239
240#define CONFIG_PCI 1 /* Include PCI support */
241#undef CONFIG_PCI_PNP
242
243/* PCI Memory space(s) */
244#define PCI_MEM_SPACE1_START 0x80000000
245#define PCI_MEM_SPACE2_START 0xfd000000
246
247/* ROM Spaces */
248#include "../board/bmw/bmw.h"
249
250/* BAT configuration */
251#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
252#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
253
254#define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
255#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
256
257#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
258#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
259
260#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
261#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
262
263#define CFG_DBAT0L CFG_IBAT0L
264#define CFG_DBAT0U CFG_IBAT0U
265#define CFG_DBAT1L CFG_IBAT1L
266#define CFG_DBAT1U CFG_IBAT1U
267#define CFG_DBAT2L CFG_IBAT2L
268#define CFG_DBAT2U CFG_IBAT2U
269#define CFG_DBAT3L CFG_IBAT3L
270#define CFG_DBAT3U CFG_IBAT3U
271
272/*
273 * For booting Linux, the board info and command line data
274 * have to be in the first 8 MB of memory, since this is
275 * the maximum mapped by the Linux kernel during initialization.
276 */
277#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
278
279/*
280 * FLASH organization
281 */
282#define CFG_MAX_FLASH_BANKS 0 /* Max number of flash banks */
283#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
284
285#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
286#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
287
288/*
289 * Warining: environment is not EMBEDDED in the U-Boot code.
290 * It's stored in flash separately.
291 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200292#define CONFIG_ENV_IS_IN_NVRAM 1
wdenkc6097192002-11-03 00:24:07 +0000293#define CONFIG_ENV_OVERWRITE 1
294#define CFG_NVRAM_ACCESS_ROUTINE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200295#define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */
296#define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */
297#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
wdenkc6097192002-11-03 00:24:07 +0000298
299/*
300 * Cache Configuration
301 */
302#define CFG_CACHELINE_SIZE 32
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500303#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000304# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
305#endif
306
307/*
308 * Internal Definitions
309 *
310 * Boot Flags
311 */
312#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
313#define BOOTFLAG_WARM 0x02 /* Software reboot */
314
315
316#endif /* __CONFIG_H */