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Cliff Cai716ebf42008-11-29 18:22:38 -05001/*
2 * Driver for Blackfin on-chip SDH controller
3 *
Cliff Caie54c8202009-11-20 08:24:43 +00004 * Copyright (c) 2008-2009 Analog Devices Inc.
Cliff Cai716ebf42008-11-29 18:22:38 -05005 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <common.h>
10#include <malloc.h>
11#include <part.h>
12#include <mmc.h>
13
14#include <asm/io.h>
15#include <asm/errno.h>
16#include <asm/byteorder.h>
17#include <asm/blackfin.h>
Mike Frysingera87589f2010-06-02 05:59:50 -040018#include <asm/portmux.h>
Cliff Cai716ebf42008-11-29 18:22:38 -050019#include <asm/mach-common/bits/sdh.h>
20#include <asm/mach-common/bits/dma.h>
21
Mike Frysingercca07412010-12-17 15:25:09 -050022#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
Cliff Cai716ebf42008-11-29 18:22:38 -050023# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
24# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
25# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
26# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
27# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
28# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
29# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
30# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
31# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
32# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
33# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
34# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
35# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
36# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
37# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
38# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
39# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
40# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
41# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
42# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
43# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
44# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
Mike Frysingera87589f2010-06-02 05:59:50 -040045# define PORTMUX_PINS \
46 { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
Cliff Cai716ebf42008-11-29 18:22:38 -050047#elif defined(__ADSPBF54x__)
48# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
49# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
50# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
51# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
Mike Frysingera87589f2010-06-02 05:59:50 -040052# define PORTMUX_PINS \
53 { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
Cliff Cai716ebf42008-11-29 18:22:38 -050054#else
55# error no support for this proc yet
56#endif
57
Cliff Cai716ebf42008-11-29 18:22:38 -050058static int
Cliff Caie54c8202009-11-20 08:24:43 +000059sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
Cliff Cai716ebf42008-11-29 18:22:38 -050060{
Mike Frysinger6815f542010-06-21 20:56:54 +000061 unsigned int status, timeout;
Cliff Caie54c8202009-11-20 08:24:43 +000062 int cmd = mmc_cmd->cmdidx;
63 int flags = mmc_cmd->resp_type;
64 int arg = mmc_cmd->cmdarg;
Mike Frysinger6815f542010-06-21 20:56:54 +000065 int ret;
66 u16 sdh_cmd;
Cliff Caie54c8202009-11-20 08:24:43 +000067
Mike Frysinger6815f542010-06-21 20:56:54 +000068 sdh_cmd = cmd | CMD_E;
Cliff Cai716ebf42008-11-29 18:22:38 -050069 if (flags & MMC_RSP_PRESENT)
70 sdh_cmd |= CMD_RSP;
Cliff Cai716ebf42008-11-29 18:22:38 -050071 if (flags & MMC_RSP_136)
72 sdh_cmd |= CMD_L_RSP;
73
74 bfin_write_SDH_ARGUMENT(arg);
Mike Frysinger6815f542010-06-21 20:56:54 +000075 bfin_write_SDH_COMMAND(sdh_cmd);
Cliff Cai716ebf42008-11-29 18:22:38 -050076
77 /* wait for a while */
Mike Frysinger6815f542010-06-21 20:56:54 +000078 timeout = 0;
Cliff Cai716ebf42008-11-29 18:22:38 -050079 do {
Mike Frysinger6815f542010-06-21 20:56:54 +000080 if (++timeout > 1000000) {
81 status = CMD_TIME_OUT;
82 break;
83 }
Cliff Cai716ebf42008-11-29 18:22:38 -050084 udelay(1);
85 status = bfin_read_SDH_STATUS();
86 } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
87 CMD_CRC_FAIL)));
88
89 if (flags & MMC_RSP_PRESENT) {
Cliff Caie54c8202009-11-20 08:24:43 +000090 mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
Cliff Cai716ebf42008-11-29 18:22:38 -050091 if (flags & MMC_RSP_136) {
Cliff Caie54c8202009-11-20 08:24:43 +000092 mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
93 mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
94 mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
Cliff Cai716ebf42008-11-29 18:22:38 -050095 }
96 }
97
Cliff Caie54c8202009-11-20 08:24:43 +000098 if (status & CMD_TIME_OUT)
Mike Frysinger6815f542010-06-21 20:56:54 +000099 ret = TIMEOUT;
Cliff Caie54c8202009-11-20 08:24:43 +0000100 else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
Mike Frysinger6815f542010-06-21 20:56:54 +0000101 ret = COMM_ERR;
102 else
103 ret = 0;
Cliff Caie54c8202009-11-20 08:24:43 +0000104
Cliff Cai716ebf42008-11-29 18:22:38 -0500105 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
106 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
Mike Frysinger6815f542010-06-21 20:56:54 +0000107
Cliff Cai716ebf42008-11-29 18:22:38 -0500108 return ret;
109}
110
Cliff Caie54c8202009-11-20 08:24:43 +0000111/* set data for single block transfer */
112static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
Cliff Cai716ebf42008-11-29 18:22:38 -0500113{
Cliff Caie54c8202009-11-20 08:24:43 +0000114 u16 data_ctl = 0;
115 u16 dma_cfg = 0;
Cliff Cai716ebf42008-11-29 18:22:38 -0500116 int ret = 0;
Sonic Zhang21a50372010-12-30 08:38:00 +0000117 unsigned long data_size = data->blocksize * data->blocks;
Cliff Cai716ebf42008-11-29 18:22:38 -0500118
Cliff Caie54c8202009-11-20 08:24:43 +0000119 /* Don't support write yet. */
120 if (data->flags & MMC_DATA_WRITE)
121 return UNUSABLE_ERR;
Sonic Zhang21a50372010-12-30 08:38:00 +0000122 data_ctl |= ((ffs(data_size) - 1) << 4);
Cliff Caie54c8202009-11-20 08:24:43 +0000123 data_ctl |= DTX_DIR;
124 bfin_write_SDH_DATA_CTL(data_ctl);
125 dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
Cliff Cai716ebf42008-11-29 18:22:38 -0500126
Cliff Cai1fd2d792009-12-07 06:12:11 +0000127 bfin_write_SDH_DATA_TIMER(-1);
Cliff Caie54c8202009-11-20 08:24:43 +0000128
129 blackfin_dcache_flush_invalidate_range(data->dest,
Sonic Zhang21a50372010-12-30 08:38:00 +0000130 data->dest + data_size);
Cliff Caie54c8202009-11-20 08:24:43 +0000131 /* configure DMA */
132 bfin_write_DMA_START_ADDR(data->dest);
Sonic Zhang21a50372010-12-30 08:38:00 +0000133 bfin_write_DMA_X_COUNT(data_size / 4);
Cliff Caie54c8202009-11-20 08:24:43 +0000134 bfin_write_DMA_X_MODIFY(4);
135 bfin_write_DMA_CONFIG(dma_cfg);
Sonic Zhang21a50372010-12-30 08:38:00 +0000136 bfin_write_SDH_DATA_LGTH(data_size);
Cliff Caie54c8202009-11-20 08:24:43 +0000137 /* kick off transfer */
138 bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
139
Cliff Cai716ebf42008-11-29 18:22:38 -0500140 return ret;
141}
142
Cliff Caie54c8202009-11-20 08:24:43 +0000143
144static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
145 struct mmc_data *data)
Cliff Cai716ebf42008-11-29 18:22:38 -0500146{
Cliff Caie54c8202009-11-20 08:24:43 +0000147 u32 status;
148 int ret = 0;
Cliff Cai716ebf42008-11-29 18:22:38 -0500149
Cliff Caie54c8202009-11-20 08:24:43 +0000150 ret = sdh_send_cmd(mmc, cmd);
151 if (ret) {
152 printf("sending CMD%d failed\n", cmd->cmdidx);
153 return ret;
154 }
155 if (data) {
156 ret = sdh_setup_data(mmc, data);
Cliff Cai716ebf42008-11-29 18:22:38 -0500157 do {
158 udelay(1);
159 status = bfin_read_SDH_STATUS();
160 } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
161
Cliff Caie54c8202009-11-20 08:24:43 +0000162 if (status & DAT_TIME_OUT) {
163 bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
164 ret |= TIMEOUT;
165 } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
166 bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
167 ret |= COMM_ERR;
168 } else
Cliff Cai716ebf42008-11-29 18:22:38 -0500169 bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
Cliff Caie54c8202009-11-20 08:24:43 +0000170
171 if (ret) {
172 printf("tranfering data failed\n");
173 return ret;
Cliff Cai716ebf42008-11-29 18:22:38 -0500174 }
175 }
Cliff Cai716ebf42008-11-29 18:22:38 -0500176 return 0;
177}
178
Cliff Caie54c8202009-11-20 08:24:43 +0000179static void sdh_set_clk(unsigned long clk)
Cliff Cai716ebf42008-11-29 18:22:38 -0500180{
Cliff Caie54c8202009-11-20 08:24:43 +0000181 unsigned long sys_clk;
182 unsigned long clk_div;
183 u16 clk_ctl = 0;
Cliff Cai716ebf42008-11-29 18:22:38 -0500184
Cliff Caie54c8202009-11-20 08:24:43 +0000185 clk_ctl = bfin_read_SDH_CLK_CTL();
186 if (clk) {
187 /* setting SD_CLK */
188 sys_clk = get_sclk();
189 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
190 if (sys_clk % (2 * clk) == 0)
191 clk_div = sys_clk / (2 * clk) - 1;
192 else
193 clk_div = sys_clk / (2 * clk);
Cliff Cai716ebf42008-11-29 18:22:38 -0500194
Cliff Caie54c8202009-11-20 08:24:43 +0000195 if (clk_div > 0xff)
196 clk_div = 0xff;
197 clk_ctl |= (clk_div & 0xff);
198 clk_ctl |= CLK_E;
199 bfin_write_SDH_CLK_CTL(clk_ctl);
200 } else
201 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
Cliff Cai716ebf42008-11-29 18:22:38 -0500202}
203
Cliff Caie54c8202009-11-20 08:24:43 +0000204static void bfin_sdh_set_ios(struct mmc *mmc)
Cliff Cai716ebf42008-11-29 18:22:38 -0500205{
Cliff Caie54c8202009-11-20 08:24:43 +0000206 u16 cfg = 0;
207 u16 clk_ctl = 0;
208
209 if (mmc->bus_width == 4) {
210 cfg = bfin_read_SDH_CFG();
211 cfg &= ~0x80;
212 cfg |= 0x40;
213 bfin_write_SDH_CFG(cfg);
214 clk_ctl |= WIDE_BUS;
215 }
216 bfin_write_SDH_CLK_CTL(clk_ctl);
217 sdh_set_clk(mmc->clock);
218}
219
220static int bfin_sdh_init(struct mmc *mmc)
221{
Mike Frysingera87589f2010-06-02 05:59:50 -0400222 const unsigned short pins[] = PORTMUX_PINS;
Cliff Caie54c8202009-11-20 08:24:43 +0000223 u16 pwr_ctl = 0;
Mike Frysingera87589f2010-06-02 05:59:50 -0400224
225 /* Initialize sdh controller */
226 peripheral_request_list(pins, "bfin_sdh");
Cliff Cai716ebf42008-11-29 18:22:38 -0500227#if defined(__ADSPBF54x__)
228 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
Cliff Cai716ebf42008-11-29 18:22:38 -0500229#endif
230 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
231 /* Disable card detect pin */
232 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
Cliff Caie54c8202009-11-20 08:24:43 +0000233
Cliff Cai716ebf42008-11-29 18:22:38 -0500234 pwr_ctl |= ROD_CTL;
235 pwr_ctl |= PWR_ON;
236 bfin_write_SDH_PWR_CTL(pwr_ctl);
Cliff Cai716ebf42008-11-29 18:22:38 -0500237 return 0;
238}
239
Cliff Caie54c8202009-11-20 08:24:43 +0000240
241int bfin_mmc_init(bd_t *bis)
Cliff Cai716ebf42008-11-29 18:22:38 -0500242{
Cliff Caie54c8202009-11-20 08:24:43 +0000243 struct mmc *mmc = NULL;
244
245 mmc = malloc(sizeof(struct mmc));
246
247 if (!mmc)
248 return -ENOMEM;
249 sprintf(mmc->name, "Blackfin SDH");
250 mmc->send_cmd = bfin_sdh_request;
251 mmc->set_ios = bfin_sdh_set_ios;
252 mmc->init = bfin_sdh_init;
Thierry Reding48972d92012-01-02 01:15:37 +0000253 mmc->getcd = NULL;
Cliff Caie54c8202009-11-20 08:24:43 +0000254 mmc->host_caps = MMC_MODE_4BIT;
255
256 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
257 mmc->f_max = get_sclk();
258 mmc->f_min = mmc->f_max >> 9;
Cliff Caie54c8202009-11-20 08:24:43 +0000259
John Rigby8feafcc2011-04-18 05:50:08 +0000260 mmc->b_max = 0;
261
Cliff Caie54c8202009-11-20 08:24:43 +0000262 mmc_register(mmc);
263
Cliff Cai716ebf42008-11-29 18:22:38 -0500264 return 0;
265}