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Tom Rix23b80982009-09-27 11:10:09 -05001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * (C) Copyright 2009
8 * Eric Benard <eric@eukrea.com>
9 *
10 * Configuration settings for the Eukrea CPU9260 board.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
Eric Benardc2b2a072011-04-03 06:35:54 +000034/* to be removed once maemory-map.h is fixed */
35#define AT91_BASE_SYS 0xffffe800
36#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
Tom Rix23b80982009-09-27 11:10:09 -050037
Achim Ehrlich7c966a82010-02-24 10:29:16 +010038#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Tom Rix23b80982009-09-27 11:10:09 -050039#define CONFIG_SYS_HZ 1000
Eric Benard95d50e52011-06-06 22:48:28 +000040#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Tom Rix23b80982009-09-27 11:10:09 -050041
42#if defined(CONFIG_CPU9G20)
Eric Benardc2b2a072011-04-03 06:35:54 +000043#define CONFIG_AT91SAM9G20
Tom Rix23b80982009-09-27 11:10:09 -050044#elif defined(CONFIG_CPU9260)
Eric Benardc2b2a072011-04-03 06:35:54 +000045#define CONFIG_AT91SAM9260
Tom Rix23b80982009-09-27 11:10:09 -050046#else
47#error "Unknown board"
48#endif
49
Eric Benard95d50e52011-06-06 22:48:28 +000050#include <asm/arch/hardware.h>
51
Eric Benardc2b2a072011-04-03 06:35:54 +000052#define CONFIG_AT91FAMILY
Tom Rix23b80982009-09-27 11:10:09 -050053#define CONFIG_ARCH_CPU_INIT
54#undef CONFIG_USE_IRQ
Eric Benardc2b2a072011-04-03 06:35:54 +000055#define CONFIG_DISPLAY_CPUINFO
56#define CONFIG_BOARD_EARLY_INIT_F
Tom Rix23b80982009-09-27 11:10:09 -050057
Eric Benardc2b2a072011-04-03 06:35:54 +000058#define CONFIG_CMDLINE_TAG
59#define CONFIG_SETUP_MEMORY_TAGS
60#define CONFIG_INITRD_TAG
61
62#if defined(CONFIG_NANDBOOT)
63#define CONFIG_SKIP_LOWLEVEL_INIT
64#define CONFIG_SYS_TEXT_BASE 0x23f00000
65#else
66#define CONFIG_SYS_TEXT_BASE 0x00000000
67#endif
Tom Rix23b80982009-09-27 11:10:09 -050068
69/* clocks */
70#if defined(CONFIG_CPU9G20)
71#define MASTER_PLL_DIV 0x01
72#define MASTER_PLL_MUL 0x2B
73#elif defined(CONFIG_CPU9260)
74#define MASTER_PLL_DIV 0x09
75#define MASTER_PLL_MUL 0x61
76#endif
77
78/* CKGR_MOR - enable main osc. */
79#define CONFIG_SYS_MOR_VAL \
80 (AT91_PMC_MOSCEN | \
81 (255 << 8)) /* Main Oscillator Start-up Time */
82#if defined(CONFIG_CPU9G20)
83#define CONFIG_SYS_PLLAR_VAL \
84 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
85 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
86#elif defined(CONFIG_CPU9260)
87#define CONFIG_SYS_PLLAR_VAL \
88 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
89 AT91_PMC_OUT | \
90 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
91#endif
92
93#if defined(CONFIG_CPU9G20)
94#define CONFIG_SYS_MCKR1_VAL \
95 (AT91_PMC_CSS_PLLA | \
96 AT91_PMC_PRES_1 | \
97 AT91SAM9_PMC_MDIV_6 | \
98 AT91_PMC_PDIV_2)
99#define CONFIG_SYS_MCKR2_VAL \
100 CONFIG_SYS_MCKR1_VAL
101#elif defined(CONFIG_CPU9260)
102#define CONFIG_SYS_MCKR1_VAL \
103 (AT91_PMC_CSS_SLOW | \
104 AT91_PMC_PRES_1 | \
105 AT91SAM9_PMC_MDIV_2 | \
106 AT91_PMC_PDIV_1)
107#define CONFIG_SYS_MCKR2_VAL \
108 (AT91_PMC_CSS_PLLA | \
109 AT91_PMC_PRES_1 | \
110 AT91SAM9_PMC_MDIV_2 | \
111 AT91_PMC_PDIV_1)
112#endif
113
114/* define PDC[31:16] as DATA[31:16] */
115#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
116/* no pull-up for D[31:16] */
117#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
118
119/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
120#define CONFIG_SYS_MATRIX_EBICSA_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000121 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
122 AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
Tom Rix23b80982009-09-27 11:10:09 -0500123
124/* SDRAM */
125/* SDRAMC_MR Mode register */
126#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
127/* SDRAMC_TR - Refresh Timer register */
128#define CONFIG_SYS_SDRC_TR_VAL1 0x287
129/* SDRAMC_CR - Configuration register*/
130#if defined(CONFIG_CPU9G20)
131#define CONFIG_SYS_SDRC_CR_VAL_64MB \
132 (AT91_SDRAMC_NC_9 | \
133 AT91_SDRAMC_NR_13 | \
134 AT91_SDRAMC_NB_4 | \
135 AT91_SDRAMC_CAS_2 | \
136 AT91_SDRAMC_DBW_32 | \
137 (2 << 8) | /* Write Recovery Delay */ \
138 (9 << 12) | /* Row Cycle Delay */ \
139 (3 << 16) | /* Row Precharge Delay */ \
140 (3 << 20) | /* Row to Column Delay */ \
141 (6 << 24) | /* Active to Precharge Delay */ \
142 (10 << 28)) /* Exit Self Refresh to Active Delay */
143
144#define CONFIG_SYS_SDRC_CR_VAL_128MB \
145 (AT91_SDRAMC_NC_10 | \
146 AT91_SDRAMC_NR_13 | \
147 AT91_SDRAMC_NB_4 | \
148 AT91_SDRAMC_CAS_2 | \
149 AT91_SDRAMC_DBW_32 | \
150 (2 << 8) | /* Write Recovery Delay */ \
151 (9 << 12) | /* Row Cycle Delay */ \
152 (3 << 16) | /* Row Precharge Delay */ \
153 (3 << 20) | /* Row to Column Delay */ \
154 (6 << 24) | /* Active to Precharge Delay */ \
155 (10 << 28)) /* Exit Self Refresh to Active Delay */
156#elif defined(CONFIG_CPU9260)
157#define CONFIG_SYS_SDRC_CR_VAL_64MB \
158 (AT91_SDRAMC_NC_9 | \
159 AT91_SDRAMC_NR_13 | \
160 AT91_SDRAMC_NB_4 | \
161 AT91_SDRAMC_CAS_2 | \
162 AT91_SDRAMC_DBW_32 | \
163 (2 << 8) | /* Write Recovery Delay */ \
164 (7 << 12) | /* Row Cycle Delay */ \
165 (2 << 16) | /* Row Precharge Delay */ \
166 (2 << 20) | /* Row to Column Delay */ \
167 (5 << 24) | /* Active to Precharge Delay */ \
168 (8 << 28)) /* Exit Self Refresh to Active Delay */
169
170#define CONFIG_SYS_SDRC_CR_VAL_128MB \
171 (AT91_SDRAMC_NC_10 | \
172 AT91_SDRAMC_NR_13 | \
173 AT91_SDRAMC_NB_4 | \
174 AT91_SDRAMC_CAS_2 | \
175 AT91_SDRAMC_DBW_32 | \
176 (2 << 8) | /* Write Recovery Delay */ \
177 (7 << 12) | /* Row Cycle Delay */ \
178 (2 << 16) | /* Row Precharge Delay */ \
179 (2 << 20) | /* Row to Column Delay */ \
180 (5 << 24) | /* Active to Precharge Delay */ \
181 (8 << 28)) /* Exit Self Refresh to Active Delay */
182#endif
183
184/* Memory Device Register -> SDRAM */
185#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
186#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
187#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
188#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
189#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
190#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
191#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
192#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
193#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
194#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
195#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
196#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
197#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
198#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
199#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
200#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
201#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
202#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
203
204/* setup SMC0, CS0 (NOR Flash) - 16-bit */
205#if defined(CONFIG_CPU9G20)
206#define CONFIG_SYS_SMC0_SETUP0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000207 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
208 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
Tom Rix23b80982009-09-27 11:10:09 -0500209#define CONFIG_SYS_SMC0_PULSE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000210 (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
211 AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
Tom Rix23b80982009-09-27 11:10:09 -0500212#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000213 (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
Tom Rix23b80982009-09-27 11:10:09 -0500214#define CONFIG_SYS_SMC0_MODE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000215 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
216 AT91_SMC_MODE_DBW_16 | \
217 AT91_SMC_MODE_TDF | \
218 AT91_SMC_MODE_TDF_CYCLE(3))
Tom Rix23b80982009-09-27 11:10:09 -0500219#elif defined(CONFIG_CPU9260)
220#define CONFIG_SYS_SMC0_SETUP0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000221 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
222 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
Tom Rix23b80982009-09-27 11:10:09 -0500223#define CONFIG_SYS_SMC0_PULSE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000224 (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
225 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
Tom Rix23b80982009-09-27 11:10:09 -0500226#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000227 (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
Tom Rix23b80982009-09-27 11:10:09 -0500228#define CONFIG_SYS_SMC0_MODE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000229 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
230 AT91_SMC_MODE_DBW_16 | \
231 AT91_SMC_MODE_TDF | \
232 AT91_SMC_MODE_TDF_CYCLE(2))
Tom Rix23b80982009-09-27 11:10:09 -0500233#endif
234
235/* user reset enable */
236#define CONFIG_SYS_RSTC_RMR_VAL \
237 (AT91_RSTC_KEY | \
Eric Benardc2b2a072011-04-03 06:35:54 +0000238 AT91_RSTC_CR_PROCRST | \
239 AT91_RSTC_MR_ERSTL(1) | \
240 AT91_RSTC_MR_ERSTL(2))
Tom Rix23b80982009-09-27 11:10:09 -0500241
242/* Disable Watchdog */
243#define CONFIG_SYS_WDTC_WDMR_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000244 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
245 AT91_WDT_MR_WDV(0xfff) | \
246 AT91_WDT_MR_WDDIS | \
247 AT91_WDT_MR_WDD(0xfff))
Tom Rix23b80982009-09-27 11:10:09 -0500248
249/*
250 * Hardware drivers
251 */
Eric Benardc2b2a072011-04-03 06:35:54 +0000252#define CONFIG_AT91SAM9_WATCHDOG
253#define CONFIG_AT91_GPIO
254#define CONFIG_ATMEL_USART
Eric Benard95d50e52011-06-06 22:48:28 +0000255#define CONFIG_USART_BASE ATMEL_BASE_DBGU
256#define CONFIG_USART_ID ATMEL_ID_SYS
Tom Rix23b80982009-09-27 11:10:09 -0500257
258#define CONFIG_BOOTDELAY 3
259
260/*
261 * BOOTP options
262 */
Eric Benardc2b2a072011-04-03 06:35:54 +0000263#define CONFIG_BOOTP_BOOTFILESIZE
264#define CONFIG_BOOTP_BOOTPATH
265#define CONFIG_BOOTP_GATEWAY
266#define CONFIG_BOOTP_HOSTNAME
Tom Rix23b80982009-09-27 11:10:09 -0500267
268/*
269 * Command line configuration.
270 */
271#include <config_cmd_default.h>
272#undef CONFIG_CMD_BDI
273#undef CONFIG_CMD_IMI
274#undef CONFIG_CMD_FPGA
275#undef CONFIG_CMD_LOADS
276#undef CONFIG_CMD_IMLS
277
Eric Benardc2b2a072011-04-03 06:35:54 +0000278#define CONFIG_CMD_PING
279#define CONFIG_CMD_DHCP
280#define CONFIG_CMD_NAND
281#define CONFIG_CMD_USB
282#define CONFIG_CMD_FAT
283#define CONFIG_CMD_MII
Tom Rix23b80982009-09-27 11:10:09 -0500284
285/* SDRAM */
286#define CONFIG_NR_DRAM_BANKS 1
Eric Benardc2b2a072011-04-03 06:35:54 +0000287#define CONFIG_SYS_SDRAM_BASE 0x20000000
Tom Rix23b80982009-09-27 11:10:09 -0500288#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
Eric Benardc2b2a072011-04-03 06:35:54 +0000289#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500290#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
291#else
Eric Benardc2b2a072011-04-03 06:35:54 +0000292#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500293#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
294#endif
295
296/* NAND flash */
Eric Benardc2b2a072011-04-03 06:35:54 +0000297#define CONFIG_NAND_ATMEL
Tom Rix23b80982009-09-27 11:10:09 -0500298#define NAND_MAX_CHIPS 1
299#define CONFIG_SYS_MAX_NAND_DEVICE 1
300#define CONFIG_SYS_NAND_BASE 0x40000000
301#define CONFIG_SYS_NAND_DBW_8 1
Eric Benardc2b2a072011-04-03 06:35:54 +0000302#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13
303#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
Tom Rix23b80982009-09-27 11:10:09 -0500304#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
305#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rix23b80982009-09-27 11:10:09 -0500306
307/* NOR flash */
Eric Benardc2b2a072011-04-03 06:35:54 +0000308#if defined(CONFIG_NANDBOOT)
309#define CONFIG_SYS_NO_FLASH
310#else
311#define CONFIG_SYS_FLASH_CFI
312#define CONFIG_FLASH_CFI_DRIVER
Tom Rix23b80982009-09-27 11:10:09 -0500313#define PHYS_FLASH_1 0x10000000
314#define PHYS_FLASH_2 0x12000000
315#define CONFIG_SYS_FLASH_BANKS_LIST \
316 { PHYS_FLASH_1, PHYS_FLASH_2 }
317#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
318#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
319#define CONFIG_SYS_MAX_FLASH_BANKS 2
320#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Eric Benardc2b2a072011-04-03 06:35:54 +0000321#define CONFIG_SYS_FLASH_EMPTY_INFO
322#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
323#define CONFIG_SYS_FLASH_PROTECTION
Tom Rix23b80982009-09-27 11:10:09 -0500324#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
Eric Benardc2b2a072011-04-03 06:35:54 +0000325#endif
Tom Rix23b80982009-09-27 11:10:09 -0500326
327/* Ethernet */
Eric Benardc2b2a072011-04-03 06:35:54 +0000328#define CONFIG_MACB
329#define CONFIG_RMII
Tom Rix23b80982009-09-27 11:10:09 -0500330#define CONFIG_NET_RETRY_COUNT 20
Eric Benardc2b2a072011-04-03 06:35:54 +0000331#define CONFIG_MACB_SEARCH_PHY
Tom Rix23b80982009-09-27 11:10:09 -0500332
333/* LEDS */
334/* Status LED */
Eric Benardc2b2a072011-04-03 06:35:54 +0000335#define CONFIG_STATUS_LED
336#define CONFIG_BOARD_SPECIFIC_LED
Tom Rix23b80982009-09-27 11:10:09 -0500337#define STATUS_LED_RED 0
338#define STATUS_LED_GREEN 1
339#define STATUS_LED_YELLOW 2
340#define STATUS_LED_BLUE 3
341/* Red */
342#define STATUS_LED_BIT STATUS_LED_RED
343#define STATUS_LED_STATE STATUS_LED_OFF
344#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
345/* Green */
346#define STATUS_LED_BIT1 STATUS_LED_GREEN
347#define STATUS_LED_STATE1 STATUS_LED_OFF
348#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
349/* Yellow */
350#define STATUS_LED_BIT2 STATUS_LED_YELLOW
351#define STATUS_LED_STATE2 STATUS_LED_OFF
352#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
353/* Blue */
354#define STATUS_LED_BIT3 STATUS_LED_BLUE
355#define STATUS_LED_STATE3 STATUS_LED_ON
356#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
357/* Optional value */
358#define STATUS_LED_BOOT STATUS_LED_BIT
359
Eric Benardc2b2a072011-04-03 06:35:54 +0000360#define CONFIG_RED_LED AT91_PIO_PORTC, 11
361#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
362#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
363#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
Tom Rix23b80982009-09-27 11:10:09 -0500364
365/* USB */
Eric Benardc2b2a072011-04-03 06:35:54 +0000366#define CONFIG_USB_ATMEL
367#define CONFIG_USB_OHCI_NEW
368#define CONFIG_DOS_PARTITION
369#define CONFIG_SYS_USB_OHCI_CPU_INIT
Tom Rix23b80982009-09-27 11:10:09 -0500370#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
Eric Benardc2b2a072011-04-03 06:35:54 +0000371#if defined(CONFIG_CPU9G20)
372#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
373#elif defined(CONFIG_CPU9260)
Tom Rix23b80982009-09-27 11:10:09 -0500374#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
Eric Benardc2b2a072011-04-03 06:35:54 +0000375#endif
Tom Rix23b80982009-09-27 11:10:09 -0500376#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Eric Benardc2b2a072011-04-03 06:35:54 +0000377#define CONFIG_USB_STORAGE
Tom Rix23b80982009-09-27 11:10:09 -0500378
379#define CONFIG_SYS_LOAD_ADDR 0x21000000
Eric Benardc2b2a072011-04-03 06:35:54 +0000380#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
Tom Rix23b80982009-09-27 11:10:09 -0500381
Eric Benardc2b2a072011-04-03 06:35:54 +0000382#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
383#define CONFIG_SYS_MEMTEST_END \
384 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500385
Eric Benardc2b2a072011-04-03 06:35:54 +0000386#if defined(CONFIG_NANDBOOT)
387#define CONFIG_SYS_USE_NANDFLASH
388#undef CONFIG_SYS_USE_FLASH
389#else
390#define CONFIG_SYS_USE_FLASH
Tom Rix23b80982009-09-27 11:10:09 -0500391#undef CONFIG_SYS_USE_NANDFLASH
Eric Benardc2b2a072011-04-03 06:35:54 +0000392#endif
393
394#if defined(CONFIG_CPU9G20)
395#define CONFIG_SYS_BASEDIR "cpu9G20"
396#elif defined(CONFIG_CPU9260)
397#define CONFIG_SYS_BASEDIR "cpu9260"
398#endif
Tom Rix23b80982009-09-27 11:10:09 -0500399
400#if defined(CONFIG_SYS_USE_FLASH)
Eric Benardc2b2a072011-04-03 06:35:54 +0000401#define CONFIG_ENV_IS_IN_FLASH
Tom Rix23b80982009-09-27 11:10:09 -0500402#define CONFIG_ENV_OFFSET 0x40000
403#define CONFIG_ENV_SECT_SIZE 0x20000
404#define CONFIG_ENV_SIZE 0x20000
Eric Benardc2b2a072011-04-03 06:35:54 +0000405#define CONFIG_ENV_OVERWRITE
Tom Rix23b80982009-09-27 11:10:09 -0500406
407#define CONFIG_BOOTCOMMAND "run flashboot"
408
Eric Benardc2b2a072011-04-03 06:35:54 +0000409#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
Tom Rix23b80982009-09-27 11:10:09 -0500410#define MTDPARTS_DEFAULT \
411 "mtdparts=physmap-flash.0:" \
412 "256k(u-boot)ro," \
413 "128k(u-boot-env)ro," \
414 "1792k(kernel)," \
415 "-(rootfs);" \
416 "atmel_nand:-(nand)"
417
418#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
419
Tom Rix23b80982009-09-27 11:10:09 -0500420#define CONFIG_EXTRA_ENV_SETTINGS \
421 "mtdids=" MTDIDS_DEFAULT "\0" \
422 "mtdparts=" MTDPARTS_DEFAULT "\0" \
423 "partition=nand0,0\0" \
424 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
Eric Benardc2b2a072011-04-03 06:35:54 +0000425 "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
Tom Rix23b80982009-09-27 11:10:09 -0500426 "run ramargs;bootm 22000000\0" \
427 "flashboot=run ramargs;bootm 0x10060000\0" \
428 "basedir=" CONFIG_SYS_BASEDIR "\0" \
429 "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
430 "off 0x10000000 0x1003ffff;erase 0x10000000 " \
431 "0x1003ffff;cp.b 0x24000000 0x10000000 " \
432 "$(filesize)\0" \
433 "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
434 " 0x10060000 0x1021ffff;erase 0x10060000 " \
435 "0x1021ffff;cp.b 0x24000000 0x10060000 " \
436 "$(filesize)\0" \
437 "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
438 "protect off 0x10220000 0x13ffffff;erase " \
439 "0x10220000 0x13ffffff;cp.b 0x24000000 " \
440 "0x10220000 $(filesize)\0" \
441 ""
Eric Benardc2b2a072011-04-03 06:35:54 +0000442#elif defined(CONFIG_NANDBOOT)
443#define CONFIG_ENV_IS_IN_NAND
444#define CONFIG_ENV_OFFSET 0x60000
445#define CONFIG_ENV_OFFSET_REDUND 0x80000
446#define CONFIG_ENV_SECT_SIZE 0x20000
447#define CONFIG_ENV_SIZE 0x20000
448#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
449#define CONFIG_ENV_OVERWRITE
450
451#define CONFIG_BOOTCOMMAND "run flashboot"
452
453#define MTDIDS_DEFAULT "nand0=atmel_nand"
454#define MTDPARTS_DEFAULT \
455 "mtdparts=atmel_nand:" \
456 "128k(bootstrap)ro," \
457 "256k(u-boot)ro," \
458 "128k(u-boot-env)ro," \
459 "128k(u-boot-env2)ro," \
460 "2M(kernel)," \
461 "-(rootfs)"
462
463#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
464 "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
465
466#define CONFIG_EXTRA_ENV_SETTINGS \
467 "mtdids=" MTDIDS_DEFAULT "\0" \
468 "mtdparts=" MTDPARTS_DEFAULT "\0" \
469 "partition=nand0,5\0" \
470 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
471 "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
472 "run ramargs;bootm 22000000\0" \
473 "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
474 "0x200000; bootm 0x22000000\0" \
475 "basedir=" CONFIG_SYS_BASEDIR "\0" \
476 "u-boot=u-boot-eukrea-cpu9260.bin\0" \
477 "kernel=uImage-eukrea-cpu9260.bin\0" \
478 "rootfs=image-eukrea-cpu9260.ubi\0" \
479 "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
480 "nand erase 20000 40000; " \
481 "nand write ${loadaddr} 20000 40000\0" \
482 "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
483 "nand erase a0000 200000; " \
484 "nand write ${loadaddr} a0000 200000\0" \
485 "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
486 "nand erase 2a0000 fd60000; " \
487 "nand write ${loadaddr} 2a0000 ${filesize}\0"
Tom Rix23b80982009-09-27 11:10:09 -0500488#endif
489
490#define CONFIG_BAUDRATE 115200
491#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
492
493#if defined(CONFIG_CPU9G20)
494#define CONFIG_SYS_PROMPT "CPU9G20=> "
495#elif defined(CONFIG_CPU9260)
496#define CONFIG_SYS_PROMPT "CPU9260=> "
497#endif
498#define CONFIG_SYS_CBSIZE 256
499#define CONFIG_SYS_MAXARGS 16
500#define CONFIG_SYS_PBSIZE \
501 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Eric Benardc2b2a072011-04-03 06:35:54 +0000502#define CONFIG_SYS_LONGHELP
503#define CONFIG_CMDLINE_EDITING
504#define CONFIG_SILENT_CONSOLE
505#define CONFIG_NETCONSOLE
Tom Rix23b80982009-09-27 11:10:09 -0500506
507/*
508 * Size of malloc() pool
509 */
510#define CONFIG_SYS_MALLOC_LEN \
511 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Tom Rix23b80982009-09-27 11:10:09 -0500512
Eric Benardc2b2a072011-04-03 06:35:54 +0000513#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
514 GENERATED_GBL_DATA_SIZE)
515
Tom Rix23b80982009-09-27 11:10:09 -0500516#define CONFIG_STACKSIZE (32 * 1024)
517
518#if defined(CONFIG_USE_IRQ)
519#error CONFIG_USE_IRQ not supported
520#endif
521
522#endif