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Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Chou4395e062015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glassaaba7032018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
19 help
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
23 access the device.
24
25config TPL_MISC
26 bool "Enable Driver Model for Misc drivers in TPL"
27 depends on TPL_DM
28 help
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
32 access the device.
33
Thomas Chouca844dd2015-10-14 08:43:31 +080034config ALTERA_SYSID
35 bool "Altera Sysid support"
36 depends on MISC
37 help
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
40
Marek BehĂșnaa5eb9a2017-06-09 19:28:44 +020041config ATSHA204A
42 bool "Support for Atmel ATSHA204A module"
43 depends on MISC
44 help
45 Enable support for I2C connected Atmel's ATSHA204A
46 CryptoAuthentication module found for example on the Turris Omnia
47 board.
48
Philipp Tomsich49cd8e82017-05-05 19:21:38 +020049config ROCKCHIP_EFUSE
50 bool "Rockchip e-fuse support"
51 depends on MISC
52 help
53 Enable (read-only) access for the e-fuse block found in Rockchip
54 SoCs: accesses can either be made using byte addressing and a length
55 or through child-nodes that are generated based on the e-fuse map
56 retrieved from the DTS.
57
58 This driver currently supports the RK3399 only, but can easily be
59 extended (by porting the read function from the Linux kernel sources)
60 to support other recent Rockchip devices.
61
Liviu Dudau0fabfeb2018-09-28 13:43:31 +010062config VEXPRESS_CONFIG
63 bool "Enable support for Arm Versatile Express config bus"
64 depends on MISC
65 help
66 If you say Y here, you will get support for accessing the
67 configuration bus on the Arm Versatile Express boards via
68 a sysreg driver.
69
Simon Glass6fb9ac12015-02-13 12:20:47 -070070config CMD_CROS_EC
71 bool "Enable crosec command"
72 depends on CROS_EC
73 help
74 Enable command-line access to the Chrome OS EC (Embedded
75 Controller). This provides the 'crosec' command which has
76 a number of sub-commands for performing EC tasks such as
77 updating its flash, accessing a small saved context area
78 and talking to the I2C bus behind the EC (if there is one).
79
80config CROS_EC
81 bool "Enable Chrome OS EC"
82 help
83 Enable access to the Chrome OS EC. This is a separate
84 microcontroller typically available on a SPI bus on Chromebooks. It
85 provides access to the keyboard, some internal storage and may
86 control access to the battery and main PMIC depending on the
87 device. You can use the 'crosec' command to access it.
88
Simon Glassaaba7032018-11-18 08:14:27 -070089config SPL_CROS_EC
90 bool "Enable Chrome OS EC in SPL"
Adam Forda0746672019-08-24 13:50:34 -050091 depends on SPL
Simon Glassaaba7032018-11-18 08:14:27 -070092 help
93 Enable access to the Chrome OS EC in SPL. This is a separate
94 microcontroller typically available on a SPI bus on Chromebooks. It
95 provides access to the keyboard, some internal storage and may
96 control access to the battery and main PMIC depending on the
97 device. You can use the 'crosec' command to access it.
98
99config TPL_CROS_EC
100 bool "Enable Chrome OS EC in TPL"
Adam Forda0746672019-08-24 13:50:34 -0500101 depends on TPL
Simon Glassaaba7032018-11-18 08:14:27 -0700102 help
103 Enable access to the Chrome OS EC in TPL. This is a separate
104 microcontroller typically available on a SPI bus on Chromebooks. It
105 provides access to the keyboard, some internal storage and may
106 control access to the battery and main PMIC depending on the
107 device. You can use the 'crosec' command to access it.
108
Simon Glass6fb9ac12015-02-13 12:20:47 -0700109config CROS_EC_I2C
110 bool "Enable Chrome OS EC I2C driver"
111 depends on CROS_EC
112 help
113 Enable I2C access to the Chrome OS EC. This is used on older
114 ARM Chromebooks such as snow and spring before the standard bus
115 changed to SPI. The EC will accept commands across the I2C using
116 a special message protocol, and provide responses.
117
118config CROS_EC_LPC
119 bool "Enable Chrome OS EC LPC driver"
120 depends on CROS_EC
121 help
122 Enable I2C access to the Chrome OS EC. This is used on x86
123 Chromebooks such as link and falco. The keyboard is provided
124 through a legacy port interface, so on x86 machines the main
125 function of the EC is power and thermal management.
126
Simon Glassaaba7032018-11-18 08:14:27 -0700127config SPL_CROS_EC_LPC
128 bool "Enable Chrome OS EC LPC driver in SPL"
129 depends on CROS_EC
130 help
131 Enable I2C access to the Chrome OS EC. This is used on x86
132 Chromebooks such as link and falco. The keyboard is provided
133 through a legacy port interface, so on x86 machines the main
134 function of the EC is power and thermal management.
135
136config TPL_CROS_EC_LPC
137 bool "Enable Chrome OS EC LPC driver in TPL"
138 depends on CROS_EC
139 help
140 Enable I2C access to the Chrome OS EC. This is used on x86
141 Chromebooks such as link and falco. The keyboard is provided
142 through a legacy port interface, so on x86 machines the main
143 function of the EC is power and thermal management.
144
Simon Glass47cb8c62015-03-26 09:29:40 -0600145config CROS_EC_SANDBOX
146 bool "Enable Chrome OS EC sandbox driver"
147 depends on CROS_EC && SANDBOX
148 help
149 Enable a sandbox emulation of the Chrome OS EC. This supports
150 keyboard (use the -l flag to enable the LCD), verified boot context,
151 EC flash read/write/erase support and a few other things. It is
152 enough to perform a Chrome OS verified boot on sandbox.
153
Simon Glassaaba7032018-11-18 08:14:27 -0700154config SPL_CROS_EC_SANDBOX
155 bool "Enable Chrome OS EC sandbox driver in SPL"
156 depends on SPL_CROS_EC && SANDBOX
157 help
158 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
159 keyboard (use the -l flag to enable the LCD), verified boot context,
160 EC flash read/write/erase support and a few other things. It is
161 enough to perform a Chrome OS verified boot on sandbox.
162
163config TPL_CROS_EC_SANDBOX
164 bool "Enable Chrome OS EC sandbox driver in TPL"
165 depends on TPL_CROS_EC && SANDBOX
166 help
167 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
168 keyboard (use the -l flag to enable the LCD), verified boot context,
169 EC flash read/write/erase support and a few other things. It is
170 enough to perform a Chrome OS verified boot on sandbox.
171
Simon Glass6fb9ac12015-02-13 12:20:47 -0700172config CROS_EC_SPI
173 bool "Enable Chrome OS EC SPI driver"
174 depends on CROS_EC
175 help
176 Enable SPI access to the Chrome OS EC. This is used on newer
177 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
178 provides a faster and more robust interface than I2C but the bugs
179 are less interesting.
180
Simon Glass879704d2017-05-17 03:25:02 -0600181config DS4510
182 bool "Enable support for DS4510 CPU supervisor"
183 help
184 Enable support for the Maxim DS4510 CPU supervisor. It has an
185 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
186 and a configurable timer for the supervisor function. The device is
187 connected over I2C.
188
Peng Fanc12e0d92015-08-26 15:41:33 +0800189config FSL_SEC_MON
gaurav ranafe783782015-02-27 09:44:22 +0530190 bool "Enable FSL SEC_MON Driver"
191 help
192 Freescale Security Monitor block is responsible for monitoring
193 system states.
194 Security Monitor can be transitioned on any security failures,
195 like software violations or hardware security violations.
Stefan Roese1cdd9412015-03-12 11:22:46 +0100196
Paul Burtonb5392c52018-12-16 19:25:19 -0300197config JZ4780_EFUSE
198 bool "Ingenic JZ4780 eFUSE support"
199 depends on ARCH_JZ47XX
200 help
201 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
202
Peng Fan3e020f02015-08-27 14:49:05 +0800203config MXC_OCOTP
204 bool "Enable MXC OCOTP Driver"
Peng Fan994ab732019-07-22 01:24:55 +0000205 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswiler0a6f6252019-03-25 17:24:57 +0100206 default y
Peng Fan3e020f02015-08-27 14:49:05 +0800207 help
208 If you say Y here, you will get support for the One Time
209 Programmable memory pages that are stored on the some
210 Freescale i.MX processors.
211
Stefan Roese4cf9e462016-07-19 07:45:46 +0200212config NUVOTON_NCT6102D
213 bool "Enable Nuvoton NCT6102D Super I/O driver"
214 help
215 If you say Y here, you will get support for the Nuvoton
216 NCT6102D Super I/O driver. This can be used to enable or
217 disable the legacy UART, the watchdog or other devices
218 in the Nuvoton Super IO chips on X86 platforms.
219
Simon Glass5fd6bad2016-01-21 19:43:31 -0700220config PWRSEQ
221 bool "Enable power-sequencing drivers"
222 depends on DM
223 help
224 Power-sequencing drivers provide support for controlling power for
225 devices. They are typically referenced by a phandle from another
226 device. When the device is started up, its power sequence can be
227 initiated.
228
229config SPL_PWRSEQ
230 bool "Enable power-sequencing drivers for SPL"
231 depends on PWRSEQ
232 help
233 Power-sequencing drivers provide support for controlling power for
234 devices. They are typically referenced by a phandle from another
235 device. When the device is started up, its power sequence can be
236 initiated.
237
Stefan Roese1cdd9412015-03-12 11:22:46 +0100238config PCA9551_LED
239 bool "Enable PCA9551 LED driver"
240 help
241 Enable driver for PCA9551 LED controller. This controller
242 is connected via I2C. So I2C needs to be enabled.
243
244config PCA9551_I2C_ADDR
245 hex "I2C address of PCA9551 LED controller"
246 depends on PCA9551_LED
247 default 0x60
248 help
249 The I2C address of the PCA9551 LED controller.
Simon Glassf9917452015-06-23 15:39:13 -0600250
Patrick Delaunayc3600e12018-05-17 15:24:06 +0200251config STM32MP_FUSE
252 bool "Enable STM32MP fuse wrapper providing the fuse API"
253 depends on ARCH_STM32MP && MISC
254 default y if CMD_FUSE
255 help
256 If you say Y here, you will get support for the fuse API (OTP)
257 for STM32MP architecture.
258 This API is needed for CMD_FUSE.
259
Christophe Kerello4e280b92017-09-13 18:00:08 +0200260config STM32_RCC
261 bool "Enable RCC driver for the STM32 SoC's family"
Patrick Delaunayd090cba2018-07-09 15:17:20 +0200262 depends on (STM32 || ARCH_STM32MP) && MISC
Christophe Kerello4e280b92017-09-13 18:00:08 +0200263 help
264 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
265 block) is responsible of the management of the clock and reset
266 generation.
267 This driver is similar to an MFD driver in the Linux kernel.
268
Stephen Warrenbd3ee842016-09-13 10:45:57 -0600269config TEGRA_CAR
270 bool "Enable support for the Tegra CAR driver"
271 depends on TEGRA_NO_BPMP
272 help
273 The Tegra CAR (Clock and Reset Controller) is a HW module that
274 controls almost all clocks and resets in a Tegra SoC.
275
Stephen Warren73dd5c42016-08-08 09:41:34 -0600276config TEGRA186_BPMP
277 bool "Enable support for the Tegra186 BPMP driver"
278 depends on TEGRA186
279 help
280 The Tegra BPMP (Boot and Power Management Processor) is a separate
281 auxiliary CPU embedded into Tegra to perform power management work,
282 and controls related features such as clocks, resets, power domains,
283 PMIC I2C bus, etc. This driver provides the core low-level
284 communication path by which feature-specific drivers (such as clock)
285 can make requests to the BPMP. This driver is similar to an MFD
286 driver in the Linux kernel.
287
Adam Fordcc3fedb2018-08-06 14:26:50 -0500288config TWL4030_LED
289 bool "Enable TWL4030 LED controller"
290 help
291 Enable this to add support for the TWL4030 LED controller.
292
Stefan Roese85056932016-01-19 14:05:10 +0100293config WINBOND_W83627
294 bool "Enable Winbond Super I/O driver"
295 help
296 If you say Y here, you will get support for the Winbond
297 W83627 Super I/O driver. This can be used to enable the
298 legacy UART or other devices in the Winbond Super IO chips
299 on X86 platforms.
300
Miao Yanfcf5c042016-05-22 19:37:14 -0700301config QFW
302 bool
303 help
304 Hidden option to enable QEMU fw_cfg interface. This will be selected by
Miao Yan18686592016-05-22 19:37:17 -0700305 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
Miao Yanfcf5c042016-05-22 19:37:14 -0700306
mario.six@gdsys.ccd7e28912016-06-22 15:14:16 +0200307config I2C_EEPROM
308 bool "Enable driver for generic I2C-attached EEPROMs"
309 depends on MISC
310 help
311 Enable a generic driver for EEPROMs attached via I2C.
Adam Forde3f24d42017-08-13 09:00:28 -0500312
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800313
314config SPL_I2C_EEPROM
315 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
316 depends on MISC && SPL && SPL_DM
317 help
318 This option is an SPL-variant of the I2C_EEPROM option.
319 See the help of I2C_EEPROM for details.
320
Vipul Kumar5c32de22018-02-16 19:07:21 +0530321config ZYNQ_GEM_I2C_MAC_OFFSET
322 hex "Set the I2C MAC offset"
323 default 0x0
Michal Simek027b1132019-01-22 15:55:46 +0100324 depends on DM_I2C
Vipul Kumar5c32de22018-02-16 19:07:21 +0530325 help
326 Set the MAC offset for i2C.
327
Adam Forde3f24d42017-08-13 09:00:28 -0500328if I2C_EEPROM
329
330config SYS_I2C_EEPROM_ADDR
331 hex "Chip address of the EEPROM device"
332 default 0
333
334config SYS_I2C_EEPROM_BUS
335 int "I2C bus of the EEPROM device."
336 default 0
337
338config SYS_EEPROM_SIZE
339 int "Size in bytes of the EEPROM device"
340 default 256
341
342config SYS_EEPROM_PAGE_WRITE_BITS
343 int "Number of bits used to address bytes in a single page"
344 default 0
345 help
346 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
347 A 64 byte page, for example would require six bits.
348
349config SYS_EEPROM_PAGE_WRITE_DELAY_MS
350 int "Number of milliseconds to delay between page writes"
351 default 0
352
353config SYS_I2C_EEPROM_ADDR_LEN
354 int "Length in bytes of the EEPROM memory array address"
355 default 1
356 help
357 Note: This is NOT the chip address length!
358
359config SYS_I2C_EEPROM_ADDR_OVERFLOW
360 hex "EEPROM Address Overflow"
361 default 0
362 help
363 EEPROM chips that implement "address overflow" are ones
364 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
365 address and the extra bits end up in the "chip address" bit
366 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
367 byte chips.
368
369endif
370
Mario Six86da8c12018-04-27 14:53:33 +0200371config GDSYS_RXAUI_CTRL
372 bool "Enable gdsys RXAUI control driver"
373 depends on MISC
374 help
375 Support gdsys FPGA's RXAUI control.
Mario Six7e862422018-07-31 14:24:15 +0200376
377config GDSYS_IOEP
378 bool "Enable gdsys IOEP driver"
379 depends on MISC
380 help
381 Support gdsys FPGA's IO endpoint driver.
Mario Sixd2166312018-08-06 10:23:46 +0200382
383config MPC83XX_SERDES
384 bool "Enable MPC83xx serdes driver"
385 depends on MISC
386 help
387 Support for serdes found on MPC83xx SoCs.
388
Tien Fong Chee62030002018-07-06 16:28:03 +0800389config FS_LOADER
390 bool "Enable loader driver for file system"
391 help
392 This is file system generic loader which can be used to load
393 the file image from the storage into target such as memory.
394
395 The consumer driver would then use this loader to program whatever,
396 ie. the FPGA device.
397
Mario Sixc0a2b082018-10-04 09:00:54 +0200398config GDSYS_SOC
399 bool "Enable gdsys SOC driver"
400 depends on MISC
401 help
402 Support for gdsys IHS SOC, a simple bus associated with each gdsys
403 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
404 register maps are contained within the FPGA's register map.
405
Mario Sixab88bd22018-10-04 09:00:55 +0200406config IHS_FPGA
407 bool "Enable IHS FPGA driver"
408 depends on MISC
409 help
410 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
411 gdsys devices, which supply the majority of the functionality offered
412 by the devices. This driver supports both CON and CPU variants of the
413 devices, depending on the device tree entry.
414
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900415endmenu