blob: 40f1e63281d5a2992da2f349eeb4bd43e1e3eb4b [file] [log] [blame]
Dave Liu19580e62007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * CREDITS: Kim Phillips contribute to LIBFDT code
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <common.h>
14#include <i2c.h>
Dave Liu6f8c85e2008-03-26 22:56:36 +080015#include <asm/io.h>
16#include <asm/fsl_serdes.h>
Dave Liu19580e62007-09-18 12:37:57 +080017#include <spd_sdram.h>
Kim Phillipsb3458d22007-12-20 15:57:28 -060018#if defined(CONFIG_OF_LIBFDT)
Dave Liu19580e62007-09-18 12:37:57 +080019#include <libfdt.h>
20#endif
21#if defined(CONFIG_PQ_MDS_PIB)
22#include "../common/pq-mds-pib.h"
23#endif
24
25int board_early_init_f(void)
26{
27 u8 *bcsr = (u8 *)CFG_BCSR;
28
29 /* Enable flash write */
30 bcsr[0x9] &= ~0x04;
31 /* Clear all of the interrupt of BCSR */
32 bcsr[0xe] = 0xff;
33
Dave Liu6f8c85e2008-03-26 22:56:36 +080034#ifdef CONFIG_FSL_SERDES
35 immap_t *immr = (immap_t *)CFG_IMMR;
36 u32 spridr = in_be32(&immr->sysconf.spridr);
37
38 /* we check only part num, and don't look for CPU revisions */
Dave Liu5fb5a682008-03-31 17:05:12 +080039 switch (PARTID_NO_E(spridr)) {
Kim Phillipse5c4ade2008-03-28 10:19:07 -050040 case SPR_8377:
Dave Liu6f8c85e2008-03-26 22:56:36 +080041 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
42 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
43 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
44 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
45 break;
Kim Phillipse5c4ade2008-03-28 10:19:07 -050046 case SPR_8378:
47 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
48 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
49 break;
50 case SPR_8379:
51 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
52 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
53 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
54 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
55 break;
Dave Liu6f8c85e2008-03-26 22:56:36 +080056 default:
57 printf("serdes not configured: unknown CPU part number: "
58 "%04x\n", spridr >> 16);
59 break;
60 }
61#endif /* CONFIG_FSL_SERDES */
Dave Liu19580e62007-09-18 12:37:57 +080062 return 0;
63}
64
65int board_early_init_r(void)
66{
67#ifdef CONFIG_PQ_MDS_PIB
68 pib_init();
69#endif
70 return 0;
71}
72
73#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
74extern void ddr_enable_ecc(unsigned int dram_size);
75#endif
76int fixed_sdram(void);
77
Becky Bruce9973e3c2008-06-09 16:03:40 -050078phys_size_t initdram(int board_type)
Dave Liu19580e62007-09-18 12:37:57 +080079{
80 volatile immap_t *im = (immap_t *) CFG_IMMR;
81 u32 msize = 0;
82
83 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
84 return -1;
85
86#if defined(CONFIG_SPD_EEPROM)
87 msize = spd_sdram();
88#else
89 msize = fixed_sdram();
90#endif
91
92#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
93 /* Initialize DDR ECC byte */
94 ddr_enable_ecc(msize * 1024 * 1024);
95#endif
96
97 /* return total bus DDR size(bytes) */
98 return (msize * 1024 * 1024);
99}
100
101#if !defined(CONFIG_SPD_EEPROM)
102/*************************************************************************
103 * fixed sdram init -- doesn't use serial presence detect.
104 ************************************************************************/
105int fixed_sdram(void)
106{
107 volatile immap_t *im = (immap_t *) CFG_IMMR;
108 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
109 u32 msize_log2 = __ilog2(msize);
110
111 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
112 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
113
114#if (CFG_DDR_SIZE != 512)
115#warning Currenly any ddr size other than 512 is not supported
116#endif
117 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
118 udelay(50000);
119
120 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
121 udelay(1000);
122
123 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
124 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
125 udelay(1000);
126
127 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
128 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
129 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
130 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
131 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
132 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
133 im->ddr.sdram_mode = CFG_DDR_MODE;
134 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
135 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
136 __asm__ __volatile__("sync");
137 udelay(1000);
138
139 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
140 udelay(2000);
141 return CFG_DDR_SIZE;
142}
143#endif /*!CFG_SPD_EEPROM */
144
145int checkboard(void)
146{
147 puts("Board: Freescale MPC837xEMDS\n");
148 return 0;
149}
150
151#if defined(CONFIG_OF_BOARD_SETUP)
152void ft_board_setup(void *blob, bd_t *bd)
153{
Dave Liu19580e62007-09-18 12:37:57 +0800154 ft_cpu_setup(blob, bd);
155#ifdef CONFIG_PCI
156 ft_pci_setup(blob, bd);
157#endif
158}
159#endif /* CONFIG_OF_BOARD_SETUP */