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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liew8e585f02007-06-18 13:50:13 -05002/*
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liew8e585f02007-06-18 13:50:13 -05007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M5329EVB_H
14#define _M5329EVB_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChung Liew8e585f02007-06-18 13:50:13 -050020
Tom Rini65cc0e22022-11-16 13:10:41 -050021#define CFG_SYS_UART_PORT (0)
TsiChung Liew8e585f02007-06-18 13:50:13 -050022
TsiChungLieweaf9e442007-08-05 04:11:20 -050023/* I2C */
TsiChungLieweaf9e442007-08-05 04:11:20 -050024
Tom Rini0613c362022-12-04 10:03:50 -050025#define CFG_EXTRA_ENV_SETTINGS \
TsiChung Liew8e585f02007-06-18 13:50:13 -050026 "netdev=eth0\0" \
27 "loadaddr=40010000\0" \
28 "u-boot=u-boot.bin\0" \
29 "load=tftp ${loadaddr) ${u-boot}\0" \
30 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +080031 "prog=prot off 0 3ffff;" \
32 "era 0 3ffff;" \
TsiChung Liew8e585f02007-06-18 13:50:13 -050033 "cp.b ${loadaddr} 0 ${filesize};" \
34 "save\0" \
35 ""
36
Tom Rini7c5c1372022-12-04 10:13:37 -050037#define CFG_PRAM 512 /* 512 KB */
TsiChung Liew8e585f02007-06-18 13:50:13 -050038
Tom Rini65cc0e22022-11-16 13:10:41 -050039#define CFG_SYS_CLK 80000000
40#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
TsiChung Liew8e585f02007-06-18 13:50:13 -050041
Tom Rini65cc0e22022-11-16 13:10:41 -050042#define CFG_SYS_MBAR 0xFC000000
TsiChung Liew8e585f02007-06-18 13:50:13 -050043
Tom Rini65cc0e22022-11-16 13:10:41 -050044#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
TsiChungLiew1a33ce62007-08-05 04:31:18 -050045
TsiChung Liew8e585f02007-06-18 13:50:13 -050046/*
47 * Low Level Configuration Settings
48 * (address mappings, register initial values, etc.)
49 * You should know what you are doing if you make changes here.
50 */
51/*-----------------------------------------------------------------------
52 * Definitions for initial stack pointer and data area (in DPRAM)
53 */
Tom Rini65cc0e22022-11-16 13:10:41 -050054#define CFG_SYS_INIT_RAM_ADDR 0x80000000
55#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
56#define CFG_SYS_INIT_RAM_CTRL 0x221
TsiChung Liew8e585f02007-06-18 13:50:13 -050057
58/*-----------------------------------------------------------------------
59 * Start addresses for the final memory configuration
60 * (Set up by the startup code)
Tom Riniaa6e94d2022-11-16 13:10:37 -050061 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew8e585f02007-06-18 13:50:13 -050062 */
Tom Riniaa6e94d2022-11-16 13:10:37 -050063#define CFG_SYS_SDRAM_BASE 0x40000000
64#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
65#define CFG_SYS_SDRAM_CFG1 0x53722730
66#define CFG_SYS_SDRAM_CFG2 0x56670000
67#define CFG_SYS_SDRAM_CTRL 0xE1092000
68#define CFG_SYS_SDRAM_EMOD 0x40010000
69#define CFG_SYS_SDRAM_MODE 0x018D0000
TsiChung Liew8e585f02007-06-18 13:50:13 -050070
TsiChung Liew8e585f02007-06-18 13:50:13 -050071/*
72 * For booting Linux, the board info and command line data
73 * have to be in the first 8 MB of memory, since this is
74 * the maximum mapped by the Linux kernel during initialization ??
75 */
Tom Rini65cc0e22022-11-16 13:10:41 -050076#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
TsiChung Liew8e585f02007-06-18 13:50:13 -050077
78/*-----------------------------------------------------------------------
79 * FLASH organization
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#ifdef CONFIG_SYS_FLASH_CFI
Tom Rini65cc0e22022-11-16 13:10:41 -050082# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
TsiChung Liew8e585f02007-06-18 13:50:13 -050083#endif
84
Tom Riniac28e202022-03-24 17:17:57 -040085#ifdef CONFIG_CMD_NAND
Tom Rini65cc0e22022-11-16 13:10:41 -050086# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
Tom Rini4e590942022-11-12 17:36:51 -050087# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
TsiChungLiewab77bc52007-08-15 15:39:17 -050088# define NAND_ALLOW_ERASE_ALL 1
TsiChungLiew1a33ce62007-08-05 04:31:18 -050089#endif
90
Tom Rini65cc0e22022-11-16 13:10:41 -050091#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
TsiChung Liew8e585f02007-06-18 13:50:13 -050092
93/* Configuration for environment
94 * Environment is embedded in u-boot in the second sector of the flash
95 */
TsiChung Liew8e585f02007-06-18 13:50:13 -050096
angelo@sysam.it5296cb12015-03-29 22:54:16 +020097#define LDS_BOARD_TEXT \
Simon Glass0649cd02017-08-03 12:21:49 -060098 . = DEFINED(env_offset) ? env_offset : .; \
99 env/embedded.o(.text*);
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200100
TsiChung Liew8e585f02007-06-18 13:50:13 -0500101/*-----------------------------------------------------------------------
102 * Cache Configuration
103 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500104
Tom Rini65cc0e22022-11-16 13:10:41 -0500105#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
106 CFG_SYS_INIT_RAM_SIZE - 8)
107#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
108 CFG_SYS_INIT_RAM_SIZE - 4)
109#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
110#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
Tom Riniaa6e94d2022-11-16 13:10:37 -0500111 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600112 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini65cc0e22022-11-16 13:10:41 -0500113#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600114 CF_CACR_DCM_P)
115
TsiChung Liew8e585f02007-06-18 13:50:13 -0500116/*-----------------------------------------------------------------------
117 * Chipselect bank definitions
118 */
119/*
120 * CS0 - NOR Flash 1, 2, 4, or 8MB
121 * CS1 - CompactFlash and registers
122 * CS2 - NAND Flash 16, 32, or 64MB
123 * CS3 - Available
124 * CS4 - Available
125 * CS5 - Available
126 */
Tom Rini65cc0e22022-11-16 13:10:41 -0500127#define CFG_SYS_CS0_BASE 0
128#define CFG_SYS_CS0_MASK 0x007f0001
129#define CFG_SYS_CS0_CTRL 0x00001fa0
TsiChung Liew8e585f02007-06-18 13:50:13 -0500130
Tom Rini65cc0e22022-11-16 13:10:41 -0500131#define CFG_SYS_CS1_BASE 0x10000000
132#define CFG_SYS_CS1_MASK 0x001f0001
133#define CFG_SYS_CS1_CTRL 0x002A3780
TsiChung Liew8e585f02007-06-18 13:50:13 -0500134
Tom Riniac28e202022-03-24 17:17:57 -0400135#ifdef CONFIG_CMD_NAND
Tom Rini65cc0e22022-11-16 13:10:41 -0500136#define CFG_SYS_CS2_BASE 0x20000000
137#define CFG_SYS_CS2_MASK (16 << 20)
138#define CFG_SYS_CS2_CTRL 0x00001f60
TsiChung Liew8e585f02007-06-18 13:50:13 -0500139#endif
140
Angelo Dureghello7ff7b462023-02-25 23:25:26 +0100141
TsiChung Liew8e585f02007-06-18 13:50:13 -0500142#endif /* _M5329EVB_H */