blob: 801be68e8ef5eaa7573d7a1634813d47ddbbec62 [file] [log] [blame]
Dirk Eibach50dcf892014-11-13 19:21:18 +01001/*
2 * (C) Copyright 2014
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_MPC83xx 1 /* MPC83xx family */
17#define CONFIG_MPC830x 1 /* MPC830x family */
18#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19#define CONFIG_HRCON 1 /* HRCON board specific */
20
21#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
Dirk Eibach7ed45d32015-10-28 11:46:35 +010023#ifdef CONFIG_HRCON_DH
24#define CONFIG_IDENT_STRING " hrcon dh 0.01"
25#else
Dirk Eibach50dcf892014-11-13 19:21:18 +010026#define CONFIG_IDENT_STRING " hrcon 0.01"
Dirk Eibach7ed45d32015-10-28 11:46:35 +010027#endif
Dirk Eibach50dcf892014-11-13 19:21:18 +010028
Dirk Eibach50dcf892014-11-13 19:21:18 +010029
30#define CONFIG_BOARD_EARLY_INIT_F
31#define CONFIG_BOARD_EARLY_INIT_R
32#define CONFIG_LAST_STAGE_INIT
33
34/* new uImage format support */
35#define CONFIG_FIT 1
36#define CONFIG_FIT_VERBOSE 1
37
38#define CONFIG_MMC
39#define CONFIG_FSL_ESDHC
40#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
41#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
42
43#define CONFIG_CMD_MMC
44#define CONFIG_GENERIC_MMC
45#define CONFIG_DOS_PARTITION
46#define CONFIG_CMD_EXT2
47
48#define CONFIG_CMD_FPGAD
49#define CONFIG_CMD_IOLOOP
50
51/*
52 * System Clock Setup
53 */
54#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
55#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
56
57/*
58 * Hardware Reset Configuration Word
59 * if CLKIN is 66.66MHz, then
60 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
61 * We choose the A type silicon as default, so the core is 400Mhz.
62 */
63#define CONFIG_SYS_HRCW_LOW (\
64 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
65 HRCWL_DDR_TO_SCB_CLK_2X1 |\
66 HRCWL_SVCOD_DIV_2 |\
67 HRCWL_CSB_TO_CLKIN_4X1 |\
68 HRCWL_CORE_TO_CSB_3X1)
69/*
70 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
71 * in 8308's HRCWH according to the manual, but original Freescale's
72 * code has them and I've expirienced some problems using the board
73 * with BDI3000 attached when I've tried to set these bits to zero
74 * (UART doesn't work after the 'reset run' command).
75 */
76#define CONFIG_SYS_HRCW_HIGH (\
77 HRCWH_PCI_HOST |\
78 HRCWH_PCI1_ARBITER_ENABLE |\
79 HRCWH_CORE_ENABLE |\
80 HRCWH_FROM_0XFFF00100 |\
81 HRCWH_BOOTSEQ_DISABLE |\
82 HRCWH_SW_WATCHDOG_DISABLE |\
83 HRCWH_ROM_LOC_LOCAL_16BIT |\
84 HRCWH_RL_EXT_LEGACY |\
85 HRCWH_TSEC1M_IN_RGMII |\
86 HRCWH_TSEC2M_IN_RGMII |\
87 HRCWH_BIG_ENDIAN)
88
89/*
90 * System IO Config
91 */
92#define CONFIG_SYS_SICRH (\
93 SICRH_ESDHC_A_SD |\
94 SICRH_ESDHC_B_SD |\
95 SICRH_ESDHC_C_SD |\
96 SICRH_GPIO_A_GPIO |\
97 SICRH_GPIO_B_GPIO |\
98 SICRH_IEEE1588_A_GPIO |\
99 SICRH_USB |\
100 SICRH_GTM_GPIO |\
101 SICRH_IEEE1588_B_GPIO |\
102 SICRH_ETSEC2_GPIO |\
103 SICRH_GPIOSEL_1 |\
104 SICRH_TMROBI_V3P3 |\
105 SICRH_TSOBI1_V2P5 |\
106 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
107#define CONFIG_SYS_SICRL (\
108 SICRL_SPI_PF0 |\
109 SICRL_UART_PF0 |\
110 SICRL_IRQ_PF0 |\
111 SICRL_I2C2_PF0 |\
112 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
113
114/*
115 * IMMR new address
116 */
117#define CONFIG_SYS_IMMR 0xE0000000
118
119/*
120 * SERDES
121 */
122#define CONFIG_FSL_SERDES
123#define CONFIG_FSL_SERDES1 0xe3000
124
125/*
126 * Arbiter Setup
127 */
128#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
129#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
130#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
131
132/*
133 * DDR Setup
134 */
135#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
136#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
137#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
138#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
139#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
140 | DDRCDR_PZ_LOZ \
141 | DDRCDR_NZ_LOZ \
142 | DDRCDR_ODT \
143 | DDRCDR_Q_DRN)
144 /* 0x7b880001 */
145/*
146 * Manually set up DDR parameters
147 * consist of one chip NT5TU64M16HG from NANYA
148 */
149
150#define CONFIG_SYS_DDR_SIZE 128 /* MB */
151
152#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
153#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
154 | CSCONFIG_ODT_RD_NEVER \
155 | CSCONFIG_ODT_WR_ONLY_CURRENT \
156 | CSCONFIG_BANK_BIT_3 \
157 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
158 /* 0x80010102 */
159#define CONFIG_SYS_DDR_TIMING_3 0
160#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
161 | (0 << TIMING_CFG0_WRT_SHIFT) \
162 | (0 << TIMING_CFG0_RRT_SHIFT) \
163 | (0 << TIMING_CFG0_WWT_SHIFT) \
164 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
165 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
166 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
167 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
168 /* 0x00260802 */
169#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
170 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
171 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
172 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
173 | (9 << TIMING_CFG1_REFREC_SHIFT) \
174 | (2 << TIMING_CFG1_WRREC_SHIFT) \
175 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
176 | (2 << TIMING_CFG1_WRTORD_SHIFT))
177 /* 0x26279222 */
178#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
179 | (4 << TIMING_CFG2_CPO_SHIFT) \
180 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
181 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
182 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
183 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
184 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
185 /* 0x021848c5 */
186#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
187 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
188 /* 0x08240100 */
189#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
190 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
191 | SDRAM_CFG_DBW_16)
192 /* 0x43100000 */
193
194#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
195#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
196 | (0x0242 << SDRAM_MODE_SD_SHIFT))
197 /* ODT 150ohm CL=4, AL=0 on SDRAM */
198#define CONFIG_SYS_DDR_MODE2 0x00000000
199
200/*
201 * Memory test
202 */
203#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
204#define CONFIG_SYS_MEMTEST_END 0x07f00000
205
206/*
207 * The reserved memory
208 */
209#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
210
211#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
212#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
213
214/*
215 * Initial RAM Base Address Setup
216 */
217#define CONFIG_SYS_INIT_RAM_LOCK 1
218#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
219#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
220#define CONFIG_SYS_GBL_DATA_OFFSET \
221 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
222
223/*
224 * Local Bus Configuration & Clock Setup
225 */
226#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
227#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
228#define CONFIG_SYS_LBC_LBCR 0x00040000
229
230/*
231 * FLASH on the Local Bus
232 */
233#if 1
234#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
235#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
236#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
237#define CONFIG_FLASH_CFI_LEGACY
238#define CONFIG_SYS_FLASH_LEGACY_512Kx16
239#else
240#define CONFIG_SYS_NO_FLASH
241#endif
242
243#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
244#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
245#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
246
247/* Window base at flash base */
248#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
249#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
250
251#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
252 | BR_PS_16 /* 16 bit port */ \
253 | BR_MS_GPCM /* MSEL = GPCM */ \
254 | BR_V) /* valid */
255#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
256 | OR_UPM_XAM \
257 | OR_GPCM_CSNT \
258 | OR_GPCM_ACS_DIV2 \
259 | OR_GPCM_XACS \
260 | OR_GPCM_SCY_15 \
261 | OR_GPCM_TRLX_SET \
262 | OR_GPCM_EHTR_SET)
263
264#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
265#define CONFIG_SYS_MAX_FLASH_SECT 135
266
267#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
268#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
269
270/*
271 * FPGA
272 */
273#define CONFIG_SYS_FPGA0_BASE 0xE0600000
274#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
275
276/* Window base at FPGA base */
277#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
278#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
279
280#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
281 | BR_PS_16 /* 16 bit port */ \
282 | BR_MS_GPCM /* MSEL = GPCM */ \
283 | BR_V) /* valid */
284#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
285 | OR_UPM_XAM \
286 | OR_GPCM_CSNT \
287 | OR_GPCM_ACS_DIV2 \
288 | OR_GPCM_XACS \
289 | OR_GPCM_SCY_15 \
290 | OR_GPCM_TRLX_SET \
291 | OR_GPCM_EHTR_SET)
292
293#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
294#define CONFIG_SYS_FPGA_DONE(k) 0x0010
295
296#define CONFIG_SYS_FPGA_COUNT 1
297
298#define CONFIG_SYS_MCLINK_MAX 3
299
300#define CONFIG_SYS_FPGA_PTR \
301 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
302
303/*
304 * Serial Port
305 */
306#define CONFIG_CONS_INDEX 2
Dirk Eibach50dcf892014-11-13 19:21:18 +0100307#define CONFIG_SYS_NS16550_SERIAL
308#define CONFIG_SYS_NS16550_REG_SIZE 1
309#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
310
311#define CONFIG_SYS_BAUDRATE_TABLE \
312 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
313
314#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
315#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
316
317/* Use the HUSH parser */
318#define CONFIG_SYS_HUSH_PARSER
319
320/* Pass open firmware flat tree */
321#define CONFIG_OF_LIBFDT 1
322#define CONFIG_OF_BOARD_SETUP 1
323#define CONFIG_OF_STDOUT_VIA_ALIAS 1
324
325/* I2C */
326#define CONFIG_SYS_I2C
327#define CONFIG_SYS_I2C_FSL
328#define CONFIG_SYS_FSL_I2C_SPEED 400000
329#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
330#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
331
332#define CONFIG_PCA953X /* NXP PCA9554 */
333#define CONFIG_PCA9698 /* NXP PCA9698 */
334
335#define CONFIG_SYS_I2C_IHS
336#define CONFIG_SYS_I2C_IHS_CH0
337#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
338#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
339#define CONFIG_SYS_I2C_IHS_CH1
340#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
341#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
342#define CONFIG_SYS_I2C_IHS_CH2
343#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
344#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
345#define CONFIG_SYS_I2C_IHS_CH3
346#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
347#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
348
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100349#ifdef CONFIG_HRCON_DH
350#define CONFIG_SYS_I2C_IHS_DUAL
351#define CONFIG_SYS_I2C_IHS_CH0_1
352#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
353#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
354#define CONFIG_SYS_I2C_IHS_CH1_1
355#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
356#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
357#define CONFIG_SYS_I2C_IHS_CH2_1
358#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
359#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
360#define CONFIG_SYS_I2C_IHS_CH3_1
361#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
362#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
363#endif
364
Dirk Eibach50dcf892014-11-13 19:21:18 +0100365/*
366 * Software (bit-bang) I2C driver configuration
367 */
368#define CONFIG_SYS_I2C_SOFT
369#define CONFIG_SYS_I2C_SOFT_SPEED 50000
370#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
371#define I2C_SOFT_DECLARATIONS2
372#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
373#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
374#define I2C_SOFT_DECLARATIONS3
375#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
376#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
377#define I2C_SOFT_DECLARATIONS4
378#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
379#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100380#define I2C_SOFT_DECLARATIONS5
381#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
382#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
383#define I2C_SOFT_DECLARATIONS6
384#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
385#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
386#define I2C_SOFT_DECLARATIONS7
387#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
388#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
389#define I2C_SOFT_DECLARATIONS8
390#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
391#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100392
393#ifdef CONFIG_HRCON_DH
394#define I2C_SOFT_DECLARATIONS9
395#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
396#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
397#define I2C_SOFT_DECLARATIONS10
398#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
399#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
400#define I2C_SOFT_DECLARATIONS11
401#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
402#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
403#define I2C_SOFT_DECLARATIONS12
404#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
405#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100406#endif
407
408#ifdef CONFIG_HRCON_DH
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100409#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100410#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100411#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
412 {12, 0x4c} }
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100413#else
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100414#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
Dirk Eibach50dcf892014-11-13 19:21:18 +0100415#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100416#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
417 {8, 0x4c} }
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100418#endif
Dirk Eibach50dcf892014-11-13 19:21:18 +0100419
420#ifndef __ASSEMBLY__
421void fpga_gpio_set(unsigned int bus, int pin);
422void fpga_gpio_clear(unsigned int bus, int pin);
423int fpga_gpio_get(unsigned int bus, int pin);
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100424void fpga_control_set(unsigned int bus, int pin);
425void fpga_control_clear(unsigned int bus, int pin);
Dirk Eibach50dcf892014-11-13 19:21:18 +0100426#endif
427
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100428#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
429#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
430#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
431
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100432#ifdef CONFIG_HRCON_DH
433#define I2C_ACTIVE \
434 do { \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100435 if (I2C_ADAP_HWNR > 7) \
436 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100437 else \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100438 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100439 } while (0)
440#else
Dirk Eibach50dcf892014-11-13 19:21:18 +0100441#define I2C_ACTIVE { }
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100442#endif
Dirk Eibach50dcf892014-11-13 19:21:18 +0100443#define I2C_TRISTATE { }
444#define I2C_READ \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100445 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
Dirk Eibach50dcf892014-11-13 19:21:18 +0100446#define I2C_SDA(bit) \
447 do { \
448 if (bit) \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100449 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
Dirk Eibach50dcf892014-11-13 19:21:18 +0100450 else \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100451 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
Dirk Eibach50dcf892014-11-13 19:21:18 +0100452 } while (0)
453#define I2C_SCL(bit) \
454 do { \
455 if (bit) \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100456 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
Dirk Eibach50dcf892014-11-13 19:21:18 +0100457 else \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100458 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
Dirk Eibach50dcf892014-11-13 19:21:18 +0100459 } while (0)
460#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
461
462/*
463 * Software (bit-bang) MII driver configuration
464 */
465#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
466#define CONFIG_BITBANGMII_MULTI
467
468/*
469 * OSD Setup
470 */
471#define CONFIG_SYS_OSD_SCREENS 1
472#define CONFIG_SYS_DP501_DIFFERENTIAL
473#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
474
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100475#ifdef CONFIG_HRCON_DH
476#define CONFIG_SYS_OSD_DH
477#endif
478
Dirk Eibach50dcf892014-11-13 19:21:18 +0100479/*
480 * General PCI
481 * Addresses are mapped 1-1.
482 */
483#define CONFIG_SYS_PCIE1_BASE 0xA0000000
484#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
485#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
486#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
487#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
488#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
489#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
490#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
491#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
492
493/* enable PCIE clock */
494#define CONFIG_SYS_SCCR_PCIEXP1CM 1
495
496#define CONFIG_PCI
497#define CONFIG_PCI_INDIRECT_BRIDGE
498#define CONFIG_PCIE
499
500#define CONFIG_PCI_PNP /* do pci plug-and-play */
501
502#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
503#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
504
505/*
506 * TSEC
507 */
508#define CONFIG_TSEC_ENET /* TSEC ethernet support */
509#define CONFIG_SYS_TSEC1_OFFSET 0x24000
510#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
511
512/*
513 * TSEC ethernet configuration
514 */
515#define CONFIG_MII 1 /* MII PHY management */
516#define CONFIG_TSEC1
517#define CONFIG_TSEC1_NAME "eTSEC0"
518#define TSEC1_PHY_ADDR 1
519#define TSEC1_PHYIDX 0
520#define TSEC1_FLAGS TSEC_GIGABIT
521
522/* Options are: eTSEC[0-1] */
523#define CONFIG_ETHPRIME "eTSEC0"
524
525/*
526 * Environment
527 */
528#if 1
529#define CONFIG_ENV_IS_IN_FLASH 1
530#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
531 CONFIG_SYS_MONITOR_LEN)
532#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
533#define CONFIG_ENV_SIZE 0x2000
534#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
535#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
536#else
537#define CONFIG_ENV_IS_NOWHERE
538#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
539#endif
540
541#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
542#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
543
544/*
545 * Command line configuration.
546 */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100547#define CONFIG_CMD_I2C
548#define CONFIG_CMD_MII
Dirk Eibach50dcf892014-11-13 19:21:18 +0100549#define CONFIG_CMD_PCI
550#define CONFIG_CMD_PING
551
552#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
553#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
554
555/*
556 * Miscellaneous configurable options
557 */
558#define CONFIG_SYS_LONGHELP /* undef to save memory */
559#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100560#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
561
562#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100563
564#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
565
566#define CONFIG_SYS_CONSOLE_INFO_QUIET
567
568/* Print Buffer Size */
569#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
570#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
571#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
572
573/*
574 * For booting Linux, the board info and command line data
575 * have to be in the first 256 MB of memory, since this is
576 * the maximum mapped by the Linux kernel during initialization.
577 */
578#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
579
580/*
581 * Core HID Setup
582 */
583#define CONFIG_SYS_HID0_INIT 0x000000000
584#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
585 HID0_ENABLE_INSTRUCTION_CACHE | \
586 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
587#define CONFIG_SYS_HID2 HID2_HBE
588
589/*
590 * MMU Setup
591 */
592
593/* DDR: cache cacheable */
594#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
595 BATL_MEMCOHERENCE)
596#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
597 BATU_VS | BATU_VP)
598#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
599#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
600
601/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
602#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
603 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
604#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
605 BATU_VP)
606#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
607#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
608
609/* FLASH: icache cacheable, but dcache-inhibit and guarded */
610#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
611 BATL_MEMCOHERENCE)
612#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
613 BATU_VS | BATU_VP)
614#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
615 BATL_CACHEINHIBIT | \
616 BATL_GUARDEDSTORAGE)
617#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
618
619/* Stack in dcache: cacheable, no memory coherence */
620#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
621#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
622 BATU_VS | BATU_VP)
623#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
624#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
625
626/*
627 * Environment Configuration
628 */
629
630#define CONFIG_ENV_OVERWRITE
631
632#if defined(CONFIG_TSEC_ENET)
633#define CONFIG_HAS_ETH0
634#endif
635
636#define CONFIG_BAUDRATE 115200
637
638#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
639
640#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
641
642#define CONFIG_HOSTNAME hrcon
643#define CONFIG_ROOTPATH "/opt/nfsroot"
644#define CONFIG_BOOTFILE "uImage"
645
646#define CONFIG_PREBOOT /* enable preboot variable */
647
648#define CONFIG_EXTRA_ENV_SETTINGS \
649 "netdev=eth0\0" \
650 "consoledev=ttyS1\0" \
651 "u-boot=u-boot.bin\0" \
652 "kernel_addr=1000000\0" \
653 "fdt_addr=C00000\0" \
654 "fdtfile=hrcon.dtb\0" \
655 "load=tftp ${loadaddr} ${u-boot}\0" \
656 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
657 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
658 " +${filesize};cp.b ${fileaddr} " \
659 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
660 "upd=run load update\0" \
661
662#define CONFIG_NFSBOOTCOMMAND \
663 "setenv bootargs root=/dev/nfs rw " \
664 "nfsroot=$serverip:$rootpath " \
665 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
666 "console=$consoledev,$baudrate $othbootargs;" \
667 "tftp ${kernel_addr} $bootfile;" \
668 "tftp ${fdt_addr} $fdtfile;" \
669 "bootm ${kernel_addr} - ${fdt_addr}"
670
671#define CONFIG_MMCBOOTCOMMAND \
672 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
673 "console=$consoledev,$baudrate $othbootargs;" \
674 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
675 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
676 "bootm ${kernel_addr} - ${fdt_addr}"
677
678#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
679
680
681#endif /* __CONFIG_H */