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Vikas Manochae66c49f2016-02-11 15:47:20 -08001/*
Vikas Manocha712f99a2017-02-12 10:25:45 -08002 * (C) Copyright 2017
Vikas Manochae66c49f2016-02-11 15:47:20 -08003 * Vikas Manocha, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
Vikas Manochae66c49f2016-02-11 15:47:20 -08007#include <common.h>
Vikas Manocha712f99a2017-02-12 10:25:45 -08008#include <clk-uclass.h>
9#include <dm.h>
Vikas Manochae66c49f2016-02-11 15:47:20 -080010#include <asm/io.h>
11#include <asm/arch/rcc.h>
12#include <asm/arch/stm32.h>
13#include <asm/arch/stm32_periph.h>
14
Michael Kurzbad51882017-01-22 16:04:24 +010015#define RCC_CR_HSION BIT(0)
16#define RCC_CR_HSEON BIT(16)
17#define RCC_CR_HSERDY BIT(17)
18#define RCC_CR_HSEBYP BIT(18)
19#define RCC_CR_CSSON BIT(19)
20#define RCC_CR_PLLON BIT(24)
21#define RCC_CR_PLLRDY BIT(25)
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090022
Michael Kurzbad51882017-01-22 16:04:24 +010023#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
24#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
25#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
26#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
27#define RCC_PLLCFGR_PLLSRC BIT(22)
28#define RCC_PLLCFGR_PLLM_SHIFT 0
29#define RCC_PLLCFGR_PLLN_SHIFT 6
30#define RCC_PLLCFGR_PLLP_SHIFT 16
31#define RCC_PLLCFGR_PLLQ_SHIFT 24
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090032
Michael Kurzbad51882017-01-22 16:04:24 +010033#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
34#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
35#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
36#define RCC_CFGR_SW0 BIT(0)
37#define RCC_CFGR_SW1 BIT(1)
38#define RCC_CFGR_SW_MASK GENMASK(1, 0)
39#define RCC_CFGR_SW_HSI 0
40#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
41#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
42#define RCC_CFGR_SWS0 BIT(2)
43#define RCC_CFGR_SWS1 BIT(3)
44#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
45#define RCC_CFGR_SWS_HSI 0
46#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
47#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
48#define RCC_CFGR_HPRE_SHIFT 4
49#define RCC_CFGR_PPRE1_SHIFT 10
50#define RCC_CFGR_PPRE2_SHIFT 13
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090051
52/*
53 * Offsets of some PWR registers
54 */
Michael Kurzbad51882017-01-22 16:04:24 +010055#define PWR_CR1_ODEN BIT(16)
56#define PWR_CR1_ODSWEN BIT(17)
57#define PWR_CSR1_ODRDY BIT(16)
58#define PWR_CSR1_ODSWRDY BIT(17)
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090059
60struct pll_psc {
61 u8 pll_m;
62 u16 pll_n;
63 u8 pll_p;
64 u8 pll_q;
65 u8 ahb_psc;
66 u8 apb1_psc;
67 u8 apb2_psc;
68};
69
Michael Kurzbad51882017-01-22 16:04:24 +010070#define AHB_PSC_1 0
71#define AHB_PSC_2 0x8
72#define AHB_PSC_4 0x9
73#define AHB_PSC_8 0xA
74#define AHB_PSC_16 0xB
75#define AHB_PSC_64 0xC
76#define AHB_PSC_128 0xD
77#define AHB_PSC_256 0xE
78#define AHB_PSC_512 0xF
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090079
Michael Kurzbad51882017-01-22 16:04:24 +010080#define APB_PSC_1 0
81#define APB_PSC_2 0x4
82#define APB_PSC_4 0x5
83#define APB_PSC_8 0x6
84#define APB_PSC_16 0x7
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090085
86#if !defined(CONFIG_STM32_HSE_HZ)
87#error "CONFIG_STM32_HSE_HZ not defined!"
88#else
89#if (CONFIG_STM32_HSE_HZ == 25000000)
90#if (CONFIG_SYS_CLK_FREQ == 200000000)
91/* 200 MHz */
92struct pll_psc sys_pll_psc = {
93 .pll_m = 25,
94 .pll_n = 400,
95 .pll_p = 2,
96 .pll_q = 8,
97 .ahb_psc = AHB_PSC_1,
98 .apb1_psc = APB_PSC_4,
99 .apb2_psc = APB_PSC_2
100};
101#endif
102#else
103#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
104#endif
105#endif
106
107int configure_clocks(void)
108{
109 /* Reset RCC configuration */
110 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
111 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
112 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
113 | RCC_CR_PLLON));
114 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
115 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
116 writel(0, &STM32_RCC->cir); /* Disable all interrupts */
117
118 /* Configure for HSE+PLL operation */
119 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
120 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
121 ;
122
123 setbits_le32(&STM32_RCC->cfgr, ((
124 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
125 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
126 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
127
128 /* Configure the main PLL */
129 uint32_t pllcfgr = 0;
130 pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
131 pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
132 pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
133 pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
134 pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
135 writel(pllcfgr, &STM32_RCC->pllcfgr);
136
137 /* Enable the main PLL */
138 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
139 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
140 ;
141
142 /* Enable high performance mode, System frequency up to 200 MHz */
143 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
144 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
145 /* Infinite wait! */
146 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
147 ;
148 /* Enable the Over-drive switch */
149 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
150 /* Infinite wait! */
151 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
152 ;
153
154 stm32_flash_latency_cfg(5);
155 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
156 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
157
158 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
159 RCC_CFGR_SWS_PLL)
160 ;
161
162 return 0;
163}
164
165unsigned long clock_get(enum clock clck)
166{
167 u32 sysclk = 0;
168 u32 shift = 0;
169 /* Prescaler table lookups for clock computation */
170 u8 ahb_psc_table[16] = {
171 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
172 };
173 u8 apb_psc_table[8] = {
174 0, 0, 0, 0, 1, 2, 3, 4
175 };
176
177 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
178 RCC_CFGR_SWS_PLL) {
179 u16 pllm, plln, pllp;
180 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
181 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
182 >> RCC_PLLCFGR_PLLN_SHIFT);
183 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
184 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
185 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
186 }
187
188 switch (clck) {
189 case CLOCK_CORE:
190 return sysclk;
191 break;
192 case CLOCK_AHB:
193 shift = ahb_psc_table[(
194 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
195 >> RCC_CFGR_HPRE_SHIFT)];
196 return sysclk >>= shift;
197 break;
198 case CLOCK_APB1:
199 shift = apb_psc_table[(
200 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
201 >> RCC_CFGR_PPRE1_SHIFT)];
202 return sysclk >>= shift;
203 break;
204 case CLOCK_APB2:
205 shift = apb_psc_table[(
206 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
207 >> RCC_CFGR_PPRE2_SHIFT)];
208 return sysclk >>= shift;
209 break;
210 default:
211 return 0;
212 break;
213 }
214}
215
Vikas Manocha712f99a2017-02-12 10:25:45 -0800216static int stm32_clk_enable(struct clk *clk)
217{
218 u32 offset = clk->id / 32;
219 u32 bit_index = clk->id % 32;
220
221 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
222 __func__, clk->id, offset, bit_index);
223 setbits_le32(&STM32_RCC->ahb1enr + offset, BIT(bit_index));
224
225 return 0;
226}
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +0900227
Vikas Manochae66c49f2016-02-11 15:47:20 -0800228void clock_setup(int peripheral)
229{
230 switch (peripheral) {
Michael Kurz081de092017-01-22 16:04:26 +0100231 case SYSCFG_CLOCK_CFG:
232 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
233 break;
234 case TIMER2_CLOCK_CFG:
235 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
236 break;
Michael Kurzb20b70f2017-01-22 16:04:27 +0100237 case STMMAC_CLOCK_CFG:
238 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
239 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
240 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
241 break;
Vikas Manochae66c49f2016-02-11 15:47:20 -0800242 default:
243 break;
244 }
245}
Vikas Manocha712f99a2017-02-12 10:25:45 -0800246
247static int stm32_clk_probe(struct udevice *dev)
248{
249 debug("%s: stm32_clk_probe\n", __func__);
250 configure_clocks();
251
252 return 0;
253}
254
255static int stm32_clk_of_xlate(struct clk *clk,
256 struct fdtdec_phandle_args *args)
257{
258 debug("%s(clk=%p)\n", __func__, clk);
259
260 if (args->args_count != 2) {
261 debug("Invaild args_count: %d\n", args->args_count);
262 return -EINVAL;
263 }
264
265 if (args->args_count)
266 clk->id = args->args[1];
267 else
268 clk->id = 0;
269
270 return 0;
271}
272
273static struct clk_ops stm32_clk_ops = {
274 .of_xlate = stm32_clk_of_xlate,
275 .enable = stm32_clk_enable,
276};
277
278static const struct udevice_id stm32_clk_ids[] = {
279 { .compatible = "st,stm32f42xx-rcc"},
280 {}
281};
282
283U_BOOT_DRIVER(stm32f7_clk) = {
284 .name = "stm32f7_clk",
285 .id = UCLASS_CLK,
286 .of_match = stm32_clk_ids,
287 .ops = &stm32_clk_ops,
288 .probe = stm32_clk_probe,
289 .flags = DM_FLAG_PRE_RELOC,
290};