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Vikas Manochae66c49f2016-02-11 15:47:20 -08001/*
2 * (C) Copyright 2016
3 * Vikas Manocha, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/rcc.h>
11#include <asm/arch/stm32.h>
12#include <asm/arch/stm32_periph.h>
13
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090014#define RCC_CR_HSION (1 << 0)
15#define RCC_CR_HSEON (1 << 16)
16#define RCC_CR_HSERDY (1 << 17)
17#define RCC_CR_HSEBYP (1 << 18)
18#define RCC_CR_CSSON (1 << 19)
19#define RCC_CR_PLLON (1 << 24)
20#define RCC_CR_PLLRDY (1 << 25)
21
22#define RCC_PLLCFGR_PLLM_MASK 0x3F
23#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
24#define RCC_PLLCFGR_PLLP_MASK 0x30000
25#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
26#define RCC_PLLCFGR_PLLSRC (1 << 22)
27#define RCC_PLLCFGR_PLLM_SHIFT 0
28#define RCC_PLLCFGR_PLLN_SHIFT 6
29#define RCC_PLLCFGR_PLLP_SHIFT 16
30#define RCC_PLLCFGR_PLLQ_SHIFT 24
31
32#define RCC_CFGR_AHB_PSC_MASK 0xF0
33#define RCC_CFGR_APB1_PSC_MASK 0x1C00
34#define RCC_CFGR_APB2_PSC_MASK 0xE000
35#define RCC_CFGR_SW0 (1 << 0)
36#define RCC_CFGR_SW1 (1 << 1)
37#define RCC_CFGR_SW_MASK 0x3
38#define RCC_CFGR_SW_HSI 0
39#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
40#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
41#define RCC_CFGR_SWS0 (1 << 2)
42#define RCC_CFGR_SWS1 (1 << 3)
43#define RCC_CFGR_SWS_MASK 0xC
44#define RCC_CFGR_SWS_HSI 0
45#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
46#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
47#define RCC_CFGR_HPRE_SHIFT 4
48#define RCC_CFGR_PPRE1_SHIFT 10
49#define RCC_CFGR_PPRE2_SHIFT 13
50
51#define RCC_APB1ENR_PWREN (1 << 28)
52
53/*
54 * RCC USART specific definitions
55 */
56#define RCC_ENR_USART1EN (1 << 4)
57#define RCC_ENR_USART2EN (1 << 17)
58#define RCC_ENR_USART3EN (1 << 18)
59#define RCC_ENR_USART6EN (1 << 5)
60
61/*
62 * Offsets of some PWR registers
63 */
64#define PWR_CR1_ODEN (1 << 16)
65#define PWR_CR1_ODSWEN (1 << 17)
66#define PWR_CSR1_ODRDY (1 << 16)
67#define PWR_CSR1_ODSWRDY (1 << 17)
68
69
70/*
71 * RCC GPIO specific definitions
72 */
73#define RCC_ENR_GPIO_A_EN (1 << 0)
74#define RCC_ENR_GPIO_B_EN (1 << 1)
75#define RCC_ENR_GPIO_C_EN (1 << 2)
76#define RCC_ENR_GPIO_D_EN (1 << 3)
77#define RCC_ENR_GPIO_E_EN (1 << 4)
78#define RCC_ENR_GPIO_F_EN (1 << 5)
79#define RCC_ENR_GPIO_G_EN (1 << 6)
80#define RCC_ENR_GPIO_H_EN (1 << 7)
81#define RCC_ENR_GPIO_I_EN (1 << 8)
82#define RCC_ENR_GPIO_J_EN (1 << 9)
83#define RCC_ENR_GPIO_K_EN (1 << 10)
84
85struct pll_psc {
86 u8 pll_m;
87 u16 pll_n;
88 u8 pll_p;
89 u8 pll_q;
90 u8 ahb_psc;
91 u8 apb1_psc;
92 u8 apb2_psc;
93};
94
95#define AHB_PSC_1 0
96#define AHB_PSC_2 0x8
97#define AHB_PSC_4 0x9
98#define AHB_PSC_8 0xA
99#define AHB_PSC_16 0xB
100#define AHB_PSC_64 0xC
101#define AHB_PSC_128 0xD
102#define AHB_PSC_256 0xE
103#define AHB_PSC_512 0xF
104
105#define APB_PSC_1 0
106#define APB_PSC_2 0x4
107#define APB_PSC_4 0x5
108#define APB_PSC_8 0x6
109#define APB_PSC_16 0x7
110
111#if !defined(CONFIG_STM32_HSE_HZ)
112#error "CONFIG_STM32_HSE_HZ not defined!"
113#else
114#if (CONFIG_STM32_HSE_HZ == 25000000)
115#if (CONFIG_SYS_CLK_FREQ == 200000000)
116/* 200 MHz */
117struct pll_psc sys_pll_psc = {
118 .pll_m = 25,
119 .pll_n = 400,
120 .pll_p = 2,
121 .pll_q = 8,
122 .ahb_psc = AHB_PSC_1,
123 .apb1_psc = APB_PSC_4,
124 .apb2_psc = APB_PSC_2
125};
126#endif
127#else
128#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
129#endif
130#endif
131
132int configure_clocks(void)
133{
134 /* Reset RCC configuration */
135 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
136 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
137 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
138 | RCC_CR_PLLON));
139 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
140 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
141 writel(0, &STM32_RCC->cir); /* Disable all interrupts */
142
143 /* Configure for HSE+PLL operation */
144 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
145 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
146 ;
147
148 setbits_le32(&STM32_RCC->cfgr, ((
149 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
150 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
151 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
152
153 /* Configure the main PLL */
154 uint32_t pllcfgr = 0;
155 pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
156 pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
157 pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
158 pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
159 pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
160 writel(pllcfgr, &STM32_RCC->pllcfgr);
161
162 /* Enable the main PLL */
163 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
164 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
165 ;
166
167 /* Enable high performance mode, System frequency up to 200 MHz */
168 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
169 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
170 /* Infinite wait! */
171 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
172 ;
173 /* Enable the Over-drive switch */
174 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
175 /* Infinite wait! */
176 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
177 ;
178
179 stm32_flash_latency_cfg(5);
180 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
181 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
182
183 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
184 RCC_CFGR_SWS_PLL)
185 ;
186
187 return 0;
188}
189
190unsigned long clock_get(enum clock clck)
191{
192 u32 sysclk = 0;
193 u32 shift = 0;
194 /* Prescaler table lookups for clock computation */
195 u8 ahb_psc_table[16] = {
196 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
197 };
198 u8 apb_psc_table[8] = {
199 0, 0, 0, 0, 1, 2, 3, 4
200 };
201
202 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
203 RCC_CFGR_SWS_PLL) {
204 u16 pllm, plln, pllp;
205 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
206 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
207 >> RCC_PLLCFGR_PLLN_SHIFT);
208 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
209 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
210 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
211 }
212
213 switch (clck) {
214 case CLOCK_CORE:
215 return sysclk;
216 break;
217 case CLOCK_AHB:
218 shift = ahb_psc_table[(
219 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
220 >> RCC_CFGR_HPRE_SHIFT)];
221 return sysclk >>= shift;
222 break;
223 case CLOCK_APB1:
224 shift = apb_psc_table[(
225 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
226 >> RCC_CFGR_PPRE1_SHIFT)];
227 return sysclk >>= shift;
228 break;
229 case CLOCK_APB2:
230 shift = apb_psc_table[(
231 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
232 >> RCC_CFGR_PPRE2_SHIFT)];
233 return sysclk >>= shift;
234 break;
235 default:
236 return 0;
237 break;
238 }
239}
240
241
Vikas Manochae66c49f2016-02-11 15:47:20 -0800242void clock_setup(int peripheral)
243{
244 switch (peripheral) {
245 case USART1_CLOCK_CFG:
246 setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
247 break;
248 case GPIO_A_CLOCK_CFG:
249 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
250 break;
251 case GPIO_B_CLOCK_CFG:
252 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN);
253 break;
254 case GPIO_C_CLOCK_CFG:
255 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN);
256 break;
257 case GPIO_D_CLOCK_CFG:
258 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN);
259 break;
260 case GPIO_E_CLOCK_CFG:
261 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN);
262 break;
263 case GPIO_F_CLOCK_CFG:
264 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN);
265 break;
266 case GPIO_G_CLOCK_CFG:
267 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN);
268 break;
269 case GPIO_H_CLOCK_CFG:
270 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN);
271 break;
272 case GPIO_I_CLOCK_CFG:
273 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN);
274 break;
275 case GPIO_J_CLOCK_CFG:
276 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN);
277 break;
278 case GPIO_K_CLOCK_CFG:
279 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);
280 break;
281 default:
282 break;
283 }
284}