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Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +00001/*
2 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __CONFIG_IGEP0033_H
15#define __CONFIG_IGEP0033_H
16
17#define CONFIG_AM33XX
SRICHARAN R4a0eb752013-04-24 00:41:24 +000018#define CONFIG_OMAP
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000019
20#include <asm/arch/omap.h>
21
22/* Mach type */
23#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */
24#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033
25
26/* Clock defines */
27#define V_OSCK 24000000 /* Clock output from T2 */
28#define V_SCLK (V_OSCK)
29
30/* DMA defines */
31#define CONFIG_DMA_COHERENT
32#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
33
34#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
35#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
36#define CONFIG_SYS_LONGHELP /* undef to save memory */
37#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
38#define CONFIG_SYS_PROMPT "U-Boot# "
39#define CONFIG_SYS_NO_FLASH
40
41/* Display cpuinfo */
42#define CONFIG_DISPLAY_CPUINFO
43
44/* Commands to include */
45#include <config_cmd_default.h>
46
47#define CONFIG_CMD_ASKENV
48#define CONFIG_CMD_BOOTZ
49#define CONFIG_CMD_DHCP
50#define CONFIG_CMD_ECHO
51#define CONFIG_CMD_EXT4
52#define CONFIG_CMD_FAT
53#define CONFIG_CMD_FS_GENERIC
54#define CONFIG_CMD_MMC
55#define CONFIG_CMD_MTDPARTS
56#define CONFIG_CMD_NAND
57#define CONFIG_CMD_NET
58#define CONFIG_CMD_PING
59#define CONFIG_CMD_UBI
60#define CONFIG_CMD_UBIFS
61
62/*
63 * Because the issues explained in doc/README.memory-test, the "mtest command
64 * is considered deprecated. It should not be enabled in most normal ports of
65 * U-Boot.
66 */
67#undef CONFIG_CMD_MEMTEST
68
69#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
70#define CONFIG_ENV_VARS_UBOOT_CONFIG
71#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
72#define CONFIG_EXTRA_ENV_SETTINGS \
73 "loadaddr=0x80200000\0" \
74 "rdaddr=0x81000000\0" \
75 "bootfile=/boot/uImage\0" \
76 "console=ttyO0,115200n8\0" \
77 "optargs=\0" \
78 "mmcdev=0\0" \
79 "mmcroot=/dev/mmcblk0p2 rw\0" \
80 "mmcrootfstype=ext4 rootwait\0" \
81 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
82 "ramrootfstype=ext2\0" \
83 "mmcargs=setenv bootargs console=${console} " \
84 "${optargs} " \
85 "root=${mmcroot} " \
86 "rootfstype=${mmcrootfstype}\0" \
87 "bootenv=uEnv.txt\0" \
88 "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
89 "importbootenv=echo Importing environment from mmc ...; " \
90 "env import -t $loadaddr $filesize\0" \
91 "ramargs=setenv bootargs console=${console} " \
92 "${optargs} " \
93 "root=${ramroot} " \
94 "rootfstype=${ramrootfstype}\0" \
95 "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
96 "loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
97 "loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
98 "mmcboot=echo Booting from mmc ...; " \
99 "run mmcargs; " \
100 "bootm ${loadaddr}\0" \
101 "ramboot=echo Booting from ramdisk ...; " \
102 "run ramargs; " \
103 "bootm ${loadaddr}\0" \
104
105#define CONFIG_BOOTCOMMAND \
106 "mmc dev ${mmcdev}; if mmc rescan; then " \
107 "echo SD/MMC found on device ${mmcdev};" \
108 "if run loadbootenv; then " \
109 "echo Loaded environment from ${bootenv};" \
110 "run importbootenv;" \
111 "fi;" \
112 "if test -n $uenvcmd; then " \
113 "echo Running uenvcmd ...;" \
114 "run uenvcmd;" \
115 "fi;" \
116 "if run loaduimage; then " \
117 "run mmcboot;" \
118 "fi;" \
119 "fi;" \
120
121/* Max number of command args */
122#define CONFIG_SYS_MAXARGS 16
123
124/* Console I/O Buffer Size */
125#define CONFIG_SYS_CBSIZE 512
126
127/* Print Buffer Size */
128#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
129 + sizeof(CONFIG_SYS_PROMPT) + 16)
130
131/* Boot Argument Buffer Size */
132#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
133#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
134#define CONFIG_SYS_HZ 1000 /* 1ms clock */
135
136/* Physical Memory Map */
137#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
138#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
139#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
140
141#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
142#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
143 GENERATED_GBL_DATA_SIZE)
144/* Platform/Board specific defs */
145#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
146#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
147#define CONFIG_SYS_HZ 1000
148
149/* NS16550 Configuration */
150#define CONFIG_SYS_NS16550
151#define CONFIG_SYS_NS16550_SERIAL
152#define CONFIG_SYS_NS16550_REG_SIZE (-4)
153#define CONFIG_SYS_NS16550_CLK (48000000)
154#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
155
156#define CONFIG_SERIAL_MULTI
157#define CONFIG_CONS_INDEX 1
158#define CONFIG_BAUDRATE 115200
159
SRICHARAN R47c6ea02013-04-24 00:41:25 +0000160/* CPU */
161#define CONFIG_ARCH_CPU_INIT
162
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000163#define CONFIG_ENV_OVERWRITE 1
164#define CONFIG_SYS_CONSOLE_INFO_QUIET
165
166/* MMC support */
167#define CONFIG_MMC
168#define CONFIG_GENERIC_MMC
169#define CONFIG_OMAP_HSMMC
170#define CONFIG_DOS_PARTITION
171
172/* GPIO support */
173#define CONFIG_OMAP_GPIO
174
175/* Ethernet support */
176#define CONFIG_DRIVER_TI_CPSW
177#define CONFIG_MII
178#define CONFIG_BOOTP_DEFAULT
179#define CONFIG_BOOTP_DNS
180#define CONFIG_BOOTP_DNS2
181#define CONFIG_BOOTP_SEND_HOSTNAME
182#define CONFIG_BOOTP_GATEWAY
183#define CONFIG_BOOTP_SUBNETMASK
184#define CONFIG_NET_RETRY_COUNT 10
185#define CONFIG_NET_MULTI
186#define CONFIG_PHYLIB
187#define CONFIG_PHY_ADDR 0
188#define CONFIG_PHY_SMSC
189
190/* NAND support */
191#define CONFIG_NAND
192#define CONFIG_NAND_OMAP_GPMC
193#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
194#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
195#define CONFIG_SYS_MAX_NAND_DEVICE 1
196#define CONFIG_SYS_NAND_ONFI_DETECTION 1
197#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
198#define CONFIG_ENV_IS_IN_NAND
199#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
200
201#define CONFIG_MTD_PARTITIONS
202#define CONFIG_MTD_DEVICE
203#define CONFIG_RBTREE
204#define CONFIG_LZO
205
206#define MTDIDS_DEFAULT "nand0=nand"
207#define MTDPARTS_DEFAULT "mtdparts=nand:512k(SPL),"\
208 "1m(U-Boot),128k(U-Boot Env),"\
209 "5m(Kernel),-(File System)"
210
211/* Unsupported features */
212#undef CONFIG_USE_IRQ
213
214/* Defines for SPL */
215#define CONFIG_SPL
216#define CONFIG_SPL_FRAMEWORK
Tom Rini320d9742013-05-31 10:48:03 -0400217/*
Tom Riniedfcf852013-06-06 08:57:45 -0400218 * Place the image at the start of the ROM defined image space.
Tom Rini320d9742013-05-31 10:48:03 -0400219 * We limit our size to the ROM-defined downloaded image area, and use the
220 * rest of the space for stack.
221 */
Tom Riniedfcf852013-06-06 08:57:45 -0400222#define CONFIG_SPL_TEXT_BASE 0x402F0400
Tom Rini320d9742013-05-31 10:48:03 -0400223#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000224#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
225
226#define CONFIG_SPL_BSS_START_ADDR 0x80000000
227#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
228
229#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
230#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
231#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
232#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
233#define CONFIG_SPL_MMC_SUPPORT
234#define CONFIG_SPL_FAT_SUPPORT
235#define CONFIG_SPL_LIBCOMMON_SUPPORT
236#define CONFIG_SPL_LIBDISK_SUPPORT
237#define CONFIG_SPL_LIBGENERIC_SUPPORT
238#define CONFIG_SPL_SERIAL_SUPPORT
239#define CONFIG_SPL_GPIO_SUPPORT
240#define CONFIG_SPL_YMODEM_SUPPORT
241#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
242
243#define CONFIG_SPL_BOARD_INIT
244#define CONFIG_SPL_NAND_AM33XX_BCH
245#define CONFIG_SPL_NAND_SUPPORT
246#define CONFIG_SPL_NAND_BASE
247#define CONFIG_SPL_NAND_DRIVERS
248#define CONFIG_SPL_NAND_ECC
249#define CONFIG_SYS_NAND_5_ADDR_CYCLE
250#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
251 CONFIG_SYS_NAND_PAGE_SIZE)
252#define CONFIG_SYS_NAND_PAGE_SIZE 2048
253#define CONFIG_SYS_NAND_OOBSIZE 64
254#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
255#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
256#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
257 10, 11, 12, 13, 14, 15, 16, 17, \
258 18, 19, 20, 21, 22, 23, 24, 25, \
259 26, 27, 28, 29, 30, 31, 32, 33, \
260 34, 35, 36, 37, 38, 39, 40, 41, \
261 42, 43, 44, 45, 46, 47, 48, 49, \
262 50, 51, 52, 53, 54, 55, 56, 57, }
263
264#define CONFIG_SYS_NAND_ECCSIZE 512
265#define CONFIG_SYS_NAND_ECCBYTES 14
266
267#define CONFIG_SYS_NAND_ECCSTEPS 4
268#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
269 CONFIG_SYS_NAND_ECCSTEPS)
270
271#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
272
273#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
274
275/*
276 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
277 * 64 bytes before this address should be set aside for u-boot.img's
278 * header. That is 0x800FFFC0--0x80100000 should not be used for any
279 * other needs.
280 */
281#define CONFIG_SYS_TEXT_BASE 0x80800000
282#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
283#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
284
285/*
286 * Since SPL did pll and ddr initialization for us,
287 * we don't need to do it twice.
288 */
289#ifndef CONFIG_SPL_BUILD
290#define CONFIG_SKIP_LOWLEVEL_INIT
291#endif
292
293#endif /* ! __CONFIG_IGEP0033_H */