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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002
6 * Gregory E. Allen, gallen@arlut.utexas.edu
7 * Matthew E. Karger, karger@arlut.utexas.edu
8 * Applied Research Laboratories, The University of Texas at Austin
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 *
31 * Configuration settings for the utx8245 board.
32 *
33 */
34
35/* ------------------------------------------------------------------------- */
36
37/*
38 * board/config.h - configuration options, board specific
39 */
40
41#ifndef __CONFIG_H
42#define __CONFIG_H
43
44/*
45 * High Level Configuration Options
46 * (easy to change)
47 */
48
49#define CONFIG_MPC824X 1
50#define CONFIG_MPC8245 1
51#define CONFIG_UTX8245 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020052
53#define CONFIG_SYS_TEXT_BASE 0xFFF00000
54
wdenkc6097192002-11-03 00:24:07 +000055#define DEBUG 1
56
wdenk7a8e9bed2003-05-31 18:35:21 +000057#define CONFIG_IDENT_STRING " [UTX5] "
58
wdenkc6097192002-11-03 00:24:07 +000059#define CONFIG_CONS_INDEX 1
60#define CONFIG_BAUDRATE 57600
wdenkc6097192002-11-03 00:24:07 +000061
wdenk7a8e9bed2003-05-31 18:35:21 +000062#define CONFIG_BOOTDELAY 2
Stefan Roesef2302d42008-08-06 14:05:38 +020063#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
wdenk7a8e9bed2003-05-31 18:35:21 +000064#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +000065#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
wdenk7a8e9bed2003-05-31 18:35:21 +000066#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
67#define CONFIG_SERVERIP 10.8.17.105 /* Spree */
wdenk7a8e9bed2003-05-31 18:35:21 +000068
69#define CONFIG_EXTRA_ENV_SETTINGS \
70 "kernel_addr=FFA00000\0" \
71 "ramdisk_addr=FF800000\0" \
72 "u-boot_startaddr=FFB00000\0" \
73 "u-boot_endaddr=FFB2FFFF\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010074 "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
75nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
76 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
77 "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
78 "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
79 "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
80 "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
82 "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
83 "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
84${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
85${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
86protect on ${u-boot_startaddr} ${u-boot_endaddr}"
wdenk7a8e9bed2003-05-31 18:35:21 +000087
wdenkc6097192002-11-03 00:24:07 +000088#define CONFIG_ENV_OVERWRITE
89
wdenkc6097192002-11-03 00:24:07 +000090
Jon Loeliger6c18eb92007-07-04 22:33:38 -050091/*
Jon Loeliger079a1362007-07-10 10:12:10 -050092 * BOOTP options
93 */
94#define CONFIG_BOOTP_BOOTFILESIZE
95#define CONFIG_BOOTP_BOOTPATH
96#define CONFIG_BOOTP_GATEWAY
97#define CONFIG_BOOTP_HOSTNAME
98
99
100/*
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500101 * Command line configuration.
wdenkc6097192002-11-03 00:24:07 +0000102 */
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500103#include <config_cmd_default.h>
104
105#define CONFIG_CMD_BDI
106#define CONFIG_CMD_PCI
107#define CONFIG_CMD_FLASH
108#define CONFIG_CMD_MEMORY
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500109#define CONFIG_CMD_SAVEENV
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500110#define CONFIG_CMD_CONSOLE
111#define CONFIG_CMD_LOADS
112#define CONFIG_CMD_LOADB
113#define CONFIG_CMD_IMI
114#define CONFIG_CMD_CACHE
115#define CONFIG_CMD_REGINFO
116#define CONFIG_CMD_NET
117#define CONFIG_CMD_DHCP
118#define CONFIG_CMD_I2C
119#define CONFIG_CMD_DATE
wdenkc6097192002-11-03 00:24:07 +0000120
121
122/*
123 * Miscellaneous configurable options
124 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_LONGHELP /* undef to save memory */
126#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
127#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000128
129/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenkc6097192002-11-03 00:24:07 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
134#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkc6097192002-11-03 00:24:07 +0000135
136
137/*-----------------------------------------------------------------------
138 * PCI configuration
139 *-----------------------------------------------------------------------
140 */
141#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000142#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
wdenkc6097192002-11-03 00:24:07 +0000143#undef CONFIG_PCI_PNP
144#define CONFIG_PCI_SCAN_SHOW
wdenkc6097192002-11-03 00:24:07 +0000145#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000147#define CONFIG_EEPRO100_SROM_WRITE
wdenkc6097192002-11-03 00:24:07 +0000148
wdenk7a8e9bed2003-05-31 18:35:21 +0000149#define PCI_ENET0_IOADDR 0xF0000000
150#define PCI_ENET0_MEMADDR 0xF0000000
151
152#define PCI_FIREWIRE_IOADDR 0xF1000000
153#define PCI_FIREWIRE_MEMADDR 0xF1000000
154/*
155#define PCI_ENET0_IOADDR 0xFE000000
wdenkc6097192002-11-03 00:24:07 +0000156#define PCI_ENET0_MEMADDR 0x80000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000157
wdenkc6097192002-11-03 00:24:07 +0000158#define PCI_FIREWIRE_IOADDR 0x81000000
159#define PCI_FIREWIRE_MEMADDR 0x81000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000160*/
wdenkc6097192002-11-03 00:24:07 +0000161
162/*-----------------------------------------------------------------------
163 * Start addresses for the final memory configuration
164 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_SDRAM_BASE 0x00000000
168#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 256MB */
169/*#define CONFIG_SYS_VERY_BIG_RAM 1 */
wdenkc6097192002-11-03 00:24:07 +0000170
wdenk7a8e9bed2003-05-31 18:35:21 +0000171/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
172 * is actually located at FFF00100. Therefore, U-Boot is
173 * physically located at 0xFFB0_0000, but is also mirrored at
174 * 0xFFF0_0000.
wdenkc6097192002-11-03 00:24:07 +0000175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkc6097192002-11-03 00:24:07 +0000179
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200180#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
183#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185/*#define CONFIG_SYS_DRAM_TEST 1 */
186#define CONFIG_SYS_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
187#define CONFIG_SYS_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */
wdenkc6097192002-11-03 00:24:07 +0000188 /* vectors and U-Boot */
189
190
191/*--------------------------------------------------------------------
192 * Definitions for initial stack pointer and data area
193 *------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
wdenkc6097192002-11-03 00:24:07 +0000195 /* initial data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200197#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
198#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200199#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000200
201/*--------------------------------------------------------------------
202 * NS16550 Configuration
203 *------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_NS16550
205#define CONFIG_SYS_NS16550_SERIAL
wdenkc6097192002-11-03 00:24:07 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkc6097192002-11-03 00:24:07 +0000208
wdenk7a8e9bed2003-05-31 18:35:21 +0000209#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210# define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk7a8e9bed2003-05-31 18:35:21 +0000211#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212# define CONFIG_SYS_NS16550_CLK 33000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000213#endif
wdenkc6097192002-11-03 00:24:07 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
216#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
217#define CONFIG_SYS_NS16550_COM3 0xFF000000
218#define CONFIG_SYS_NS16550_COM4 0xFF000008
wdenkc6097192002-11-03 00:24:07 +0000219
220/*--------------------------------------------------------------------
221 * Low Level Configuration Settings
222 * (address mappings, register initial values, etc.)
223 * You should know what you are doing if you make changes here.
224 * For the detail description refer to the MPC8240 user's manual.
225 *------------------------------------------------------------------*/
226
227#define CONFIG_SYS_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_HZ 1000
wdenkc6097192002-11-03 00:24:07 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230/*#define CONFIG_SYS_ETH_DEV_FN 0x7800 */
231/*#define CONFIG_SYS_ETH_IOBASE 0x00104000 */
wdenkc6097192002-11-03 00:24:07 +0000232
wdenk7a8e9bed2003-05-31 18:35:21 +0000233/*--------------------------------------------------------------------
234 * I2C Configuration
235 *------------------------------------------------------------------*/
236#if 1
237#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Heiko Schocherea818db2013-01-29 08:53:15 +0100238#define CONFIG_SYS_I2C_SPEED 400000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk7a8e9bed2003-05-31 18:35:21 +0000240#endif
241
242#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */
243 /* Philips PCF8563 RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
wdenkc6097192002-11-03 00:24:07 +0000245
246/*--------------------------------------------------------------------
247 * Memory Control Configuration Register values
248 * - see sec. 4.12 of MPC8245 UM
249 *------------------------------------------------------------------*/
250
wdenk7a8e9bed2003-05-31 18:35:21 +0000251/**** MCCR1 ****/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_ROMNAL 0
253#define CONFIG_SYS_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2,
wdenk7a8e9bed2003-05-31 18:35:21 +0000254 mem_freq = 100MHz */
wdenkc6097192002-11-03 00:24:07 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_BANK7_ROW 0 /* SDRAM bank 7-0 row address */
257#define CONFIG_SYS_BANK6_ROW 0 /* bit count */
258#define CONFIG_SYS_BANK5_ROW 0
259#define CONFIG_SYS_BANK4_ROW 0
260#define CONFIG_SYS_BANK3_ROW 0
261#define CONFIG_SYS_BANK2_ROW 0
262#define CONFIG_SYS_BANK1_ROW 2
263#define CONFIG_SYS_BANK0_ROW 2
wdenk7a8e9bed2003-05-31 18:35:21 +0000264
265/**** MCCR2, refresh interval clock cycles ****/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_REFINT 480 /* 33 MHz SDRAM clock was 480 */
wdenkc6097192002-11-03 00:24:07 +0000267
wdenk7a8e9bed2003-05-31 18:35:21 +0000268/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_BSTOPRE 1023 /* burst to precharge[0..9], */
wdenkc6097192002-11-03 00:24:07 +0000270 /* sets open page interval */
271
wdenk7a8e9bed2003-05-31 18:35:21 +0000272/**** MCCR3 ****/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_REFREC 7 /* Refresh to activate interval, trc */
wdenkc6097192002-11-03 00:24:07 +0000274
wdenk7a8e9bed2003-05-31 18:35:21 +0000275/**** MCCR4 ****/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_PRETOACT 2 /* trp */
277#define CONFIG_SYS_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */
278#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
279#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
280#define CONFIG_SYS_ACTORW 2 /* trcd min */
281#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
282#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
283#define CONFIG_SYS_EXTROM 0 /* we don't need extended ROM space */
284#define CONFIG_SYS_REGDIMM 0
wdenkc6097192002-11-03 00:24:07 +0000285
286/* calculate according to formula in sec. 6-22 of 8245 UM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_PGMAX 50 /* how long the 8245 retains the */
wdenkc6097192002-11-03 00:24:07 +0000288 /* currently accessed page in memory */
289 /* was 45 */
290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
wdenk7a8e9bed2003-05-31 18:35:21 +0000292 /* bits 7,6, and 3-0 MUST be 0 */
wdenkc6097192002-11-03 00:24:07 +0000293
wdenk7a8e9bed2003-05-31 18:35:21 +0000294#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_DLL_MAX_DELAY 0x04
wdenk7a8e9bed2003-05-31 18:35:21 +0000296#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_DLL_MAX_DELAY 0
wdenk7a8e9bed2003-05-31 18:35:21 +0000298#endif
299#if 0 /* need for 33MHz SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_DLL_EXTEND 0x80
wdenk7a8e9bed2003-05-31 18:35:21 +0000301#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_DLL_EXTEND 0
wdenk7a8e9bed2003-05-31 18:35:21 +0000303#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_PCI_HOLD_DEL 0x20
wdenkc6097192002-11-03 00:24:07 +0000305
306
307/* Memory bank settings.
308 * Only bits 20-29 are actually used from these values to set the
309 * start/end addresses. The upper two bits will always be 0, and the lower
310 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
311 * address. Refer to the MPC8245 user manual.
312 */
313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_BANK0_START 0x00000000
315#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
316#define CONFIG_SYS_BANK0_ENABLE 1
317#define CONFIG_SYS_BANK1_START CONFIG_SYS_MAX_RAM_SIZE/2
318#define CONFIG_SYS_BANK1_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
319#define CONFIG_SYS_BANK1_ENABLE 1
320#define CONFIG_SYS_BANK2_START 0x3ff00000 /* not available in this design */
321#define CONFIG_SYS_BANK2_END 0x3fffffff
322#define CONFIG_SYS_BANK2_ENABLE 0
323#define CONFIG_SYS_BANK3_START 0x3ff00000
324#define CONFIG_SYS_BANK3_END 0x3fffffff
325#define CONFIG_SYS_BANK3_ENABLE 0
326#define CONFIG_SYS_BANK4_START 0x3ff00000
327#define CONFIG_SYS_BANK4_END 0x3fffffff
328#define CONFIG_SYS_BANK4_ENABLE 0
329#define CONFIG_SYS_BANK5_START 0x3ff00000
330#define CONFIG_SYS_BANK5_END 0x3fffffff
331#define CONFIG_SYS_BANK5_ENABLE 0
332#define CONFIG_SYS_BANK6_START 0x3ff00000
333#define CONFIG_SYS_BANK6_END 0x3fffffff
334#define CONFIG_SYS_BANK6_ENABLE 0
335#define CONFIG_SYS_BANK7_START 0x3ff00000
336#define CONFIG_SYS_BANK7_END 0x3fffffff
337#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000338
wdenk7a8e9bed2003-05-31 18:35:21 +0000339/*--------------------------------------------------------------------*/
340/* 4.4 - Output Driver Control Register */
341/*--------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_ODCR 0xe5
wdenkc6097192002-11-03 00:24:07 +0000343
wdenk7a8e9bed2003-05-31 18:35:21 +0000344/*--------------------------------------------------------------------*/
345/* 4.8 - Error Handling Registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
347#define CONFIG_SYS_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
wdenkc6097192002-11-03 00:24:07 +0000348
349/* SDRAM 0-256 MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
351/*#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
352#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000353
354/* stack in dcache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
356#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000357
wdenkc6097192002-11-03 00:24:07 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
360#define CONFIG_SYS_IBAT2U (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
wdenk7a8e9bed2003-05-31 18:35:21 +0000361
362/* PCI memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363/*#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
364/*#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
wdenk7a8e9bed2003-05-31 18:35:21 +0000365
366/*Flash, config addrs, etc. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
368#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
371#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
372#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
373#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
374#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
375#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
376#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
377#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000378
379/*
380 * For booting Linux, the board info and command line data
381 * have to be in the first 8 MB of memory, since this is
382 * the maximum mapped by the Linux kernel during initialization.
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000385
386/*-----------------------------------------------------------------------
wdenk7a8e9bed2003-05-31 18:35:21 +0000387 * FLASH organization
388 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_FLASH_BASE 0xFF800000
390#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
wdenkc6097192002-11-03 00:24:07 +0000391
wdenk7a8e9bed2003-05-31 18:35:21 +0000392/* NOTE: environment is not EMBEDDED in the u-boot code.
393 It's stored in flash in its own separate sector. */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200394#define CONFIG_ENV_IS_IN_FLASH 1
wdenk7a8e9bed2003-05-31 18:35:21 +0000395
396#if 1 /* AMD AM29LV033C */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200398#define CONFIG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */
399#define CONFIG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */
wdenk7a8e9bed2003-05-31 18:35:21 +0000400#else /* AMD AM29LV116D */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200402#define CONFIG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
403#define CONFIG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */
wdenk7a8e9bed2003-05-31 18:35:21 +0000404#endif /* #if */
405
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200406#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Size of the Environment */
407#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
wdenkc6097192002-11-03 00:24:07 +0000408
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
410#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
413#undef CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000414#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000416#endif
417
418
419/*-----------------------------------------------------------------------
420 * Cache Configuration
421 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500423#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000425#endif
426
wdenkc6097192002-11-03 00:24:07 +0000427#endif /* __CONFIG_H */