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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07002/**
3 * (C) Copyright 2014, Cavium Inc.
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07004**/
5
6#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07007#include <cpu_func.h>
Simon Glass9d922452017-05-17 17:18:03 -06008#include <dm.h>
Simon Glass2cf431c2019-11-14 12:57:47 -07009#include <init.h>
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070010#include <malloc.h>
11#include <errno.h>
12#include <linux/compiler.h>
13
Sergey Temerkhanov3ed2ece2015-10-14 09:55:52 -070014#include <cavium/atf.h>
Alexander Grafd473f0c2016-03-04 01:09:48 +010015#include <asm/armv8/mmu.h>
Sergey Temerkhanov3ed2ece2015-10-14 09:55:52 -070016
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070017#if !CONFIG_IS_ENABLED(OF_CONTROL)
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070018#include <dm/platform_data/serial_pl01x.h>
19
20static const struct pl01x_serial_platdata serial0 = {
21 .base = CONFIG_SYS_SERIAL0,
22 .type = TYPE_PL011,
23 .clock = 0,
24 .skip_init = true,
25};
26
27U_BOOT_DEVICE(thunderx_serial0) = {
28 .name = "serial_pl01x",
29 .platdata = &serial0,
30};
31
32static const struct pl01x_serial_platdata serial1 = {
33 .base = CONFIG_SYS_SERIAL1,
34 .type = TYPE_PL011,
35 .clock = 0,
36 .skip_init = true,
37};
38
39U_BOOT_DEVICE(thunderx_serial1) = {
40 .name = "serial_pl01x",
41 .platdata = &serial1,
42};
43#endif
44
45DECLARE_GLOBAL_DATA_PTR;
46
Alexander Grafd473f0c2016-03-04 01:09:48 +010047static struct mm_region thunderx_mem_map[] = {
48 {
York Suncd4b0c52016-06-24 16:46:22 -070049 .virt = 0x000000000000UL,
50 .phys = 0x000000000000UL,
Alexander Grafd473f0c2016-03-04 01:09:48 +010051 .size = 0x40000000000UL,
52 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
53 }, {
York Suncd4b0c52016-06-24 16:46:22 -070054 .virt = 0x800000000000UL,
55 .phys = 0x800000000000UL,
Alexander Grafd473f0c2016-03-04 01:09:48 +010056 .size = 0x40000000000UL,
57 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
58 PTE_BLOCK_NON_SHARE,
59 }, {
York Suncd4b0c52016-06-24 16:46:22 -070060 .virt = 0x840000000000UL,
61 .phys = 0x840000000000UL,
Alexander Grafd473f0c2016-03-04 01:09:48 +010062 .size = 0x40000000000UL,
63 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
64 PTE_BLOCK_NON_SHARE,
65 }, {
66 /* List terminator */
67 0,
68 }
69};
70
71struct mm_region *mem_map = thunderx_mem_map;
72
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070073int board_init(void)
74{
75 return 0;
76}
77
78int timer_init(void)
79{
80 return 0;
81}
82
Sergey Temerkhanov3ed2ece2015-10-14 09:55:52 -070083int dram_init(void)
84{
85 ssize_t node_count = atf_node_count();
86 ssize_t dram_size;
87 int node;
88
89 printf("Initializing\nNodes in system: %zd\n", node_count);
90
91 gd->ram_size = 0;
92
93 for (node = 0; node < node_count; node++) {
94 dram_size = atf_dram_size(node);
95 printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
96 gd->ram_size += dram_size;
97 }
98
99 gd->ram_size -= MEM_BASE;
100
101 *(unsigned long *)CPU_RELEASE_ADDR = 0;
102
103 puts("DRAM size:");
104
105 return 0;
106}
107
Sergey Temerkhanov746f9852015-10-14 09:55:50 -0700108/*
109 * Board specific reset that is system reset.
110 */
111void reset_cpu(ulong addr)
112{
113}
114
115/*
116 * Board specific ethernet initialization routine.
117 */
118int board_eth_init(bd_t *bis)
119{
120 int rc = 0;
121
122 return rc;
123}
124
125#ifdef CONFIG_PCI
126void pci_init_board(void)
127{
128 printf("DEBUG: PCI Init TODO *****\n");
129}
130#endif