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Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +00001/*
Enric Balletbo i Serra3a2f0402013-07-25 09:27:38 +02002 * Board functions for IGEP COM AQUILA based boards
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +00003 *
4 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +00007 */
8
9#include <common.h>
10#include <errno.h>
11#include <spl.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/hardware.h>
14#include <asm/arch/omap.h>
15#include <asm/arch/ddr_defs.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/gpio.h>
18#include <asm/arch/mmc_host_def.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/io.h>
21#include <asm/emif.h>
22#include <asm/gpio.h>
23#include <i2c.h>
24#include <miiphy.h>
25#include <cpsw.h>
26#include "board.h"
27
28DECLARE_GLOBAL_DATA_PTR;
29
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000030static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
31
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000032#ifdef CONFIG_SPL_BUILD
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000033static const struct ddr_data ddr3_data = {
34 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
35 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
36 .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
37 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000038};
39
40static const struct cmd_control ddr3_cmd_ctrl_data = {
41 .cmd0csratio = K4B2G1646EBIH9_RATIO,
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000042 .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
43
44 .cmd1csratio = K4B2G1646EBIH9_RATIO,
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000045 .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
46
47 .cmd2csratio = K4B2G1646EBIH9_RATIO,
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000048 .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
49};
50
51static struct emif_regs ddr3_emif_reg_data = {
52 .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
53 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
54 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
55 .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
56 .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
57 .zq_config = K4B2G1646EBIH9_ZQ_CFG,
58 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
59};
Lokesh Vutla94d77fb2013-07-30 10:48:52 +053060
61#define OSC (V_OSCK/1000000)
62const struct dpll_params dpll_ddr = {
Enric Balletbo i Serra94b32f62013-09-10 11:12:26 +020063 400, OSC-1, 1, -1, -1, -1, -1};
Lokesh Vutla94d77fb2013-07-30 10:48:52 +053064
65const struct dpll_params *get_dpll_ddr_params(void)
66{
67 return &dpll_ddr;
68}
69
Heiko Schocher06604812013-07-30 10:48:54 +053070void set_uart_mux_conf(void)
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000071{
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000072 enable_uart0_pin_mux();
Heiko Schocher06604812013-07-30 10:48:54 +053073}
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000074
Heiko Schocher06604812013-07-30 10:48:54 +053075void set_mux_conf_regs(void)
76{
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000077 enable_board_pin_mux();
Heiko Schocher06604812013-07-30 10:48:54 +053078}
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000079
Lokesh Vutla965de8b2013-12-10 15:02:21 +053080const struct ctrl_ioregs ioregs = {
81 .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
82 .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
83 .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
84 .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
85 .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
86};
87
Heiko Schocher06604812013-07-30 10:48:54 +053088void sdram_init(void)
89{
Lokesh Vutla965de8b2013-12-10 15:02:21 +053090 config_ddr(400, &ioregs, &ddr3_data,
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000091 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000092}
Heiko Schocher06604812013-07-30 10:48:54 +053093#endif
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000094
95/*
96 * Basic board specific setup. Pinmux has been handled already.
97 */
98int board_init(void)
99{
Tom Rini73feefd2013-08-09 11:22:13 -0400100 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000101
102 gpmc_init();
103
104 return 0;
105}
106
107#if defined(CONFIG_DRIVER_TI_CPSW)
108static void cpsw_control(int enabled)
109{
110 /* VTP can be added here */
111
112 return;
113}
114
115static struct cpsw_slave_data cpsw_slaves[] = {
116 {
117 .slave_reg_ofs = 0x208,
118 .sliver_reg_ofs = 0xd80,
Mugunthan V N9c653aa2014-02-18 07:31:52 -0500119 .phy_addr = 0,
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000120 .phy_if = PHY_INTERFACE_MODE_RMII,
121 },
122};
123
124static struct cpsw_platform_data cpsw_data = {
125 .mdio_base = CPSW_MDIO_BASE,
126 .cpsw_base = CPSW_BASE,
127 .mdio_div = 0xff,
128 .channels = 8,
129 .cpdma_reg_ofs = 0x800,
130 .slaves = 1,
131 .slave_data = cpsw_slaves,
132 .ale_reg_ofs = 0xd00,
133 .ale_entries = 1024,
134 .host_port_reg_ofs = 0x108,
135 .hw_stats_reg_ofs = 0x900,
Lars Poeschel6478cde2013-09-30 09:51:34 +0200136 .bd_ram_ofs = 0x2000,
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000137 .mac_control = (1 << 5),
138 .control = cpsw_control,
139 .host_port_num = 0,
140 .version = CPSW_CTRL_VERSION_2,
141};
142
143int board_eth_init(bd_t *bis)
144{
145 int rv, ret = 0;
146 uint8_t mac_addr[6];
147 uint32_t mac_hi, mac_lo;
148
149 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
150 /* try reading mac address from efuse */
151 mac_lo = readl(&cdev->macid0l);
152 mac_hi = readl(&cdev->macid0h);
153 mac_addr[0] = mac_hi & 0xFF;
154 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
155 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
156 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
157 mac_addr[4] = mac_lo & 0xFF;
158 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
159 if (is_valid_ether_addr(mac_addr))
160 eth_setenv_enetaddr("ethaddr", mac_addr);
161 }
162
Heiko Schocherdafd4db2013-08-19 16:38:56 +0200163 writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
164 &cdev->miisel);
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000165
166 rv = cpsw_register(&cpsw_data);
167 if (rv < 0)
168 printf("Error %d registering CPSW switch\n", rv);
169 else
170 ret += rv;
171
172 return ret;
173}
174#endif