blob: b80688ae864ce5842774d9080b0e00898d2ff212 [file] [log] [blame]
liu haoe3aafef2019-10-31 07:51:08 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019
4 * shuyiqi <shuyiqi@phytium.com.cn>
5 * liuhao <liuhao@phytium.com.cn>
6 */
7
8#include <common.h>
Simon Glass09140112020-05-10 11:40:03 -06009#include <command.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -070010#include <cpu_func.h>
Simon Glass691d7192020-05-10 11:40:02 -060011#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
liu haoe3aafef2019-10-31 07:51:08 +000013#include <asm/armv8/mmu.h>
Simon Glass90526e92020-05-10 11:39:56 -060014#include <asm/cache.h>
liu haoe3aafef2019-10-31 07:51:08 +000015#include <asm/system.h>
16#include <asm/io.h>
17#include <linux/arm-smccc.h>
18#include <linux/kernel.h>
19#include <scsi.h>
20#include "cpu.h"
21
22DECLARE_GLOBAL_DATA_PTR;
23
24int dram_init(void)
25{
26 gd->mem_clk = 0;
27 gd->ram_size = PHYS_SDRAM_1_SIZE;
28 return 0;
29}
30
31int dram_init_banksize(void)
32{
33 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
34 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
35
36 return 0;
37}
38
39int board_init(void)
40{
41 return 0;
42}
43
44void reset_cpu(ulong addr)
45{
46 struct arm_smccc_res res;
47
48 arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
49 debug("reset cpu error, %lx\n", res.a0);
50}
51
52static struct mm_region durian_mem_map[] = {
53 {
54 .virt = 0x0UL,
55 .phys = 0x0UL,
56 .size = 0x80000000UL,
57 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
58 PTE_BLOCK_NON_SHARE |
59 PTE_BLOCK_PXN |
60 PTE_BLOCK_UXN
61 },
62 {
63 .virt = (u64)PHYS_SDRAM_1,
64 .phys = (u64)PHYS_SDRAM_1,
65 .size = (u64)PHYS_SDRAM_1_SIZE,
66 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
67 PTE_BLOCK_NS |
68 PTE_BLOCK_INNER_SHARE
69 },
70 {
71 0,
72 }
73};
74
75struct mm_region *mem_map = durian_mem_map;
76
77int print_cpuinfo(void)
78{
79 printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
80 return 0;
81}
82
83int __asm_flush_l3_dcache(void)
84{
85 int i, pstate;
86
87 for (i = 0; i < HNF_COUNT; i++)
88 writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
89 for (i = 0; i < HNF_COUNT; i++) {
90 do {
91 pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
92 } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
93 }
94
95 for (i = 0; i < HNF_COUNT; i++)
96 writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
97
98 return 0;
99}
100
101int last_stage_init(void)
102{
103 int ret;
104
105 /* pci e */
106 pci_init();
107 /* scsi scan */
108 ret = scsi_scan(true);
109 if (ret) {
110 printf("scsi scan failed\n");
111 return CMD_RET_FAILURE;
112 }
113 return ret;
114}
115