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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08002/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05003 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08004 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
6 *
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08007 * with the reference on libata and ahci drvier in kernel
Simon Glass7cf1afc2017-06-14 21:28:37 -06008 *
9 * This driver provides a SCSI interface to SATA.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080010 */
11#include <common.h>
Simon Glasse6f6f9e2020-05-10 11:39:58 -060012#include <blk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070013#include <cpu_func.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <log.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060016#include <linux/delay.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080017
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080018#include <command.h>
Simon Glassff758cc2015-11-29 13:18:06 -070019#include <dm.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080020#include <pci.h>
21#include <asm/processor.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090022#include <linux/errno.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080023#include <asm/io.h>
24#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060025#include <memalign.h>
Simon Glass681357f2017-06-14 21:28:46 -060026#include <pci.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080027#include <scsi.h>
Rob Herring344ca0b2013-08-24 10:10:54 -050028#include <libata.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080029#include <linux/ctype.h>
30#include <ahci.h>
Simon Glass681357f2017-06-14 21:28:46 -060031#include <dm/device-internal.h>
32#include <dm/lists.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080033
Simon Glass225b1da2017-06-14 21:28:34 -060034static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
Marc Jones766b16f2012-10-29 05:24:02 +000035
Simon Glass4682c8a2017-06-14 21:28:40 -060036#ifndef CONFIG_DM_SCSI
Simon Glass2c9f9ef2017-06-14 21:28:32 -060037struct ahci_uc_priv *probe_ent = NULL;
Simon Glass4682c8a2017-06-14 21:28:40 -060038#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080039
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050040#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
41
Vadim Bendebury284231e2012-10-29 05:23:44 +000042/*
Hung-Te Linb7a21b72012-10-29 05:23:53 +000043 * Some controllers limit number of blocks they can read/write at once.
44 * Contemporary SSD devices work much faster if the read/write size is aligned
45 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
46 * needed.
Vadim Bendebury284231e2012-10-29 05:23:44 +000047 */
Hung-Te Linb7a21b72012-10-29 05:23:53 +000048#ifndef MAX_SATA_BLOCKS_READ_WRITE
49#define MAX_SATA_BLOCKS_READ_WRITE 0x80
Vadim Bendebury284231e2012-10-29 05:23:44 +000050#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080051
Walter Murphy57847662012-10-29 05:24:00 +000052/* Maximum timeouts for each event */
Rob Herring7610b412013-08-24 10:10:53 -050053#define WAIT_MS_SPINUP 20000
Mark Langsdorff8b009e2015-06-05 00:58:46 +010054#define WAIT_MS_DATAIO 10000
Marc Jones766b16f2012-10-29 05:24:02 +000055#define WAIT_MS_FLUSH 5000
Ian Campbelle0ddcf92014-07-18 20:38:39 +010056#define WAIT_MS_LINKUP 200
Walter Murphy57847662012-10-29 05:24:00 +000057
Roman Kapl6e732552019-10-14 11:21:09 +020058#define AHCI_CAP_S64A BIT(31)
59
Stefan Roese22f5de62016-08-31 10:02:15 +020060__weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080061{
62 return base + 0x100 + (port * 0x80);
63}
64
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080065#define msleep(a) udelay(a * 1000)
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050066
Tang Yuantianfa313772015-07-09 14:37:30 +080067static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
Taylor Hutt90b276f2012-10-29 05:23:59 +000068{
69 const unsigned long start = begin;
70 const unsigned long end = start + len;
71
72 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
73 flush_dcache_range(start, end);
74}
75
76/*
77 * SATA controller DMAs to physical RAM. Ensure data from the
78 * controller is invalidated from dcache; next access comes from
79 * physical RAM.
80 */
Tang Yuantianfa313772015-07-09 14:37:30 +080081static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
Taylor Hutt90b276f2012-10-29 05:23:59 +000082{
83 const unsigned long start = begin;
84 const unsigned long end = start + len;
85
86 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
87 invalidate_dcache_range(start, end);
88}
89
90/*
91 * Ensure data for SATA controller is flushed out of dcache and
92 * written to physical memory.
93 */
94static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
95{
96 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
97 AHCI_PORT_PRIV_DMA_SZ);
98}
99
Tang Yuantianfa313772015-07-09 14:37:30 +0800100static int waiting_for_cmd_completed(void __iomem *offset,
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500101 int timeout_msec,
102 u32 sign)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800103{
104 int i;
105 u32 status;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500106
107 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800108 msleep(1);
109
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500110 return (i < timeout_msec) ? 0 : -1;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800111}
112
Marek Behún2361b5e2021-05-20 13:24:21 +0200113int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, int port)
Rob Herring124e9fa2013-08-24 10:10:51 -0500114{
115 u32 tmp;
116 int j = 0;
Simon Glass4b62b2f2017-06-14 21:28:33 -0600117 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
Rob Herring124e9fa2013-08-24 10:10:51 -0500118
Wolfgang Denk3765b3e2013-10-07 13:07:26 +0200119 /*
Rob Herring124e9fa2013-08-24 10:10:51 -0500120 * Bring up SATA link.
121 * SATA link bringup time is usually less than 1 ms; only very
122 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
123 */
124 while (j < WAIT_MS_LINKUP) {
125 tmp = readl(port_mmio + PORT_SCR_STAT);
126 tmp &= PORT_SCR_STAT_DET_MASK;
127 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
128 return 0;
129 udelay(1000);
130 j++;
131 }
132 return 1;
133}
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800134
Ian Campbella6e50a82014-07-18 20:38:41 +0100135#ifdef CONFIG_SUNXI_AHCI
136/* The sunxi AHCI controller requires this undocumented setup */
Tang Yuantianfa313772015-07-09 14:37:30 +0800137static void sunxi_dma_init(void __iomem *port_mmio)
Ian Campbella6e50a82014-07-18 20:38:41 +0100138{
139 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
140}
141#endif
142
Scott Wood9efaca32015-04-17 09:19:01 -0500143int ahci_reset(void __iomem *base)
Dmitry Lifshitz6b688882014-12-15 16:02:55 +0200144{
145 int i = 1000;
Scott Wood9efaca32015-04-17 09:19:01 -0500146 u32 __iomem *host_ctl_reg = base + HOST_CTL;
Dmitry Lifshitz6b688882014-12-15 16:02:55 +0200147 u32 tmp = readl(host_ctl_reg); /* global controller reset */
148
149 if ((tmp & HOST_RESET) == 0)
150 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
151
152 /*
153 * reset must complete within 1 second, or
154 * the hardware should be considered fried.
155 */
156 do {
157 udelay(1000);
158 tmp = readl(host_ctl_reg);
159 i--;
160 } while ((i > 0) && (tmp & HOST_RESET));
161
162 if (i == 0) {
163 printf("controller reset failed (0x%x)\n", tmp);
164 return -1;
165 }
166
167 return 0;
168}
169
Simon Glass225b1da2017-06-14 21:28:34 -0600170static int ahci_host_init(struct ahci_uc_priv *uc_priv)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800171{
Michal Simeke8a016b2016-09-08 15:06:45 +0200172#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
Simon Glass225b1da2017-06-14 21:28:34 -0600173 struct udevice *dev = uc_priv->dev;
Simon Glass8a8d24b2020-12-03 16:55:23 -0700174 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
Simon Glassff758cc2015-11-29 13:18:06 -0700175 u16 tmp16;
Rob Herring942e3142011-07-06 16:13:36 +0000176#endif
Simon Glass225b1da2017-06-14 21:28:34 -0600177 void __iomem *mmio = uc_priv->mmio_base;
Marc Jones2a0c61d2012-10-29 05:24:01 +0000178 u32 tmp, cap_save, cmd;
Rob Herring124e9fa2013-08-24 10:10:51 -0500179 int i, j, ret;
Tang Yuantianfa313772015-07-09 14:37:30 +0800180 void __iomem *port_mmio;
Richard Gibbs2915a022013-08-24 10:10:47 -0500181 u32 port_map;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800182
Vadim Bendebury284231e2012-10-29 05:23:44 +0000183 debug("ahci_host_init: start\n");
184
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800185 cap_save = readl(mmio + HOST_CAP);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500186 cap_save &= ((1 << 28) | (1 << 17));
Marc Jones2a0c61d2012-10-29 05:24:01 +0000187 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800188
Simon Glass225b1da2017-06-14 21:28:34 -0600189 ret = ahci_reset(uc_priv->mmio_base);
Dmitry Lifshitz6b688882014-12-15 16:02:55 +0200190 if (ret)
191 return ret;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800192
193 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
194 writel(cap_save, mmio + HOST_CAP);
195 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
196
Michal Simeke8a016b2016-09-08 15:06:45 +0200197#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
Simon Glassff758cc2015-11-29 13:18:06 -0700198 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
199 u16 tmp16;
200
201 dm_pci_read_config16(dev, 0x92, &tmp16);
202 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
203 }
Rob Herring942e3142011-07-06 16:13:36 +0000204#endif
Simon Glass225b1da2017-06-14 21:28:34 -0600205 uc_priv->cap = readl(mmio + HOST_CAP);
206 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
207 port_map = uc_priv->port_map;
208 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800209
210 debug("cap 0x%x port_map 0x%x n_ports %d\n",
Simon Glass225b1da2017-06-14 21:28:34 -0600211 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800212
Tuomas Tynkkynen0545ac92018-09-13 01:28:55 +0300213#if !defined(CONFIG_DM_SCSI)
Heinrich Schuchardt120ec1d2023-03-26 18:58:26 +0200214 if (uc_priv->n_ports > CONFIG_SYS_SATA_MAX_PORTS)
215 uc_priv->n_ports = CONFIG_SYS_SATA_MAX_PORTS;
Tuomas Tynkkynen0545ac92018-09-13 01:28:55 +0300216#endif
Vadim Bendebury284231e2012-10-29 05:23:44 +0000217
Simon Glass225b1da2017-06-14 21:28:34 -0600218 for (i = 0; i < uc_priv->n_ports; i++) {
Richard Gibbs2915a022013-08-24 10:10:47 -0500219 if (!(port_map & (1 << i)))
220 continue;
Simon Glass225b1da2017-06-14 21:28:34 -0600221 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
222 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800223
224 /* make sure port is not active */
225 tmp = readl(port_mmio + PORT_CMD);
226 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
227 PORT_CMD_FIS_RX | PORT_CMD_START)) {
Stefan Reinauer7ba79172012-10-29 05:23:50 +0000228 debug("Port %d is active. Deactivating.\n", i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800229 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
230 PORT_CMD_FIS_RX | PORT_CMD_START);
231 writel_with_flush(tmp, port_mmio + PORT_CMD);
232
233 /* spec says 500 msecs for each bit, so
234 * this is slightly incorrect.
235 */
236 msleep(500);
237 }
238
Ian Campbella6e50a82014-07-18 20:38:41 +0100239#ifdef CONFIG_SUNXI_AHCI
240 sunxi_dma_init(port_mmio);
241#endif
242
Marc Jones2a0c61d2012-10-29 05:24:01 +0000243 /* Add the spinup command to whatever mode bits may
244 * already be on in the command register.
245 */
246 cmd = readl(port_mmio + PORT_CMD);
Marc Jones2a0c61d2012-10-29 05:24:01 +0000247 cmd |= PORT_CMD_SPIN_UP;
248 writel_with_flush(cmd, port_mmio + PORT_CMD);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800249
Rob Herring124e9fa2013-08-24 10:10:51 -0500250 /* Bring up SATA link. */
Simon Glass225b1da2017-06-14 21:28:34 -0600251 ret = ahci_link_up(uc_priv, i);
Rob Herring124e9fa2013-08-24 10:10:51 -0500252 if (ret) {
Marc Jones2a0c61d2012-10-29 05:24:01 +0000253 printf("SATA link %d timeout.\n", i);
254 continue;
255 } else {
256 debug("SATA link ok.\n");
257 }
258
259 /* Clear error status */
260 tmp = readl(port_mmio + PORT_SCR_ERR);
261 if (tmp)
262 writel(tmp, port_mmio + PORT_SCR_ERR);
263
264 debug("Spinning up device on SATA port %d... ", i);
265
266 j = 0;
267 while (j < WAIT_MS_SPINUP) {
268 tmp = readl(port_mmio + PORT_TFDATA);
Rob Herring344ca0b2013-08-24 10:10:54 -0500269 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
Marc Jones2a0c61d2012-10-29 05:24:01 +0000270 break;
271 udelay(1000);
Rob Herring17821082013-08-24 10:10:52 -0500272 tmp = readl(port_mmio + PORT_SCR_STAT);
273 tmp &= PORT_SCR_STAT_DET_MASK;
274 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
275 break;
Marc Jones2a0c61d2012-10-29 05:24:01 +0000276 j++;
277 }
Rob Herring17821082013-08-24 10:10:52 -0500278
279 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
280 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
281 debug("SATA link %d down (COMINIT received), retrying...\n", i);
282 i--;
283 continue;
284 }
285
Marc Jones2a0c61d2012-10-29 05:24:01 +0000286 printf("Target spinup took %d ms.\n", j);
287 if (j == WAIT_MS_SPINUP)
Stefan Reinauer9a65b872012-10-29 05:23:49 +0000288 debug("timeout.\n");
289 else
290 debug("ok.\n");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800291
292 tmp = readl(port_mmio + PORT_SCR_ERR);
293 debug("PORT_SCR_ERR 0x%x\n", tmp);
294 writel(tmp, port_mmio + PORT_SCR_ERR);
295
296 /* ack any pending irq events for this port */
297 tmp = readl(port_mmio + PORT_IRQ_STAT);
298 debug("PORT_IRQ_STAT 0x%x\n", tmp);
299 if (tmp)
300 writel(tmp, port_mmio + PORT_IRQ_STAT);
301
302 writel(1 << i, mmio + HOST_IRQ_STAT);
303
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000304 /* register linkup ports */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800305 tmp = readl(port_mmio + PORT_SCR_STAT);
Marc Jones766b16f2012-10-29 05:24:02 +0000306 debug("SATA port %d status: 0x%x\n", i, tmp);
Rob Herring2bdb10d2013-08-24 10:10:50 -0500307 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
Simon Glass225b1da2017-06-14 21:28:34 -0600308 uc_priv->link_port_map |= (0x01 << i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800309 }
310
311 tmp = readl(mmio + HOST_CTL);
312 debug("HOST_CTL 0x%x\n", tmp);
313 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
314 tmp = readl(mmio + HOST_CTL);
315 debug("HOST_CTL 0x%x\n", tmp);
Michal Simeke8a016b2016-09-08 15:06:45 +0200316#if !defined(CONFIG_DM_SCSI)
Rob Herring942e3142011-07-06 16:13:36 +0000317#ifndef CONFIG_SCSI_AHCI_PLAT
Simon Glassff758cc2015-11-29 13:18:06 -0700318 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
319 tmp |= PCI_COMMAND_MASTER;
320 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
Rob Herring942e3142011-07-06 16:13:36 +0000321#endif
Michal Simeke8a016b2016-09-08 15:06:45 +0200322#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800323 return 0;
324}
325
326
Simon Glass225b1da2017-06-14 21:28:34 -0600327static void ahci_print_info(struct ahci_uc_priv *uc_priv)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800328{
Michal Simeke8a016b2016-09-08 15:06:45 +0200329#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
Simon Glass225b1da2017-06-14 21:28:34 -0600330 struct udevice *dev = uc_priv->dev;
Rob Herring942e3142011-07-06 16:13:36 +0000331 u16 cc;
332#endif
Simon Glass225b1da2017-06-14 21:28:34 -0600333 void __iomem *mmio = uc_priv->mmio_base;
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000334 u32 vers, cap, cap2, impl, speed;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800335 const char *speed_s;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800336 const char *scc_s;
337
338 vers = readl(mmio + HOST_VERSION);
Simon Glass225b1da2017-06-14 21:28:34 -0600339 cap = uc_priv->cap;
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000340 cap2 = readl(mmio + HOST_CAP2);
Simon Glass225b1da2017-06-14 21:28:34 -0600341 impl = uc_priv->port_map;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800342
343 speed = (cap >> 20) & 0xf;
344 if (speed == 1)
345 speed_s = "1.5";
346 else if (speed == 2)
347 speed_s = "3";
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000348 else if (speed == 3)
349 speed_s = "6";
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800350 else
351 speed_s = "?";
352
Michal Simeke8a016b2016-09-08 15:06:45 +0200353#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
Rob Herring942e3142011-07-06 16:13:36 +0000354 scc_s = "SATA";
355#else
Simon Glassff758cc2015-11-29 13:18:06 -0700356 dm_pci_read_config16(dev, 0x0a, &cc);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800357 if (cc == 0x0101)
358 scc_s = "IDE";
359 else if (cc == 0x0106)
360 scc_s = "SATA";
361 else if (cc == 0x0104)
362 scc_s = "RAID";
363 else
364 scc_s = "unknown";
Rob Herring942e3142011-07-06 16:13:36 +0000365#endif
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500366 printf("AHCI %02x%02x.%02x%02x "
367 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
368 (vers >> 24) & 0xff,
369 (vers >> 16) & 0xff,
370 (vers >> 8) & 0xff,
371 vers & 0xff,
372 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800373
374 printf("flags: "
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000375 "%s%s%s%s%s%s%s"
376 "%s%s%s%s%s%s%s"
377 "%s%s%s%s%s%s\n",
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500378 cap & (1 << 31) ? "64bit " : "",
379 cap & (1 << 30) ? "ncq " : "",
380 cap & (1 << 28) ? "ilck " : "",
381 cap & (1 << 27) ? "stag " : "",
382 cap & (1 << 26) ? "pm " : "",
383 cap & (1 << 25) ? "led " : "",
384 cap & (1 << 24) ? "clo " : "",
385 cap & (1 << 19) ? "nz " : "",
386 cap & (1 << 18) ? "only " : "",
387 cap & (1 << 17) ? "pmp " : "",
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000388 cap & (1 << 16) ? "fbss " : "",
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500389 cap & (1 << 15) ? "pio " : "",
390 cap & (1 << 14) ? "slum " : "",
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000391 cap & (1 << 13) ? "part " : "",
392 cap & (1 << 7) ? "ccc " : "",
393 cap & (1 << 6) ? "ems " : "",
394 cap & (1 << 5) ? "sxs " : "",
395 cap2 & (1 << 2) ? "apst " : "",
396 cap2 & (1 << 1) ? "nvmp " : "",
397 cap2 & (1 << 0) ? "boh " : "");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800398}
399
Simon Glass745a94f2017-07-04 13:31:18 -0600400#if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
Simon Glass4279efc2017-06-14 21:28:38 -0600401static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800402{
Michal Simeke8a016b2016-09-08 15:06:45 +0200403#if !defined(CONFIG_DM_SCSI)
Ed Swarthout63cec582007-08-02 14:09:49 -0500404 u16 vendor;
Michal Simeke8a016b2016-09-08 15:06:45 +0200405#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800406 int rc;
407
Simon Glass225b1da2017-06-14 21:28:34 -0600408 uc_priv->dev = dev;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800409
Simon Glass225b1da2017-06-14 21:28:34 -0600410 uc_priv->host_flags = ATA_FLAG_SATA
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500411 | ATA_FLAG_NO_LEGACY
412 | ATA_FLAG_MMIO
413 | ATA_FLAG_PIO_DMA
414 | ATA_FLAG_NO_ATAPI;
Simon Glass225b1da2017-06-14 21:28:34 -0600415 uc_priv->pio_mask = 0x1f;
416 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800417
Michal Simeke8a016b2016-09-08 15:06:45 +0200418#if !defined(CONFIG_DM_SCSI)
Andrew Scull12507a22022-04-21 16:11:10 +0000419 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 0, 0,
Andrew Scull2635e3b2022-04-21 16:11:13 +0000420 PCI_REGION_TYPE, PCI_REGION_MEM);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800421
422 /* Take from kernel:
423 * JMicron-specific fixup:
424 * make sure we're in AHCI mode
425 */
Simon Glassff758cc2015-11-29 13:18:06 -0700426 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500427 if (vendor == 0x197b)
Simon Glassff758cc2015-11-29 13:18:06 -0700428 dm_pci_write_config8(dev, 0x41, 0xa1);
429#else
Simon Glass8a8d24b2020-12-03 16:55:23 -0700430 struct scsi_plat *plat = dev_get_uclass_plat(dev);
Simon Glass225b1da2017-06-14 21:28:34 -0600431 uc_priv->mmio_base = (void *)plat->base;
Michal Simeke8a016b2016-09-08 15:06:45 +0200432#endif
Simon Glassff758cc2015-11-29 13:18:06 -0700433
Simon Glass225b1da2017-06-14 21:28:34 -0600434 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800435 /* initialize adapter */
Simon Glass225b1da2017-06-14 21:28:34 -0600436 rc = ahci_host_init(uc_priv);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800437 if (rc)
438 goto err_out;
439
Simon Glass225b1da2017-06-14 21:28:34 -0600440 ahci_print_info(uc_priv);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800441
442 return 0;
443
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500444 err_out:
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800445 return rc;
446}
Rob Herring942e3142011-07-06 16:13:36 +0000447#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800448
449#define MAX_DATA_BYTE_COUNT (4*1024*1024)
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500450
Simon Glass225b1da2017-06-14 21:28:34 -0600451static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
452 unsigned char *buf, int buf_len)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800453{
Simon Glass225b1da2017-06-14 21:28:34 -0600454 struct ahci_ioports *pp = &(uc_priv->port[port]);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800455 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
Stefan Roese1cf27002021-04-07 09:12:35 +0200456 phys_addr_t pa = virt_to_phys(buf);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800457 u32 sg_count;
458 int i;
459
460 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500461 if (sg_count > AHCI_MAX_SG) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800462 printf("Error:Too much sg!\n");
463 return -1;
464 }
465
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500466 for (i = 0; i < sg_count; i++) {
Roman Kapl6e732552019-10-14 11:21:09 +0200467 ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
468 ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
469 if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
470 printf("Error: DMA address too high\n");
471 return -1;
472 }
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500473 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
Stefan Roese1cf27002021-04-07 09:12:35 +0200474 (buf_len < MAX_DATA_BYTE_COUNT ?
475 (buf_len - 1) :
476 (MAX_DATA_BYTE_COUNT - 1)));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800477 ahci_sg++;
478 buf_len -= MAX_DATA_BYTE_COUNT;
Stefan Roese1cf27002021-04-07 09:12:35 +0200479 pa += MAX_DATA_BYTE_COUNT;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800480 }
481
482 return sg_count;
483}
484
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800485static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
486{
Stefan Roese1cf27002021-04-07 09:12:35 +0200487 phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl);
488
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800489 pp->cmd_slot->opts = cpu_to_le32(opts);
490 pp->cmd_slot->status = 0;
Stefan Roese1cf27002021-04-07 09:12:35 +0200491 pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
Tang Yuantianfa313772015-07-09 14:37:30 +0800492#ifdef CONFIG_PHYS_64BIT
Stefan Roese1cf27002021-04-07 09:12:35 +0200493 pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
Tang Yuantianfa313772015-07-09 14:37:30 +0800494#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800495}
496
Tang Yuantianfa313772015-07-09 14:37:30 +0800497static int wait_spinup(void __iomem *port_mmio)
Bin Meng4df2b482014-12-31 17:18:39 +0800498{
499 ulong start;
500 u32 tf_data;
501
502 start = get_timer(0);
503 do {
504 tf_data = readl(port_mmio + PORT_TFDATA);
505 if (!(tf_data & ATA_BUSY))
506 return 0;
507 } while (get_timer(start) < WAIT_MS_SPINUP);
508
509 return -ETIMEDOUT;
510}
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800511
Simon Glass225b1da2017-06-14 21:28:34 -0600512static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800513{
Simon Glass225b1da2017-06-14 21:28:34 -0600514 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantianfa313772015-07-09 14:37:30 +0800515 void __iomem *port_mmio = pp->port_mmio;
Oleksandr Rybalko5b7a2bf2019-08-22 12:26:56 +0200516 u64 dma_addr;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800517 u32 port_status;
Tang Yuantianfa313772015-07-09 14:37:30 +0800518 void __iomem *mem;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800519
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500520 debug("Enter start port: %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800521 port_status = readl(port_mmio + PORT_SCR_STAT);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500522 debug("Port %d status: %x\n", port, port_status);
523 if ((port_status & 0xf) != 0x03) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800524 printf("No Link on this port!\n");
525 return -1;
526 }
527
Christian Gmeiner28b4ba92019-05-06 15:18:54 +0200528 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800529 if (!mem) {
530 free(pp);
Roger Quadrosd73763a2013-11-11 16:56:37 +0200531 printf("%s: No mem for table!\n", __func__);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800532 return -ENOMEM;
533 }
Tang Yuantianfa313772015-07-09 14:37:30 +0800534 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800535
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800536 /*
537 * First item in chunk of DMA memory: 32-slot command table,
538 * 32 bytes each in size
539 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000540 pp->cmd_slot =
541 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
Tang Yuantianfa313772015-07-09 14:37:30 +0800542 debug("cmd_slot = %p\n", pp->cmd_slot);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800543 mem += (AHCI_CMD_SLOT_SZ + 224);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500544
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800545 /*
546 * Second item: Received-FIS area
547 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000548 pp->rx_fis = virt_to_phys((void *)mem);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800549 mem += AHCI_RX_FIS_SZ;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500550
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800551 /*
552 * Third item: data area for storing a single command
553 * and its scatter-gather table
554 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000555 pp->cmd_tbl = virt_to_phys((void *)mem);
Tang Yuantianfa313772015-07-09 14:37:30 +0800556 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800557
558 mem += AHCI_CMD_TBL_HDR;
Taylor Hutt64738e82012-10-29 05:23:58 +0000559 pp->cmd_tbl_sg =
560 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800561
Oleksandr Rybalko5b7a2bf2019-08-22 12:26:56 +0200562 dma_addr = (ulong)pp->cmd_slot;
563 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
564 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
565 dma_addr = (ulong)pp->rx_fis;
566 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
567 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800568
Ian Campbella6e50a82014-07-18 20:38:41 +0100569#ifdef CONFIG_SUNXI_AHCI
570 sunxi_dma_init(port_mmio);
571#endif
572
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800573 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500574 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
575 PORT_CMD_START, port_mmio + PORT_CMD);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800576
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500577 debug("Exit start port %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800578
Bin Meng4df2b482014-12-31 17:18:39 +0800579 /*
580 * Make sure interface is not busy based on error and status
581 * information from task file data register before proceeding
582 */
583 return wait_spinup(port_mmio);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800584}
585
586
Simon Glass225b1da2017-06-14 21:28:34 -0600587static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
588 int fis_len, u8 *buf, int buf_len, u8 is_write)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800589{
590
Simon Glass225b1da2017-06-14 21:28:34 -0600591 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantianfa313772015-07-09 14:37:30 +0800592 void __iomem *port_mmio = pp->port_mmio;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800593 u32 opts;
594 u32 port_status;
595 int sg_count;
596
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000597 debug("Enter %s: for port %d\n", __func__, port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800598
Simon Glass225b1da2017-06-14 21:28:34 -0600599 if (port > uc_priv->n_ports) {
Taylor Hutt5a2b77f2012-10-29 05:23:56 +0000600 printf("Invalid port number %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800601 return -1;
602 }
603
604 port_status = readl(port_mmio + PORT_SCR_STAT);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500605 if ((port_status & 0xf) != 0x03) {
606 debug("No Link on port %d!\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800607 return -1;
608 }
609
610 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
611
Simon Glass225b1da2017-06-14 21:28:34 -0600612 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000613 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800614 ahci_fill_cmd_slot(pp, opts);
615
Taylor Hutt90b276f2012-10-29 05:23:59 +0000616 ahci_dcache_flush_sata_cmd(pp);
Tang Yuantianfa313772015-07-09 14:37:30 +0800617 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
Taylor Hutt90b276f2012-10-29 05:23:59 +0000618
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800619 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
620
Walter Murphy57847662012-10-29 05:24:00 +0000621 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
622 WAIT_MS_DATAIO, 0x1)) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800623 printf("timeout exit!\n");
624 return -1;
625 }
Taylor Hutt90b276f2012-10-29 05:23:59 +0000626
Tang Yuantianfa313772015-07-09 14:37:30 +0800627 ahci_dcache_invalidate_range((unsigned long)buf,
628 (unsigned long)buf_len);
Stefan Roese1cf27002021-04-07 09:12:35 +0200629 debug("%s: %d byte transferred.\n", __func__,
630 le32_to_cpu(pp->cmd_slot->status));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800631
632 return 0;
633}
634
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800635static char *ata_id_strcpy(u16 *target, u16 *src, int len)
636{
637 int i;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500638 for (i = 0; i < len / 2; i++)
Rob Herringe5a6c792011-06-01 09:10:26 +0000639 target[i] = swab16(src[i]);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800640 return (char *)target;
641}
642
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800643/*
644 * SCSI INQUIRY command operation.
645 */
Simon Glass4b62b2f2017-06-14 21:28:33 -0600646static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
647 struct scsi_cmd *pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800648{
Rob Herring48c3a872013-08-24 10:10:48 -0500649 static const u8 hdr[] = {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800650 0,
651 0,
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500652 0x5, /* claim SPC-3 version compatibility */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800653 2,
654 95 - 4,
655 };
656 u8 fis[20];
Roger Quadros3f629712014-04-01 17:26:40 +0300657 u16 *idbuf;
Roger Quadros2faf5fb2013-11-11 16:56:38 +0200658 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800659 u8 port;
660
661 /* Clean ccb data buffer */
662 memset(pccb->pdata, 0, pccb->datalen);
663
664 memcpy(pccb->pdata, hdr, sizeof(hdr));
665
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500666 if (pccb->datalen <= 35)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800667 return 0;
668
Taylor Huttc8731112012-10-29 05:23:55 +0000669 memset(fis, 0, sizeof(fis));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800670 /* Construct the FIS */
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500671 fis[0] = 0x27; /* Host to device FIS. */
672 fis[1] = 1 << 7; /* Command FIS. */
Rob Herring344ca0b2013-08-24 10:10:54 -0500673 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800674
675 /* Read id from sata */
676 port = pccb->target;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800677
Simon Glass2b3ebf22023-01-17 10:47:53 -0700678 /* If this port number is not valid, give up */
679 if (!(uc_priv->port_map & (1 << port))) {
680 debug("Port %x not valid in map %x\n", port, uc_priv->port_map);
681 return -ENODEV;
682 }
683
Simon Glass225b1da2017-06-14 21:28:34 -0600684 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
685 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800686 debug("scsi_ahci: SCSI inquiry command failure.\n");
687 return -EIO;
688 }
689
Simon Glass4b62b2f2017-06-14 21:28:33 -0600690 if (!uc_priv->ataid[port]) {
691 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
692 if (!uc_priv->ataid[port]) {
Roger Quadros3f629712014-04-01 17:26:40 +0300693 printf("%s: No memory for ataid[port]\n", __func__);
694 return -ENOMEM;
695 }
696 }
697
Simon Glass4b62b2f2017-06-14 21:28:33 -0600698 idbuf = uc_priv->ataid[port];
Roger Quadros3f629712014-04-01 17:26:40 +0300699
700 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
701 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800702
703 memcpy(&pccb->pdata[8], "ATA ", 8);
Roger Quadros3f629712014-04-01 17:26:40 +0300704 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
705 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800706
Rob Herring344ca0b2013-08-24 10:10:54 -0500707#ifdef DEBUG
Roger Quadros3f629712014-04-01 17:26:40 +0300708 ata_dump_id(idbuf);
Rob Herring344ca0b2013-08-24 10:10:54 -0500709#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800710 return 0;
711}
712
713
714/*
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000715 * SCSI READ10/WRITE10 command operation.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800716 */
Simon Glass225b1da2017-06-14 21:28:34 -0600717static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
718 struct scsi_cmd *pccb, u8 is_write)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800719{
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100720 lbaint_t lba = 0;
Vadim Bendebury284231e2012-10-29 05:23:44 +0000721 u16 blocks = 0;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800722 u8 fis[20];
Vadim Bendebury284231e2012-10-29 05:23:44 +0000723 u8 *user_buffer = pccb->pdata;
724 u32 user_buffer_size = pccb->datalen;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800725
Vadim Bendebury284231e2012-10-29 05:23:44 +0000726 /* Retrieve the base LBA number from the ccb structure. */
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100727 if (pccb->cmd[0] == SCSI_READ16) {
728 memcpy(&lba, pccb->cmd + 2, 8);
729 lba = be64_to_cpu(lba);
730 } else {
731 u32 temp;
732 memcpy(&temp, pccb->cmd + 2, 4);
733 lba = be32_to_cpu(temp);
734 }
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800735
Vadim Bendebury284231e2012-10-29 05:23:44 +0000736 /*
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100737 * Retrieve the base LBA number and the block count from
738 * the ccb structure.
Vadim Bendebury284231e2012-10-29 05:23:44 +0000739 *
740 * For 10-byte and 16-byte SCSI R/W commands, transfer
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800741 * length 0 means transfer 0 block of data.
742 * However, for ATA R/W commands, sector count 0 means
743 * 256 or 65536 sectors, not 0 sectors as in SCSI.
744 *
745 * WARNING: one or two older ATA drives treat 0 as 0...
746 */
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100747 if (pccb->cmd[0] == SCSI_READ16)
748 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
749 else
750 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
Vadim Bendebury284231e2012-10-29 05:23:44 +0000751
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100752 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
753 is_write ? "write" : "read", blocks, lba);
Vadim Bendebury284231e2012-10-29 05:23:44 +0000754
755 /* Preset the FIS */
Taylor Huttc8731112012-10-29 05:23:55 +0000756 memset(fis, 0, sizeof(fis));
Vadim Bendebury284231e2012-10-29 05:23:44 +0000757 fis[0] = 0x27; /* Host to device FIS. */
758 fis[1] = 1 << 7; /* Command FIS. */
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000759 /* Command byte (read/write). */
Walter Murphyfe1f8082012-10-29 05:24:03 +0000760 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800761
Vadim Bendebury284231e2012-10-29 05:23:44 +0000762 while (blocks) {
763 u16 now_blocks; /* number of blocks per iteration */
764 u32 transfer_size; /* number of bytes per iteration */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800765
Masahiro Yamadab4141192014-11-07 03:03:31 +0900766 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800767
Rob Herring344ca0b2013-08-24 10:10:54 -0500768 transfer_size = ATA_SECT_SIZE * now_blocks;
Vadim Bendebury284231e2012-10-29 05:23:44 +0000769 if (transfer_size > user_buffer_size) {
770 printf("scsi_ahci: Error: buffer too small.\n");
771 return -EIO;
772 }
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800773
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100774 /*
775 * LBA48 SATA command but only use 32bit address range within
776 * that (unless we've enabled 64bit LBA support). The next
777 * smaller command range (28bit) is too small.
Walter Murphyfe1f8082012-10-29 05:24:03 +0000778 */
Vadim Bendebury284231e2012-10-29 05:23:44 +0000779 fis[4] = (lba >> 0) & 0xff;
780 fis[5] = (lba >> 8) & 0xff;
781 fis[6] = (lba >> 16) & 0xff;
Walter Murphyfe1f8082012-10-29 05:24:03 +0000782 fis[7] = 1 << 6; /* device reg: set LBA mode */
783 fis[8] = ((lba >> 24) & 0xff);
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100784#ifdef CONFIG_SYS_64BIT_LBA
785 if (pccb->cmd[0] == SCSI_READ16) {
786 fis[9] = ((lba >> 32) & 0xff);
787 fis[10] = ((lba >> 40) & 0xff);
788 }
789#endif
790
Walter Murphyfe1f8082012-10-29 05:24:03 +0000791 fis[3] = 0xe0; /* features */
Vadim Bendebury284231e2012-10-29 05:23:44 +0000792
793 /* Block (sector) count */
794 fis[12] = (now_blocks >> 0) & 0xff;
795 fis[13] = (now_blocks >> 8) & 0xff;
796
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000797 /* Read/Write from ahci */
Simon Glass225b1da2017-06-14 21:28:34 -0600798 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
799 sizeof(fis), user_buffer, transfer_size,
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000800 is_write)) {
801 debug("scsi_ahci: SCSI %s10 command failure.\n",
802 is_write ? "WRITE" : "READ");
Vadim Bendebury284231e2012-10-29 05:23:44 +0000803 return -EIO;
804 }
Marc Jones766b16f2012-10-29 05:24:02 +0000805
806 /* If this transaction is a write, do a following flush.
807 * Writes in u-boot are so rare, and the logic to know when is
808 * the last write and do a flush only there is sufficiently
809 * difficult. Just do a flush after every write. This incurs,
810 * usually, one extra flush when the rare writes do happen.
811 */
812 if (is_write) {
Simon Glass225b1da2017-06-14 21:28:34 -0600813 if (-EIO == ata_io_flush(uc_priv, pccb->target))
Marc Jones766b16f2012-10-29 05:24:02 +0000814 return -EIO;
815 }
Vadim Bendebury284231e2012-10-29 05:23:44 +0000816 user_buffer += transfer_size;
817 user_buffer_size -= transfer_size;
818 blocks -= now_blocks;
819 lba += now_blocks;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800820 }
821
822 return 0;
823}
824
825
826/*
827 * SCSI READ CAPACITY10 command operation.
828 */
Simon Glass4b62b2f2017-06-14 21:28:33 -0600829static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
830 struct scsi_cmd *pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800831{
Kumar Galacb6d0b72009-07-13 09:24:00 -0500832 u32 cap;
Rob Herring344ca0b2013-08-24 10:10:54 -0500833 u64 cap64;
Gabe Black19d1d412012-10-29 05:23:54 +0000834 u32 block_size;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800835
Simon Glass4b62b2f2017-06-14 21:28:33 -0600836 if (!uc_priv->ataid[pccb->target]) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800837 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500838 "\tNo ATA info!\n"
Vagrant Cascadian1b25e582015-11-24 14:46:24 -0800839 "\tPlease run SCSI command INQUIRY first!\n");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800840 return -EPERM;
841 }
842
Simon Glass4b62b2f2017-06-14 21:28:33 -0600843 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
Rob Herring344ca0b2013-08-24 10:10:54 -0500844 if (cap64 > 0x100000000ULL)
845 cap64 = 0xffffffff;
Gabe Black19d1d412012-10-29 05:23:54 +0000846
Rob Herring344ca0b2013-08-24 10:10:54 -0500847 cap = cpu_to_be32(cap64);
Kumar Galacb6d0b72009-07-13 09:24:00 -0500848 memcpy(pccb->pdata, &cap, sizeof(cap));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800849
Gabe Black19d1d412012-10-29 05:23:54 +0000850 block_size = cpu_to_be32((u32)512);
851 memcpy(&pccb->pdata[4], &block_size, 4);
852
853 return 0;
854}
855
856
857/*
858 * SCSI READ CAPACITY16 command operation.
859 */
Simon Glass4b62b2f2017-06-14 21:28:33 -0600860static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
861 struct scsi_cmd *pccb)
Gabe Black19d1d412012-10-29 05:23:54 +0000862{
863 u64 cap;
864 u64 block_size;
865
Simon Glass4b62b2f2017-06-14 21:28:33 -0600866 if (!uc_priv->ataid[pccb->target]) {
Gabe Black19d1d412012-10-29 05:23:54 +0000867 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
868 "\tNo ATA info!\n"
Vagrant Cascadian1b25e582015-11-24 14:46:24 -0800869 "\tPlease run SCSI command INQUIRY first!\n");
Gabe Black19d1d412012-10-29 05:23:54 +0000870 return -EPERM;
871 }
872
Simon Glass4b62b2f2017-06-14 21:28:33 -0600873 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
Gabe Black19d1d412012-10-29 05:23:54 +0000874 cap = cpu_to_be64(cap);
875 memcpy(pccb->pdata, &cap, sizeof(cap));
876
877 block_size = cpu_to_be64((u64)512);
878 memcpy(&pccb->pdata[8], &block_size, 8);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800879
880 return 0;
881}
882
883
884/*
885 * SCSI TEST UNIT READY command operation.
886 */
Simon Glass4b62b2f2017-06-14 21:28:33 -0600887static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
888 struct scsi_cmd *pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800889{
Simon Glass4b62b2f2017-06-14 21:28:33 -0600890 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800891}
892
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500893
Simon Glass4e749012017-06-14 21:28:42 -0600894static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800895{
Simon Glass4682c8a2017-06-14 21:28:40 -0600896 struct ahci_uc_priv *uc_priv;
897#ifdef CONFIG_DM_SCSI
Simon Glassbfc1c6b2017-07-04 13:31:22 -0600898 uc_priv = dev_get_uclass_priv(dev->parent);
Simon Glass4682c8a2017-06-14 21:28:40 -0600899#else
900 uc_priv = probe_ent;
901#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800902 int ret;
903
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500904 switch (pccb->cmd[0]) {
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100905 case SCSI_READ16:
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800906 case SCSI_READ10:
Simon Glass225b1da2017-06-14 21:28:34 -0600907 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000908 break;
909 case SCSI_WRITE10:
Simon Glass225b1da2017-06-14 21:28:34 -0600910 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800911 break;
Gabe Black19d1d412012-10-29 05:23:54 +0000912 case SCSI_RD_CAPAC10:
Simon Glass4b62b2f2017-06-14 21:28:33 -0600913 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800914 break;
Gabe Black19d1d412012-10-29 05:23:54 +0000915 case SCSI_RD_CAPAC16:
Simon Glass4b62b2f2017-06-14 21:28:33 -0600916 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
Gabe Black19d1d412012-10-29 05:23:54 +0000917 break;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800918 case SCSI_TST_U_RDY:
Simon Glass4b62b2f2017-06-14 21:28:33 -0600919 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800920 break;
921 case SCSI_INQUIRY:
Simon Glass4b62b2f2017-06-14 21:28:33 -0600922 ret = ata_scsiop_inquiry(uc_priv, pccb);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800923 break;
924 default:
925 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
Simon Glassf6580ef2017-06-14 21:28:44 -0600926 return -ENOTSUPP;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800927 }
928
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500929 if (ret) {
930 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
Simon Glassf6580ef2017-06-14 21:28:44 -0600931 return ret;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800932 }
Simon Glassf6580ef2017-06-14 21:28:44 -0600933 return 0;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800934
935}
936
Simon Glass62b4ec82017-06-14 21:28:36 -0600937static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
938{
939 u32 linkmap;
940 int i;
941
942 linkmap = uc_priv->link_port_map;
943
Tuomas Tynkkynen8bf207d2018-09-13 01:28:54 +0300944 for (i = 0; i < uc_priv->n_ports; i++) {
Simon Glass62b4ec82017-06-14 21:28:36 -0600945 if (((linkmap >> i) & 0x01)) {
946 if (ahci_port_start(uc_priv, (u8) i)) {
947 printf("Can not start port %d\n", i);
948 continue;
949 }
950 }
951 }
952
953 return 0;
954}
955
Simon Glass7cf1afc2017-06-14 21:28:37 -0600956#ifndef CONFIG_DM_SCSI
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800957void scsi_low_level_init(int busdevfunc)
958{
Simon Glass225b1da2017-06-14 21:28:34 -0600959 struct ahci_uc_priv *uc_priv;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800960
Rob Herring942e3142011-07-06 16:13:36 +0000961#ifndef CONFIG_SCSI_AHCI_PLAT
Simon Glass4279efc2017-06-14 21:28:38 -0600962 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
963 if (!probe_ent) {
964 printf("%s: No memory for uc_priv\n", __func__);
965 return;
966 }
967 uc_priv = probe_ent;
Simon Glassff758cc2015-11-29 13:18:06 -0700968 struct udevice *dev;
969 int ret;
970
971 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
972 if (ret)
973 return;
Simon Glass4279efc2017-06-14 21:28:38 -0600974 ahci_init_one(uc_priv, dev);
Simon Glass4279efc2017-06-14 21:28:38 -0600975#else
Simon Glass225b1da2017-06-14 21:28:34 -0600976 uc_priv = probe_ent;
Simon Glass4279efc2017-06-14 21:28:38 -0600977#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800978
Simon Glass62b4ec82017-06-14 21:28:36 -0600979 ahci_start_ports(uc_priv);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800980}
Simon Glass7cf1afc2017-06-14 21:28:37 -0600981#endif
982
983#ifndef CONFIG_SCSI_AHCI_PLAT
Michal Simeke81589e2017-11-02 15:53:56 +0100984int ahci_init_one_dm(struct udevice *dev)
Simon Glass7cf1afc2017-06-14 21:28:37 -0600985{
Simon Glass4279efc2017-06-14 21:28:38 -0600986 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
987
988 return ahci_init_one(uc_priv, dev);
Simon Glass7cf1afc2017-06-14 21:28:37 -0600989}
990#endif
Simon Glass7cf1afc2017-06-14 21:28:37 -0600991
Michal Simeke81589e2017-11-02 15:53:56 +0100992int ahci_start_ports_dm(struct udevice *dev)
Simon Glass7cf1afc2017-06-14 21:28:37 -0600993{
Simon Glass4279efc2017-06-14 21:28:38 -0600994 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass7cf1afc2017-06-14 21:28:37 -0600995
996 return ahci_start_ports(uc_priv);
997}
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800998
Rob Herring942e3142011-07-06 16:13:36 +0000999#ifdef CONFIG_SCSI_AHCI_PLAT
Simon Glass4279efc2017-06-14 21:28:38 -06001000static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
Rob Herring942e3142011-07-06 16:13:36 +00001001{
Simon Glass4279efc2017-06-14 21:28:38 -06001002 int rc;
Rob Herring942e3142011-07-06 16:13:36 +00001003
Simon Glass225b1da2017-06-14 21:28:34 -06001004 uc_priv->host_flags = ATA_FLAG_SATA
Rob Herring942e3142011-07-06 16:13:36 +00001005 | ATA_FLAG_NO_LEGACY
1006 | ATA_FLAG_MMIO
1007 | ATA_FLAG_PIO_DMA
1008 | ATA_FLAG_NO_ATAPI;
Simon Glass225b1da2017-06-14 21:28:34 -06001009 uc_priv->pio_mask = 0x1f;
1010 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
Rob Herring942e3142011-07-06 16:13:36 +00001011
Simon Glass225b1da2017-06-14 21:28:34 -06001012 uc_priv->mmio_base = base;
Rob Herring942e3142011-07-06 16:13:36 +00001013
1014 /* initialize adapter */
Simon Glass225b1da2017-06-14 21:28:34 -06001015 rc = ahci_host_init(uc_priv);
Rob Herring942e3142011-07-06 16:13:36 +00001016 if (rc)
1017 goto err_out;
1018
Simon Glass225b1da2017-06-14 21:28:34 -06001019 ahci_print_info(uc_priv);
Rob Herring942e3142011-07-06 16:13:36 +00001020
Simon Glass62b4ec82017-06-14 21:28:36 -06001021 rc = ahci_start_ports(uc_priv);
Rob Herring942e3142011-07-06 16:13:36 +00001022
Rob Herring942e3142011-07-06 16:13:36 +00001023err_out:
1024 return rc;
1025}
Ian Campbellc6f3d502014-03-07 01:20:56 +00001026
Simon Glass4279efc2017-06-14 21:28:38 -06001027#ifndef CONFIG_DM_SCSI
1028int ahci_init(void __iomem *base)
1029{
1030 struct ahci_uc_priv *uc_priv;
1031
1032 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1033 if (!probe_ent) {
1034 printf("%s: No memory for uc_priv\n", __func__);
1035 return -ENOMEM;
1036 }
1037
1038 uc_priv = probe_ent;
1039 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1040
1041 return ahci_init_common(uc_priv, base);
1042}
1043#endif
1044
1045int ahci_init_dm(struct udevice *dev, void __iomem *base)
1046{
1047 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1048
1049 return ahci_init_common(uc_priv, base);
1050}
1051
Ian Campbellc6f3d502014-03-07 01:20:56 +00001052void __weak scsi_init(void)
1053{
1054}
1055
Simon Glass4279efc2017-06-14 21:28:38 -06001056#endif /* CONFIG_SCSI_AHCI_PLAT */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001057
Marc Jones766b16f2012-10-29 05:24:02 +00001058/*
1059 * In the general case of generic rotating media it makes sense to have a
1060 * flush capability. It probably even makes sense in the case of SSDs because
1061 * one cannot always know for sure what kind of internal cache/flush mechanism
1062 * is embodied therein. At first it was planned to invoke this after the last
1063 * write to disk and before rebooting. In practice, knowing, a priori, which
1064 * is the last write is difficult. Because writing to the disk in u-boot is
1065 * very rare, this flush command will be invoked after every block write.
1066 */
Simon Glass225b1da2017-06-14 21:28:34 -06001067static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
Marc Jones766b16f2012-10-29 05:24:02 +00001068{
1069 u8 fis[20];
Simon Glass225b1da2017-06-14 21:28:34 -06001070 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantianfa313772015-07-09 14:37:30 +08001071 void __iomem *port_mmio = pp->port_mmio;
Marc Jones766b16f2012-10-29 05:24:02 +00001072 u32 cmd_fis_len = 5; /* five dwords */
1073
1074 /* Preset the FIS */
1075 memset(fis, 0, 20);
1076 fis[0] = 0x27; /* Host to device FIS. */
1077 fis[1] = 1 << 7; /* Command FIS. */
Walter Murphyfe1f8082012-10-29 05:24:03 +00001078 fis[2] = ATA_CMD_FLUSH_EXT;
Marc Jones766b16f2012-10-29 05:24:02 +00001079
1080 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1081 ahci_fill_cmd_slot(pp, cmd_fis_len);
Tang Yuantian75e14b12016-04-14 16:21:00 +08001082 ahci_dcache_flush_sata_cmd(pp);
Marc Jones766b16f2012-10-29 05:24:02 +00001083 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1084
1085 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1086 WAIT_MS_FLUSH, 0x1)) {
1087 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1088 return -EIO;
1089 }
1090
1091 return 0;
1092}
1093
Simon Glass4e749012017-06-14 21:28:42 -06001094static int ahci_scsi_bus_reset(struct udevice *dev)
1095{
1096 /* Not implemented */
1097
1098 return 0;
1099}
1100
Simon Glassf6ab5a92017-06-14 21:28:43 -06001101#ifdef CONFIG_DM_SCSI
Simon Glass681357f2017-06-14 21:28:46 -06001102int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
1103{
1104 struct udevice *dev;
1105 int ret;
1106
1107 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
1108 if (ret)
1109 return ret;
1110 *devp = dev;
1111
1112 return 0;
1113}
1114
Simon Glass745a94f2017-07-04 13:31:18 -06001115int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
Simon Glass681357f2017-06-14 21:28:46 -06001116{
Simon Glass681357f2017-06-14 21:28:46 -06001117 struct ahci_uc_priv *uc_priv;
Simon Glass8a8d24b2020-12-03 16:55:23 -07001118 struct scsi_plat *uc_plat;
Simon Glass681357f2017-06-14 21:28:46 -06001119 struct udevice *dev;
1120 int ret;
1121
1122 device_find_first_child(ahci_dev, &dev);
1123 if (!dev)
1124 return -ENODEV;
Simon Glasscaa4daa2020-12-03 16:55:18 -07001125 uc_plat = dev_get_uclass_plat(dev);
Simon Glass745a94f2017-07-04 13:31:18 -06001126 uc_plat->base = base;
Simon Glass681357f2017-06-14 21:28:46 -06001127 uc_plat->max_lun = 1;
1128 uc_plat->max_id = 2;
Simon Glass745a94f2017-07-04 13:31:18 -06001129
1130 uc_priv = dev_get_uclass_priv(ahci_dev);
Simon Glass681357f2017-06-14 21:28:46 -06001131 ret = ahci_init_one(uc_priv, dev);
1132 if (ret)
1133 return ret;
1134 ret = ahci_start_ports(uc_priv);
1135 if (ret)
1136 return ret;
Simon Glass681357f2017-06-14 21:28:46 -06001137
Park, Aidenbd98e6a2019-08-20 16:47:42 +00001138 /*
1139 * scsi_scan_dev() scans devices up-to the number of max_id.
1140 * Update max_id if the number of detected ports exceeds max_id.
1141 * This allows SCSI to scan all detected ports.
1142 */
1143 uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
1144 uc_plat->max_id);
Suneel Garapati98a81802021-03-25 17:07:36 -07001145 /* If port count is less than max_id, update max_id */
1146 if (uc_priv->n_ports < uc_plat->max_id)
1147 uc_plat->max_id = uc_priv->n_ports;
Park, Aidenbd98e6a2019-08-20 16:47:42 +00001148
Simon Glass681357f2017-06-14 21:28:46 -06001149 return 0;
1150}
1151
Simon Glass745a94f2017-07-04 13:31:18 -06001152int ahci_probe_scsi_pci(struct udevice *ahci_dev)
1153{
1154 ulong base;
Christian Gmeinercc625982023-04-11 17:07:02 +02001155 u16 vendor, device, cmd;
1156
1157 /* Enable bus mastering */
1158 dm_pci_read_config16(ahci_dev, PCI_COMMAND, &cmd);
1159 cmd |= PCI_COMMAND_MASTER;
1160 dm_pci_write_config16(ahci_dev, PCI_COMMAND, cmd);
Simon Glass745a94f2017-07-04 13:31:18 -06001161
Andrew Scull12507a22022-04-21 16:11:10 +00001162 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, 0, 0,
Andrew Scull2635e3b2022-04-21 16:11:13 +00001163 PCI_REGION_TYPE, PCI_REGION_MEM);
Simon Glass745a94f2017-07-04 13:31:18 -06001164
Suneel Garapati3f6f0cd2019-10-19 17:48:25 -07001165 /*
1166 * Note:
1167 * Right now, we have only one quirk here, which is not enough to
1168 * introduce a new Kconfig option to select this. Once we have more
1169 * quirks in this AHCI code, we should add a Kconfig option for
1170 * this though.
1171 */
1172 dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, &vendor);
1173 dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, &device);
1174
1175 if (vendor == PCI_VENDOR_ID_CAVIUM &&
1176 device == PCI_DEVICE_ID_CAVIUM_SATA)
Andrew Scull2635e3b2022-04-21 16:11:13 +00001177 base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
1178 0, 0, PCI_REGION_TYPE,
Suneel Garapati3f6f0cd2019-10-19 17:48:25 -07001179 PCI_REGION_MEM);
Simon Glass745a94f2017-07-04 13:31:18 -06001180 return ahci_probe_scsi(ahci_dev, base);
1181}
Simon Glass745a94f2017-07-04 13:31:18 -06001182
Simon Glassf6ab5a92017-06-14 21:28:43 -06001183struct scsi_ops scsi_ops = {
1184 .exec = ahci_scsi_exec,
1185 .bus_reset = ahci_scsi_bus_reset,
1186};
Simon Glass681357f2017-06-14 21:28:46 -06001187
1188U_BOOT_DRIVER(ahci_scsi) = {
1189 .name = "ahci_scsi",
1190 .id = UCLASS_SCSI,
1191 .ops = &scsi_ops,
1192};
Simon Glassf6ab5a92017-06-14 21:28:43 -06001193#else
Simon Glass4e749012017-06-14 21:28:42 -06001194int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
1195{
1196 return ahci_scsi_exec(dev, pccb);
1197}
Marc Jones766b16f2012-10-29 05:24:02 +00001198
Simon Glass4682c8a2017-06-14 21:28:40 -06001199__weak int scsi_bus_reset(struct udevice *dev)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001200{
Simon Glass4e749012017-06-14 21:28:42 -06001201 return ahci_scsi_bus_reset(dev);
Simon Glass4682c8a2017-06-14 21:28:40 -06001202
1203 return 0;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001204}
Simon Glassf6ab5a92017-06-14 21:28:43 -06001205#endif