Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 1 | if TEGRA |
| 2 | |
Simon Glass | 53b5bf3 | 2016-09-12 23:18:39 -0600 | [diff] [blame] | 3 | config SPL_GPIO_SUPPORT |
| 4 | default y |
| 5 | |
Simon Glass | 77d2f7f | 2016-09-12 23:18:41 -0600 | [diff] [blame] | 6 | config SPL_LIBCOMMON_SUPPORT |
| 7 | default y |
| 8 | |
Simon Glass | cc4288e | 2016-09-12 23:18:43 -0600 | [diff] [blame] | 9 | config SPL_LIBGENERIC_SUPPORT |
| 10 | default y |
| 11 | |
Simon Glass | e00f76c | 2016-09-12 23:18:56 -0600 | [diff] [blame] | 12 | config SPL_SERIAL_SUPPORT |
| 13 | default y |
| 14 | |
Thierry Reding | b64e0b9 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 15 | config TEGRA_CLKRST |
| 16 | bool |
| 17 | |
Thierry Reding | 9e57819 | 2019-04-15 11:32:19 +0200 | [diff] [blame^] | 18 | config TEGRA_GP_PADCTRL |
| 19 | bool |
| 20 | |
Stephen Warren | 49626ea | 2016-07-18 12:17:11 -0600 | [diff] [blame] | 21 | config TEGRA_IVC |
| 22 | bool "Tegra IVC protocol" |
| 23 | help |
| 24 | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC |
| 25 | (Inter Processor Communication) framework. Within the context of |
| 26 | U-Boot, it is typically used for communication between the main CPU |
| 27 | and various auxiliary processors. |
| 28 | |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 29 | config TEGRA_COMMON |
| 30 | bool "Tegra common options" |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 31 | select BINMAN |
| 32 | select BOARD_EARLY_INIT_F |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 33 | select CLK |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 34 | select DM |
Simon Glass | 96350f7 | 2015-11-29 13:18:01 -0700 | [diff] [blame] | 35 | select DM_ETH |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 36 | select DM_GPIO |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 37 | select DM_I2C |
Simon Glass | f77f5e9 | 2015-10-18 21:17:16 -0600 | [diff] [blame] | 38 | select DM_KEYBOARD |
Tom Warren | 6a474db | 2016-09-13 10:45:48 -0600 | [diff] [blame] | 39 | select DM_MMC |
Simon Glass | 91c08af | 2016-01-30 16:38:01 -0700 | [diff] [blame] | 40 | select DM_PWM |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 41 | select DM_RESET |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 42 | select DM_SERIAL |
| 43 | select DM_SPI |
| 44 | select DM_SPI_FLASH |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 45 | select MISC |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 46 | select OF_CONTROL |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 47 | select SPI |
Simon Glass | d6ef8a6 | 2016-02-16 18:09:19 -0700 | [diff] [blame] | 48 | select VIDCONSOLE_AS_LCD if DM_VIDEO |
Michal Simek | 08a00cb | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 49 | imply CMD_DM |
Daniel Thompson | 221a949 | 2017-05-19 17:26:58 +0100 | [diff] [blame] | 50 | imply CRC32_VERIFY |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 51 | |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 52 | config TEGRA_NO_BPMP |
| 53 | bool "Tegra common options for SoCs without BPMP" |
| 54 | select TEGRA_CAR |
| 55 | select TEGRA_CAR_CLOCK |
| 56 | select TEGRA_CAR_RESET |
| 57 | |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 58 | config TEGRA_ARMV7_COMMON |
| 59 | bool "Tegra 32-bit common options" |
Lokesh Vutla | acf1500 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 60 | select CPU_V7A |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 61 | select SPL |
Ley Foon Tan | 0680f1b | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 62 | select SPL_BOARD_INIT if SPL |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 63 | select SUPPORT_SPL |
Thierry Reding | b64e0b9 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 64 | select TEGRA_CLKRST |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 65 | select TEGRA_COMMON |
Stephen Warren | 601800b | 2016-05-12 12:07:41 -0600 | [diff] [blame] | 66 | select TEGRA_GPIO |
Thierry Reding | 9e57819 | 2019-04-15 11:32:19 +0200 | [diff] [blame^] | 67 | select TEGRA_GP_PADCTRL |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 68 | select TEGRA_NO_BPMP |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 69 | |
| 70 | config TEGRA_ARMV8_COMMON |
| 71 | bool "Tegra 64-bit common options" |
| 72 | select ARM64 |
Stephen Warren | ddecaaf | 2018-01-03 14:31:52 -0700 | [diff] [blame] | 73 | select LINUX_KERNEL_IMAGE_HEADER |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 74 | select TEGRA_COMMON |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 75 | |
Stephen Warren | ddecaaf | 2018-01-03 14:31:52 -0700 | [diff] [blame] | 76 | if TEGRA_ARMV8_COMMON |
| 77 | config LNX_KRNL_IMG_TEXT_OFFSET_BASE |
| 78 | default 0x80000000 |
| 79 | endif |
| 80 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 81 | choice |
| 82 | prompt "Tegra SoC select" |
Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 83 | optional |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 84 | |
| 85 | config TEGRA20 |
| 86 | bool "Tegra20 family" |
Tom Rini | 8dda2e2 | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 87 | select ARM_ERRATA_716044 |
| 88 | select ARM_ERRATA_742230 |
| 89 | select ARM_ERRATA_751472 |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 90 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 91 | |
| 92 | config TEGRA30 |
| 93 | bool "Tegra30 family" |
Tom Rini | 8dda2e2 | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 94 | select ARM_ERRATA_743622 |
| 95 | select ARM_ERRATA_751472 |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 96 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 97 | |
| 98 | config TEGRA114 |
| 99 | bool "Tegra114 family" |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 100 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 101 | |
| 102 | config TEGRA124 |
| 103 | bool "Tegra124 family" |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 104 | select TEGRA_ARMV7_COMMON |
Simon Glass | 66de3ee | 2017-07-25 08:29:58 -0600 | [diff] [blame] | 105 | imply REGMAP |
| 106 | imply SYSCON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 107 | |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 108 | config TEGRA210 |
| 109 | bool "Tegra210 family" |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 110 | select TEGRA_ARMV8_COMMON |
Thierry Reding | b64e0b9 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 111 | select TEGRA_CLKRST |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 112 | select TEGRA_GPIO |
Thierry Reding | 9e57819 | 2019-04-15 11:32:19 +0200 | [diff] [blame^] | 113 | select TEGRA_GP_PADCTRL |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 114 | select TEGRA_NO_BPMP |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 115 | |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 116 | config TEGRA186 |
| 117 | bool "Tegra186 family" |
Stephen Warren | 0f67e23 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 118 | select DM_MAILBOX |
Stephen Warren | 73dd5c4 | 2016-08-08 09:41:34 -0600 | [diff] [blame] | 119 | select TEGRA186_BPMP |
Stephen Warren | d9fd700 | 2016-08-08 11:28:24 -0600 | [diff] [blame] | 120 | select TEGRA186_CLOCK |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 121 | select TEGRA186_GPIO |
Stephen Warren | 4dd99d1 | 2016-08-08 11:28:25 -0600 | [diff] [blame] | 122 | select TEGRA186_RESET |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 123 | select TEGRA_ARMV8_COMMON |
Stephen Warren | 0f67e23 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 124 | select TEGRA_HSP |
Stephen Warren | 49626ea | 2016-07-18 12:17:11 -0600 | [diff] [blame] | 125 | select TEGRA_IVC |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 126 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 127 | endchoice |
| 128 | |
Stephen Warren | dd8204d | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 129 | config TEGRA_DISCONNECT_UDC_ON_BOOT |
| 130 | bool "Disconnect USB device mode controller on boot" |
| 131 | default y |
| 132 | help |
| 133 | When loading U-Boot into RAM over USB protocols using tools such as |
| 134 | tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device |
| 135 | mode controller is initialized and enumerated by the host PC running |
| 136 | the tool. Unfortunately, these tools do not shut down the USB |
| 137 | controller before executing the downloaded code, and so the host PC |
| 138 | does not "de-enumerate" the USB device. This option shuts down the |
| 139 | USB controller when U-Boot boots to avoid leaving a stale USB device |
| 140 | present. |
| 141 | |
Simon Glass | b724bd7 | 2015-02-11 16:32:59 -0700 | [diff] [blame] | 142 | config SYS_MALLOC_F_LEN |
| 143 | default 0x1800 |
| 144 | |
Masahiro Yamada | 09f455d | 2015-02-20 17:04:04 +0900 | [diff] [blame] | 145 | source "arch/arm/mach-tegra/tegra20/Kconfig" |
| 146 | source "arch/arm/mach-tegra/tegra30/Kconfig" |
| 147 | source "arch/arm/mach-tegra/tegra114/Kconfig" |
| 148 | source "arch/arm/mach-tegra/tegra124/Kconfig" |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 149 | source "arch/arm/mach-tegra/tegra210/Kconfig" |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 150 | source "arch/arm/mach-tegra/tegra186/Kconfig" |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 151 | |
Simon Glass | 42e6f85 | 2017-05-17 03:25:11 -0600 | [diff] [blame] | 152 | config CMD_ENTERRCM |
| 153 | bool "Enable 'enterrcm' command" |
| 154 | default y |
| 155 | help |
| 156 | Tegra's boot ROM supports a mode whereby code may be downloaded and |
| 157 | flash-programmed over a USB connection. On dev boards, this is |
| 158 | typically entered by holding down a "force recovery" button and |
| 159 | resetting the CPU. However, not all boards have such a button (one |
| 160 | example is the Compulab Trimslice), so a method to enter RCM from |
| 161 | software is useful. |
| 162 | |
| 163 | Even on boards other than Trimslice, controlling this over a UART |
| 164 | may be useful, e.g. to allow simple remote control without the need |
| 165 | for mechanical button actuators, or hooking up relays/... to the |
| 166 | button. |
| 167 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 168 | endif |