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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Dave Liu03051c32007-09-18 12:36:11 +08005 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
Eran Libertyf046ccd2005-07-28 10:08:46 -050024 */
25
26#include <common.h>
27#include <mpc83xx.h>
Kim Phillips54b2d432007-04-30 15:26:21 -050028#include <command.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050029#include <asm/processor.h>
30
Wolfgang Denkd87080b2006-03-31 18:32:53 +020031DECLARE_GLOBAL_DATA_PTR;
32
Eran Libertyf046ccd2005-07-28 10:08:46 -050033/* ----------------------------------------------------------------- */
34
35typedef enum {
36 _unk,
37 _off,
38 _byp,
39 _x8,
40 _x4,
41 _x2,
42 _x1,
43 _1x,
44 _1_5x,
45 _2x,
46 _2_5x,
47 _3x
48} mult_t;
49
50typedef struct {
51 mult_t core_csb_ratio;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060052 mult_t vco_divider;
Eran Libertyf046ccd2005-07-28 10:08:46 -050053} corecnf_t;
54
55corecnf_t corecnf_tab[] = {
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060056 {_byp, _byp}, /* 0x00 */
57 {_byp, _byp}, /* 0x01 */
58 {_byp, _byp}, /* 0x02 */
59 {_byp, _byp}, /* 0x03 */
60 {_byp, _byp}, /* 0x04 */
61 {_byp, _byp}, /* 0x05 */
62 {_byp, _byp}, /* 0x06 */
63 {_byp, _byp}, /* 0x07 */
64 {_1x, _x2}, /* 0x08 */
65 {_1x, _x4}, /* 0x09 */
66 {_1x, _x8}, /* 0x0A */
67 {_1x, _x8}, /* 0x0B */
68 {_1_5x, _x2}, /* 0x0C */
69 {_1_5x, _x4}, /* 0x0D */
70 {_1_5x, _x8}, /* 0x0E */
71 {_1_5x, _x8}, /* 0x0F */
72 {_2x, _x2}, /* 0x10 */
73 {_2x, _x4}, /* 0x11 */
74 {_2x, _x8}, /* 0x12 */
75 {_2x, _x8}, /* 0x13 */
76 {_2_5x, _x2}, /* 0x14 */
77 {_2_5x, _x4}, /* 0x15 */
78 {_2_5x, _x8}, /* 0x16 */
79 {_2_5x, _x8}, /* 0x17 */
80 {_3x, _x2}, /* 0x18 */
81 {_3x, _x4}, /* 0x19 */
82 {_3x, _x8}, /* 0x1A */
83 {_3x, _x8}, /* 0x1B */
Eran Libertyf046ccd2005-07-28 10:08:46 -050084};
85
86/* ----------------------------------------------------------------- */
87
88/*
89 *
90 */
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060091int get_clocks(void)
Eran Libertyf046ccd2005-07-28 10:08:46 -050092{
Timur Tabid239d742006-11-03 12:00:28 -060093 volatile immap_t *im = (immap_t *) CFG_IMMR;
Eran Libertyf046ccd2005-07-28 10:08:46 -050094 u32 pci_sync_in;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060095 u8 spmf;
96 u8 clkin_div;
Eran Libertyf046ccd2005-07-28 10:08:46 -050097 u32 sccr;
98 u32 corecnf_tab_index;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060099 u8 corepll;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500100 u32 lcrr;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500101
Eran Libertyf046ccd2005-07-28 10:08:46 -0500102 u32 csb_clk;
Dave Liu03051c32007-09-18 12:36:11 +0800103#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500104 u32 tsec1_clk;
105 u32 tsec2_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500106 u32 usbdr_clk;
Dave Liu5f820432006-11-03 19:33:44 -0600107#endif
Scott Wood7c98e512007-04-16 14:34:19 -0500108#ifdef CONFIG_MPC834X
109 u32 usbmph_clk;
110#endif
Dave Liu5f820432006-11-03 19:33:44 -0600111 u32 core_clk;
112 u32 i2c1_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800113#if !defined(CONFIG_MPC832X)
Dave Liu5f820432006-11-03 19:33:44 -0600114 u32 i2c2_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800115#endif
Dave Liu555da612007-09-18 12:36:58 +0800116#if defined(CONFIG_MPC8315)
117 u32 tdm_clk;
118#endif
Dave Liu03051c32007-09-18 12:36:11 +0800119#if defined(CONFIG_MPC837X)
120 u32 sdhc_clk;
121#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500122 u32 enc_clk;
123 u32 lbiu_clk;
124 u32 lclk_clk;
125 u32 ddr_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800126#if defined(CONFIG_MPC8360)
127 u32 ddr_sec_clk;
128#endif
129#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Dave Liu5f820432006-11-03 19:33:44 -0600130 u32 qepmf;
131 u32 qepdf;
Dave Liu5f820432006-11-03 19:33:44 -0600132 u32 qe_clk;
133 u32 brg_clk;
134#endif
Dave Liu03051c32007-09-18 12:36:11 +0800135#if defined(CONFIG_MPC837X)
136 u32 pciexp1_clk;
137 u32 pciexp2_clk;
Dave Liu555da612007-09-18 12:36:58 +0800138#endif
139#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
Dave Liu03051c32007-09-18 12:36:11 +0800140 u32 sata_clk;
141#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500142
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600143 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500144 return -1;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500145
Eran Libertyf046ccd2005-07-28 10:08:46 -0500146 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500147
Dave Liu5f820432006-11-03 19:33:44 -0600148 if (im->reset.rcwh & HRCWH_PCI_HOST) {
149#if defined(CONFIG_83XX_CLKIN)
150 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
151#else
152 pci_sync_in = 0xDEADBEEF;
153#endif
154 } else {
155#if defined(CONFIG_83XX_PCICLK)
156 pci_sync_in = CONFIG_83XX_PCICLK;
157#else
158 pci_sync_in = 0xDEADBEEF;
159#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500160 }
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500161
Dave Liue0803132006-12-07 21:11:58 +0800162 spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
Dave Liu5f820432006-11-03 19:33:44 -0600163 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
164
Eran Libertyf046ccd2005-07-28 10:08:46 -0500165 sccr = im->clk.sccr;
Dave Liu5f820432006-11-03 19:33:44 -0600166
Dave Liu03051c32007-09-18 12:36:11 +0800167#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500168 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
169 case 0:
170 tsec1_clk = 0;
171 break;
172 case 1:
173 tsec1_clk = csb_clk;
174 break;
175 case 2:
176 tsec1_clk = csb_clk / 2;
177 break;
178 case 3:
179 tsec1_clk = csb_clk / 3;
180 break;
181 default:
182 /* unkown SCCR_TSEC1CM value */
Dave Liu03051c32007-09-18 12:36:11 +0800183 return -2;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500184 }
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500185
Scott Wood7c98e512007-04-16 14:34:19 -0500186 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
187 case 0:
188 usbdr_clk = 0;
189 break;
190 case 1:
191 usbdr_clk = csb_clk;
192 break;
193 case 2:
194 usbdr_clk = csb_clk / 2;
195 break;
196 case 3:
197 usbdr_clk = csb_clk / 3;
198 break;
199 default:
200 /* unkown SCCR_USBDRCM value */
Dave Liu03051c32007-09-18 12:36:11 +0800201 return -3;
Scott Wood7c98e512007-04-16 14:34:19 -0500202 }
203#endif
204
Dave Liu555da612007-09-18 12:36:58 +0800205#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500206 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
207 case 0:
208 tsec2_clk = 0;
209 break;
210 case 1:
211 tsec2_clk = csb_clk;
212 break;
213 case 2:
214 tsec2_clk = csb_clk / 2;
215 break;
216 case 3:
217 tsec2_clk = csb_clk / 3;
218 break;
219 default:
220 /* unkown SCCR_TSEC2CM value */
Dave Liu03051c32007-09-18 12:36:11 +0800221 return -4;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500222 }
Dave Liu555da612007-09-18 12:36:58 +0800223#elif defined(CONFIG_MPC8313)
Dave Liu03051c32007-09-18 12:36:11 +0800224 tsec2_clk = tsec1_clk;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500225
Dave Liu03051c32007-09-18 12:36:11 +0800226 if (!(sccr & SCCR_TSEC1ON))
227 tsec1_clk = 0;
228 if (!(sccr & SCCR_TSEC2ON))
229 tsec2_clk = 0;
230#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500231
Dave Liu03051c32007-09-18 12:36:11 +0800232#if defined(CONFIG_MPC834X)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500233 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
234 case 0:
235 usbmph_clk = 0;
236 break;
237 case 1:
238 usbmph_clk = csb_clk;
239 break;
240 case 2:
241 usbmph_clk = csb_clk / 2;
242 break;
243 case 3:
244 usbmph_clk = csb_clk / 3;
245 break;
246 default:
247 /* unkown SCCR_USBMPHCM value */
Dave Liu03051c32007-09-18 12:36:11 +0800248 return -5;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500249 }
250
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600251 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
252 /* if USB MPH clock is not disabled and
253 * USB DR clock is not disabled then
254 * USB MPH & USB DR must have the same rate
255 */
Dave Liu03051c32007-09-18 12:36:11 +0800256 return -6;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500257 }
Dave Liu5f820432006-11-03 19:33:44 -0600258#endif
Dave Liu5f820432006-11-03 19:33:44 -0600259 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
260 case 0:
261 enc_clk = 0;
262 break;
263 case 1:
264 enc_clk = csb_clk;
265 break;
266 case 2:
267 enc_clk = csb_clk / 2;
268 break;
269 case 3:
270 enc_clk = csb_clk / 3;
271 break;
272 default:
273 /* unkown SCCR_ENCCM value */
Dave Liu03051c32007-09-18 12:36:11 +0800274 return -7;
Dave Liu5f820432006-11-03 19:33:44 -0600275 }
Dave Liu24c3aca2006-12-07 21:13:15 +0800276
Dave Liu03051c32007-09-18 12:36:11 +0800277#if defined(CONFIG_MPC837X)
278 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
279 case 0:
280 sdhc_clk = 0;
281 break;
282 case 1:
283 sdhc_clk = csb_clk;
284 break;
285 case 2:
286 sdhc_clk = csb_clk / 2;
287 break;
288 case 3:
289 sdhc_clk = csb_clk / 3;
290 break;
291 default:
292 /* unkown SCCR_SDHCCM value */
293 return -8;
294 }
295#endif
Dave Liu555da612007-09-18 12:36:58 +0800296#if defined(CONFIG_MPC8315)
297 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
298 case 0:
299 tdm_clk = 0;
300 break;
301 case 1:
302 tdm_clk = csb_clk;
303 break;
304 case 2:
305 tdm_clk = csb_clk / 2;
306 break;
307 case 3:
308 tdm_clk = csb_clk / 3;
309 break;
310 default:
311 /* unkown SCCR_TDMCM value */
312 return -8;
313 }
314#endif
Dave Liu03051c32007-09-18 12:36:11 +0800315
316#if defined(CONFIG_MPC834X)
317 i2c1_clk = tsec2_clk;
318#elif defined(CONFIG_MPC8360)
319 i2c1_clk = csb_clk;
320#elif defined(CONFIG_MPC832X)
321 i2c1_clk = enc_clk;
322#elif defined(CONFIG_MPC831X)
323 i2c1_clk = enc_clk;
324#elif defined(CONFIG_MPC837X)
325 i2c1_clk = sdhc_clk;
326#endif
327#if !defined(CONFIG_MPC832X)
328 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
329#endif
330
331#if defined(CONFIG_MPC837X)
332 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
333 case 0:
334 pciexp1_clk = 0;
335 break;
336 case 1:
337 pciexp1_clk = csb_clk;
338 break;
339 case 2:
340 pciexp1_clk = csb_clk / 2;
341 break;
342 case 3:
343 pciexp1_clk = csb_clk / 3;
344 break;
345 default:
346 /* unkown SCCR_PCIEXP1CM value */
347 return -9;
348 }
349
350 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
351 case 0:
352 pciexp2_clk = 0;
353 break;
354 case 1:
355 pciexp2_clk = csb_clk;
356 break;
357 case 2:
358 pciexp2_clk = csb_clk / 2;
359 break;
360 case 3:
361 pciexp2_clk = csb_clk / 3;
362 break;
363 default:
364 /* unkown SCCR_PCIEXP2CM value */
365 return -10;
366 }
367#endif
368
Dave Liu555da612007-09-18 12:36:58 +0800369#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
Kim Phillips9e896472008-01-16 12:06:16 -0600370 switch ((sccr & SCCR_SATACM) >> SCCR_SATACM_SHIFT) {
371 case SCCR_SATACM_0:
Dave Liu03051c32007-09-18 12:36:11 +0800372 sata_clk = 0;
373 break;
Kim Phillips9e896472008-01-16 12:06:16 -0600374 case SCCR_SATACM_1:
Dave Liu03051c32007-09-18 12:36:11 +0800375 sata_clk = csb_clk;
376 break;
Kim Phillips9e896472008-01-16 12:06:16 -0600377 case SCCR_SATACM_2:
Dave Liu03051c32007-09-18 12:36:11 +0800378 sata_clk = csb_clk / 2;
379 break;
Kim Phillips9e896472008-01-16 12:06:16 -0600380 case SCCR_SATACM_3:
Dave Liu03051c32007-09-18 12:36:11 +0800381 sata_clk = csb_clk / 3;
382 break;
383 default:
Kim Phillips9e896472008-01-16 12:06:16 -0600384 /* unkown SCCR_SATACM value */
Dave Liu03051c32007-09-18 12:36:11 +0800385 return -11;
386 }
387#endif
388
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600389 lbiu_clk = csb_clk *
Dave Liue0803132006-12-07 21:11:58 +0800390 (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
Eran Libertyf046ccd2005-07-28 10:08:46 -0500391 lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
392 switch (lcrr) {
393 case 2:
394 case 4:
395 case 8:
396 lclk_clk = lbiu_clk / lcrr;
397 break;
398 default:
399 /* unknown lcrr */
Dave Liu03051c32007-09-18 12:36:11 +0800400 return -12;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500401 }
Dave Liu24c3aca2006-12-07 21:13:15 +0800402
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600403 ddr_clk = csb_clk *
Dave Liue0803132006-12-07 21:11:58 +0800404 (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
405 corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
Dave Liu24c3aca2006-12-07 21:13:15 +0800406#if defined(CONFIG_MPC8360)
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600407 ddr_sec_clk = csb_clk * (1 +
Dave Liue0803132006-12-07 21:11:58 +0800408 ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
Dave Liu5f820432006-11-03 19:33:44 -0600409#endif
Dave Liu5f820432006-11-03 19:33:44 -0600410
Eran Libertyf046ccd2005-07-28 10:08:46 -0500411 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600412 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
Eran Libertyf046ccd2005-07-28 10:08:46 -0500413 /* corecnf_tab_index is too high, possibly worng value */
414 return -11;
415 }
416 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
417 case _byp:
418 case _x1:
419 case _1x:
420 core_clk = csb_clk;
421 break;
422 case _1_5x:
423 core_clk = (3 * csb_clk) / 2;
424 break;
425 case _2x:
426 core_clk = 2 * csb_clk;
427 break;
428 case _2_5x:
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600429 core_clk = (5 * csb_clk) / 2;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500430 break;
431 case _3x:
432 core_clk = 3 * csb_clk;
433 break;
434 default:
435 /* unkown core to csb ratio */
Dave Liu03051c32007-09-18 12:36:11 +0800436 return -13;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500437 }
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500438
Dave Liu24c3aca2006-12-07 21:13:15 +0800439#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Dave Liue0803132006-12-07 21:11:58 +0800440 qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
441 qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600442 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
Dave Liu5f820432006-11-03 19:33:44 -0600443 brg_clk = qe_clk / 2;
444#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500445
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600446 gd->csb_clk = csb_clk;
Dave Liu03051c32007-09-18 12:36:11 +0800447#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600448 gd->tsec1_clk = tsec1_clk;
449 gd->tsec2_clk = tsec2_clk;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600450 gd->usbdr_clk = usbdr_clk;
Dave Liu5f820432006-11-03 19:33:44 -0600451#endif
Scott Wood7c98e512007-04-16 14:34:19 -0500452#if defined(CONFIG_MPC834X)
453 gd->usbmph_clk = usbmph_clk;
454#endif
Dave Liu555da612007-09-18 12:36:58 +0800455#if defined(CONFIG_MPC8315)
456 gd->tdm_clk = tdm_clk;
457#endif
Dave Liu03051c32007-09-18 12:36:11 +0800458#if defined(CONFIG_MPC837X)
459 gd->sdhc_clk = sdhc_clk;
460#endif
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600461 gd->core_clk = core_clk;
462 gd->i2c1_clk = i2c1_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800463#if !defined(CONFIG_MPC832X)
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600464 gd->i2c2_clk = i2c2_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800465#endif
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600466 gd->enc_clk = enc_clk;
467 gd->lbiu_clk = lbiu_clk;
468 gd->lclk_clk = lclk_clk;
469 gd->ddr_clk = ddr_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800470#if defined(CONFIG_MPC8360)
Dave Liu5f820432006-11-03 19:33:44 -0600471 gd->ddr_sec_clk = ddr_sec_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800472#endif
473#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600474 gd->qe_clk = qe_clk;
475 gd->brg_clk = brg_clk;
Dave Liu5f820432006-11-03 19:33:44 -0600476#endif
Dave Liu03051c32007-09-18 12:36:11 +0800477#if defined(CONFIG_MPC837X)
478 gd->pciexp1_clk = pciexp1_clk;
479 gd->pciexp2_clk = pciexp2_clk;
Dave Liu555da612007-09-18 12:36:58 +0800480#endif
481#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
Dave Liu03051c32007-09-18 12:36:11 +0800482 gd->sata_clk = sata_clk;
483#endif
Kim Phillips8f9e0e92007-08-15 22:30:19 -0500484 gd->pci_clk = pci_sync_in;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600485 gd->cpu_clk = gd->core_clk;
486 gd->bus_clk = gd->csb_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500487 return 0;
Dave Liu5f820432006-11-03 19:33:44 -0600488
Eran Libertyf046ccd2005-07-28 10:08:46 -0500489}
490
491/********************************************
492 * get_bus_freq
493 * return system bus freq in Hz
494 *********************************************/
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600495ulong get_bus_freq(ulong dummy)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500496{
Eran Libertyf046ccd2005-07-28 10:08:46 -0500497 return gd->csb_clk;
498}
499
Kim Phillips54b2d432007-04-30 15:26:21 -0500500int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
Eran Libertyf046ccd2005-07-28 10:08:46 -0500501{
Eran Libertyf046ccd2005-07-28 10:08:46 -0500502 printf("Clock configuration:\n");
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600503 printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
Kim Phillips54b2d432007-04-30 15:26:21 -0500504 printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
Dave Liu24c3aca2006-12-07 21:13:15 +0800505#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600506 printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
Dave Liu24c3aca2006-12-07 21:13:15 +0800507 printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000);
Dave Liu5f820432006-11-03 19:33:44 -0600508#endif
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600509 printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
510 printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
511 printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
Dave Liu24c3aca2006-12-07 21:13:15 +0800512#if defined(CONFIG_MPC8360)
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600513 printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
Dave Liu5f820432006-11-03 19:33:44 -0600514#endif
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600515 printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
516 printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
Dave Liu24c3aca2006-12-07 21:13:15 +0800517#if !defined(CONFIG_MPC832X)
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600518 printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
Dave Liu24c3aca2006-12-07 21:13:15 +0800519#endif
Dave Liu555da612007-09-18 12:36:58 +0800520#if defined(CONFIG_MPC8315)
521 printf(" TDM: %4d MHz\n", gd->tdm_clk / 1000000);
522#endif
Dave Liu03051c32007-09-18 12:36:11 +0800523#if defined(CONFIG_MPC837X)
524 printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000);
525#endif
526#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600527 printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
528 printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600529 printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);
Dave Liu5f820432006-11-03 19:33:44 -0600530#endif
Scott Wood7c98e512007-04-16 14:34:19 -0500531#if defined(CONFIG_MPC834X)
532 printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
533#endif
Dave Liu03051c32007-09-18 12:36:11 +0800534#if defined(CONFIG_MPC837X)
535 printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000);
536 printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000);
Dave Liu555da612007-09-18 12:36:58 +0800537#endif
538#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
Dave Liu03051c32007-09-18 12:36:11 +0800539 printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000);
540#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500541 return 0;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500542}
Kim Phillips54b2d432007-04-30 15:26:21 -0500543
544U_BOOT_CMD(clocks, 1, 0, do_clocks,
545 "clocks - print clock configuration\n",
546 " clocks\n"
547);