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Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +01001/*
2 * Copyright (C) 2004-2007 ARM Limited.
3 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
Tom Rini5b8031c2016-01-14 22:05:13 -05005 * SPDX-License-Identifier: GPL-2.0
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +01006 *
7 * As a special exception, if other files instantiate templates or use macros
8 * or inline functions from this file, or you compile this file and link it
9 * with other works to produce a work based on this file, this file does not
10 * by itself cause the resulting work to be covered by the GNU General Public
11 * License. However the source code for this file must still be made available
12 * in accordance with section (3) of the GNU General Public License.
13
14 * This exception does not invalidate any other reasons why a work based on
15 * this file might be covered by the GNU General Public License.
16 */
17
18#include <common.h>
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +053019#include <serial.h>
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010020
Alexander Merklefd602c52015-03-19 18:37:19 +010021#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010022/*
Alexander Merklefd602c52015-03-19 18:37:19 +010023 * ARMV6 & ARMV7
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010024 */
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020025#define DCC_RBIT (1 << 30)
26#define DCC_WBIT (1 << 29)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010027
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020028#define write_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010029 __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
30
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020031#define read_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010032 __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
33
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020034#define status_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010035 __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
36
Jean-Christophe PLAGNIOL-VILLARD65a76d42009-05-15 23:47:14 +020037#elif defined(CONFIG_CPU_XSCALE)
38/*
39 * XSCALE
40 */
41#define DCC_RBIT (1 << 31)
42#define DCC_WBIT (1 << 28)
43
44#define write_dcc(x) \
45 __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
46
47#define read_dcc(x) \
48 __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
49
50#define status_dcc(x) \
51 __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
52
Siva Durga Prasad Paladugue05412f2015-05-29 09:54:37 +020053#elif defined(CONFIG_CPU_ARMV8)
54/*
55 * ARMV8
56 */
57#define DCC_RBIT (1 << 30)
58#define DCC_WBIT (1 << 29)
59
60#define write_dcc(x) \
61 __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x))
62
63#define read_dcc(x) \
64 __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x))
65
66#define status_dcc(x) \
67 __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x))
68
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020069#else
70#define DCC_RBIT (1 << 0)
71#define DCC_WBIT (1 << 1)
72
73#define write_dcc(x) \
74 __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
75
76#define read_dcc(x) \
77 __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
78
79#define status_dcc(x) \
80 __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
81
82#endif
83
84#define can_read_dcc(x) do { \
85 status_dcc(x); \
86 x &= DCC_RBIT; \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010087 } while (0);
88
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020089#define can_write_dcc(x) do { \
90 status_dcc(x); \
91 x &= DCC_WBIT; \
92 x = (x == 0); \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010093 } while (0);
94
95#define TIMEOUT_COUNT 0x4000000
96
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +053097static int arm_dcc_init(void)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010098{
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010099 return 0;
100}
101
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530102static int arm_dcc_getc(void)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100103{
104 int ch;
105 register unsigned int reg;
106
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200107 do {
108 can_read_dcc(reg);
109 } while (!reg);
110 read_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100111
112 return ch;
113}
114
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530115static void arm_dcc_putc(char ch)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100116{
117 register unsigned int reg;
118 unsigned int timeout_count = TIMEOUT_COUNT;
119
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200120 while (--timeout_count) {
121 can_write_dcc(reg);
122 if (reg)
123 break;
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100124 }
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200125 if (timeout_count == 0)
126 return;
127 else
128 write_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100129}
130
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530131static int arm_dcc_tstc(void)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100132{
133 register unsigned int reg;
134
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200135 can_read_dcc(reg);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100136
137 return reg;
138}
139
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530140static void arm_dcc_setbrg(void)
141{
142}
143
144static struct serial_device arm_dcc_drv = {
145 .name = "arm_dcc",
146 .start = arm_dcc_init,
147 .stop = NULL,
148 .setbrg = arm_dcc_setbrg,
149 .putc = arm_dcc_putc,
Axel Lin012a2c12013-08-17 15:39:34 +0800150 .puts = default_serial_puts,
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530151 .getc = arm_dcc_getc,
152 .tstc = arm_dcc_tstc,
153};
154
155void arm_dcc_initialize(void)
156{
157 serial_register(&arm_dcc_drv);
158}
159
Michal Simeke70fb532013-01-22 23:40:06 +0000160__weak struct serial_device *default_serial_console(void)
161{
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530162 return &arm_dcc_drv;
Michal Simeke70fb532013-01-22 23:40:06 +0000163}