blob: 09c0b043e7f3039b29b18a6e2081db2cf5dde78c [file] [log] [blame]
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +01001/*
2 * (C) Copyright 2006 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010025
Jon Loeligerb9307262007-07-09 18:24:55 -050026#if defined(CONFIG_CMD_NAND)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010027
28#include <nand.h>
29
30/*
31 * hardware specific access to control-lines
32 * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
33 */
34static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
35{
36 struct nand_chip *this = mtdinfo->priv;
37 ulong base = (ulong) this->IO_ADDR_W;
38
39 switch(cmd) {
40 case NAND_CTL_SETCLE:
41 MACRO_NAND_CTL_SETCLE((unsigned long)base);
42 break;
43 case NAND_CTL_CLRCLE:
44 MACRO_NAND_CTL_CLRCLE((unsigned long)base);
45 break;
46 case NAND_CTL_SETALE:
47 MACRO_NAND_CTL_SETALE((unsigned long)base);
48 break;
49 case NAND_CTL_CLRALE:
50 MACRO_NAND_CTL_CLRALE((unsigned long)base);
51 break;
52 case NAND_CTL_SETNCE:
53 MACRO_NAND_ENABLE_CE((unsigned long)base);
54 break;
55 case NAND_CTL_CLRNCE:
56 MACRO_NAND_DISABLE_CE((unsigned long)base);
57 break;
58 }
59}
60
61
62/*
63 * read device ready pin
64 * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
65 */
66static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
67{
68 struct nand_chip *this = mtdinfo->priv;
69 ulong rb_gpio_pin;
70
71 /* use the base addr to find out which chip are we dealing with */
72 switch((ulong) this->IO_ADDR_W) {
73 case CFG_NAND0_BASE:
74 rb_gpio_pin = CFG_NAND0_RDY;
75 break;
76 case CFG_NAND1_BASE:
77 rb_gpio_pin = CFG_NAND1_RDY;
78 break;
79 default: /* this should never happen */
80 return 0;
81 break;
82 }
83
Wolfgang Denkbfc81252006-03-06 13:03:37 +010084 if (in32(GPIO0_IR) & rb_gpio_pin)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010085 return 1;
86 return 0;
87}
88
89
90/*
91 * Board-specific NAND initialization. The following members of the
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010092 * argument are board-specific (per include/linux/mtd/nand.h):
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010093 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
94 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
95 * - hwcontrol: hardwarespecific function for accesing control-lines
96 * - dev_ready: hardwarespecific function for accesing device ready/busy line
97 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
98 * only be provided if a hardware ECC is available
99 * - eccmode: mode of ecc, see defines
100 * - chip_delay: chip dependent delay for transfering data from array to
101 * read regs (tR)
102 * - options: various chip options. They can partly be set to inform
103 * nand_scan about special functionality. See the defines for further
104 * explanation
105 * Members with a "?" were not set in the merged testing-NAND branch,
106 * so they are not set here either.
107 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100108int board_nand_init(struct nand_chip *nand)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100109{
110
111 nand->hwcontrol = ppchameleonevb_hwcontrol;
112 nand->dev_ready = ppchameleonevb_device_ready;
113 nand->eccmode = NAND_ECC_SOFT;
114 nand->chip_delay = NAND_BIG_DELAY_US;
115 nand->options = NAND_SAMSUNG_LP_OPTIONS;
Heiko Schocherfa230442006-12-21 17:17:02 +0100116 return 0;
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100117}
Jon Loeligerb9307262007-07-09 18:24:55 -0500118#endif