blob: d432d995a7ae7b11306e544d65935af3b26f5db1 [file] [log] [blame]
Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
3 * (C) Copyright 2007 DENX Software Engineering
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * CPU specific code for the MPC512x family.
26 *
27 * Derived from the MPC83xx code.
28 */
29
30#include <common.h>
31#include <command.h>
32#include <mpc512x.h>
Ben Warrena0aad082008-08-31 10:36:38 -070033#include <netdev.h>
Rafal Jaworowski8993e542007-07-27 14:43:59 +020034#include <asm/processor.h>
35
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +010036#if defined(CONFIG_OF_LIBFDT)
37#include <fdt_support.h>
38#endif
39
Rafal Jaworowski8993e542007-07-27 14:43:59 +020040DECLARE_GLOBAL_DATA_PTR;
41
42int checkcpu (void)
43{
44 volatile immap_t *immr = (immap_t *) CFG_IMMR;
45 ulong clock = gd->cpu_clk;
46 u32 pvr = get_pvr ();
47 u32 spridr = immr->sysconf.spridr;
48 char buf[32];
49
Wolfgang Denk77d19a82007-08-12 21:34:34 +020050 puts ("CPU: ");
Rafal Jaworowski8993e542007-07-27 14:43:59 +020051
52 switch (spridr & 0xffff0000) {
53 case SPR_5121E:
54 puts ("MPC5121e ");
55 break;
56 default:
57 printf ("Unknown part ID %08x ", spridr & 0xffff0000);
58 }
59 printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
60
61 switch (pvr & 0xffff0000) {
62 case PVR_E300C4:
63 puts ("e300c4 ");
64 break;
65 default:
66 puts ("unknown ");
67 }
68 printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock),
69 gd->csb_clk / 1000000);
70 return 0;
71}
72
73
74int
75do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
76{
77 ulong msr;
78 volatile immap_t *immap = (immap_t *) CFG_IMMR;
79
80 /* Interrupts and MMU off */
81 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
82
83 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
84 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
85
86 /*
87 * Enable Reset Control Reg - "RSTE" is the magic word that let us go
88 */
89 immap->reset.rpr = 0x52535445;
90
91 /* Verify Reset Control Reg is enabled */
92 while (!((immap->reset.rcer) & RCER_CRE))
93 ;
94
95 printf ("Resetting the board.\n");
96 udelay(200);
97
98 /* Perform reset */
99 immap->reset.rcr = RCR_SWHR;
100
101 /* Unreached... */
102 return 1;
103}
104
105
106/*
107 * Get timebase clock frequency (like cpu_clk in Hz)
108 */
109unsigned long get_tbclk (void)
110{
111 ulong tbclk;
112
113 tbclk = (gd->bus_clk + 3L) / 4L;
114
115 return tbclk;
116}
117
118
119#if defined(CONFIG_WATCHDOG)
120void watchdog_reset (void)
121{
122 int re_enable = disable_interrupts ();
123
124 /* Reset watchdog */
125 volatile immap_t *immr = (immap_t *) CFG_IMMR;
126 immr->wdt.swsrr = 0x556c;
127 immr->wdt.swsrr = 0xaa39;
128
129 if (re_enable)
130 enable_interrupts ();
131}
132#endif
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100133
134#ifdef CONFIG_OF_LIBFDT
John Rigbyef11df62008-08-05 17:38:57 -0600135
136#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
137/*
138 * fdt setup for old device trees
139 * fix up
140 * cpu clocks
141 * soc clocks
142 * ethernet addresses
143 */
144static void old_ft_cpu_setup(void *blob, bd_t *bd)
145{
146 /*
147 * avoid fixing up by path because that
148 * produces scary error messages
149 */
150
151 /*
152 * old device trees have ethernet nodes with
153 * device_type = "network"
154 */
155 do_fixup_by_prop(blob, "device_type", "network", 8,
156 "local-mac-address", bd->bi_enetaddr, 6, 0);
157 do_fixup_by_prop(blob, "device_type", "network", 8,
158 "address", bd->bi_enetaddr, 6, 0);
159 /*
160 * old device trees have soc nodes with
161 * device_type = "soc"
162 */
163 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
164 "bus-frequency", bd->bi_ipsfreq, 0);
165}
166#endif
167
168static void ft_clock_setup(void *blob, bd_t *bd)
169{
John Rigbyef11df62008-08-05 17:38:57 -0600170 char *cpu_path = "/cpus/" OF_CPU;
John Rigbyef11df62008-08-05 17:38:57 -0600171
172 /*
173 * fixup cpu clocks using path
174 */
175 do_fixup_by_path_u32(blob, cpu_path,
176 "timebase-frequency", OF_TBCLK, 1);
177 do_fixup_by_path_u32(blob, cpu_path,
178 "bus-frequency", bd->bi_busfreq, 1);
179 do_fixup_by_path_u32(blob, cpu_path,
180 "clock-frequency", bd->bi_intfreq, 1);
181 /*
182 * fixup soc clocks using compatible
183 */
184 do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
185 "bus-frequency", bd->bi_ipsfreq, 1);
186}
187
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100188void ft_cpu_setup(void *blob, bd_t *bd)
189{
John Rigbyef11df62008-08-05 17:38:57 -0600190#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
191 old_ft_cpu_setup(blob, bd);
192#endif
193 ft_clock_setup(blob, bd);
194#ifdef CONFIG_HAS_ETH0
Kumar Galaba37aa02008-08-19 15:41:18 -0500195 fdt_fixup_ethernet(blob);
John Rigbyef11df62008-08-05 17:38:57 -0600196#endif
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100197}
198#endif
Ben Warrena0aad082008-08-31 10:36:38 -0700199
200#ifdef CONFIG_MPC512x_FEC
201/* Default initializations for FEC controllers. To override,
202 * create a board-specific function called:
203 * int board_eth_init(bd_t *bis)
204 */
205
206int cpu_eth_init(bd_t *bis)
207{
208 return mpc512x_fec_initialize(bis);
209}
210#endif