blob: 57652be293eb5e907ca9d60eb9e4cb9ffe8dc4ee [file] [log] [blame]
Mike Frysingerd9a5d112008-10-12 20:59:12 -04001/*
2 * video.c - run splash screen on lcd
3 *
4 * Copyright (c) 2007-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <stdarg.h>
10#include <common.h>
11#include <config.h>
12#include <malloc.h>
13#include <asm/blackfin.h>
14#include <asm/mach-common/bits/dma.h>
15#include <i2c.h>
16#include <linux/types.h>
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +020017#include <stdio_dev.h>
Mike Frysingerd9a5d112008-10-12 20:59:12 -040018
Mike Frysingerd9a5d112008-10-12 20:59:12 -040019#define DMA_SIZE16 2
20
21#include <asm/mach-common/bits/ppi.h>
22#include <asm/mach-common/bits/timer.h>
23
24#include <asm/bfin_logo_230x230.h>
25
26#define LCD_X_RES 320 /* Horizontal Resolution */
27#define LCD_Y_RES 240 /* Vertical Resolution */
28#define LCD_BPP 24 /* Bit Per Pixel */
29#define LCD_PIXEL_SIZE (LCD_BPP / 8)
30
31#define DMA_BUS_SIZE 16
32#define LCD_CLK (12*1000*1000) /* 12MHz */
33
34#define CLOCKS_PER_PIX 3
35
36/* HS and VS timing parameters (all in number of PPI clk ticks) */
37#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
38#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */
39#define H_PULSE 90 /* HS pulse width */
40#define H_START 204 /* first valid pixel */
41
42#define U_LINE 1 /* Blanking Lines */
43
44#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
45#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
46#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
47
48#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
49
50#define PPI_TX_MODE 0x2
51#define PPI_XFER_TYPE_11 0xC
52#define PPI_PORT_CFG_01 0x10
53#define PPI_PACK_EN 0x80
54#define PPI_POLS_1 0x8000
55
56/* enable and disable PPI functions */
57void EnablePPI(void)
58{
59 *pPPI_CONTROL |= PORT_EN;
60}
61
62void DisablePPI(void)
63{
64 *pPPI_CONTROL &= ~PORT_EN;
65}
66
67void Init_Ports(void)
68{
69 *pPORTF_MUX &= ~PORT_x_MUX_0_MASK;
70 *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1;
71 *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
72
73 *pPORTG_MUX &= ~PORT_x_MUX_1_MASK;
74 *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1;
75 *pPORTG_FER |= PG5;
76}
77
78void Init_PPI(void)
79{
80
81 *pPPI_DELAY = H_START;
82 *pPPI_COUNT = (H_ACTPIX-1);
83 *pPPI_FRAME = 0;
84
85 /* PPI control, to be replaced with definitions */
86 *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
87 PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
88 PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
89 PPI_PACK_EN | /* packing enabled PACK_EN */
90 PPI_POLS_1; /* faling edge syncs POLS */
91}
92
93void Init_DMA(void *dst)
94{
95 *pDMA0_START_ADDR = dst;
96
97 /* X count */
98 *pDMA0_X_COUNT = H_ACTPIX / 2;
99 *pDMA0_X_MODIFY = DMA_BUS_SIZE / 8;
100
101 /* Y count */
102 *pDMA0_Y_COUNT = V_LINES;
103 *pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8;
104
105 /* DMA Config */
106 *pDMA0_CONFIG =
107 WDSIZE_16 | /* 16 bit DMA */
108 DMA2D | /* 2D DMA */
109 FLOW_AUTO; /* autobuffer mode */
110}
111
112
113void EnableDMA(void)
114{
115 *pDMA0_CONFIG |= DMAEN;
116}
117
118void DisableDMA(void)
119{
120 *pDMA0_CONFIG &= ~DMAEN;
121}
122
123
124/* Init TIMER0 as Frame Sync 1 generator */
125void InitTIMER0(void)
126{
127 *pTIMER_DISABLE |= TIMDIS0; /* disable Timer */
128 SSYNC();
129 *pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */
130 SSYNC();
131
132 *pTIMER0_PERIOD = H_PERIOD;
133 SSYNC();
134 *pTIMER0_WIDTH = H_PULSE;
135 SSYNC();
136
137 *pTIMER0_CONFIG = PWM_OUT |
138 PERIOD_CNT |
139 TIN_SEL |
140 CLK_SEL |
141 EMU_RUN;
142 SSYNC();
143}
144
145void EnableTIMER0(void)
146{
147 *pTIMER_ENABLE |= TIMEN0;
148 SSYNC();
149}
150
151void DisableTIMER0(void)
152{
153 *pTIMER_DISABLE |= TIMDIS0;
154 SSYNC();
155}
156
157
158void InitTIMER1(void)
159{
160 *pTIMER_DISABLE |= TIMDIS1; /* disable Timer */
161 SSYNC();
162 *pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */
163 SSYNC();
164
165
166 *pTIMER1_PERIOD = V_PERIOD;
167 SSYNC();
168 *pTIMER1_WIDTH = V_PULSE;
169 SSYNC();
170
171 *pTIMER1_CONFIG = PWM_OUT |
172 PERIOD_CNT |
173 TIN_SEL |
174 CLK_SEL |
175 EMU_RUN;
176 SSYNC();
177}
178
179void EnableTIMER1(void)
180{
181 *pTIMER_ENABLE |= TIMEN1;
182 SSYNC();
183}
184
185void DisableTIMER1(void)
186{
187 *pTIMER_DISABLE |= TIMDIS1;
188 SSYNC();
189}
190
191int video_init(void *dst)
192{
193
194 Init_Ports();
195 Init_DMA(dst);
196 EnableDMA();
197 InitTIMER0();
198 InitTIMER1();
199 Init_PPI();
200 EnablePPI();
201
202 /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
203 EnableTIMER1();
204 /* Add Some Delay ... */
205 SSYNC();
206 SSYNC();
207 SSYNC();
208 SSYNC();
209
210 /* now start frame sync 1 */
211 EnableTIMER0();
212
213 return 0;
214}
215
216static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
217{
218 if (dcache_status())
219 blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
220
221 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
222
223 /* Setup destination start address */
224 bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
225 + (y * LCD_X_RES * LCD_PIXEL_SIZE));
226 /* Setup destination xcount */
227 bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
228 /* Setup destination xmodify */
229 bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
230
231 /* Setup destination ycount */
232 bfin_write_MDMA_D0_Y_COUNT(logo->height);
233 /* Setup destination ymodify */
234 bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
235
236
237 /* Setup Source start address */
238 bfin_write_MDMA_S0_START_ADDR(logo->data);
239 /* Setup Source xcount */
240 bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
241 /* Setup Source xmodify */
242 bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
243
244 /* Setup Source ycount */
245 bfin_write_MDMA_S0_Y_COUNT(logo->height);
246 /* Setup Source ymodify */
247 bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
248
249
250 /* Enable source DMA */
251 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
252 SSYNC();
253 bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
254
255 while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
256
257 bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
258 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
259
260}
261
262void video_putc(const char c)
263{
264}
265
266void video_puts(const char *s)
267{
268}
269
270int drv_video_init(void)
271{
272 int error, devices = 1;
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200273 struct stdio_dev videodev;
Mike Frysingerd9a5d112008-10-12 20:59:12 -0400274
275 u8 *dst;
276 u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
277
278 dst = malloc(fbmem_size);
279
280 if (dst == NULL) {
281 printf("Failed to alloc FB memory\n");
282 return -1;
283 }
284
285#ifdef EASYLOGO_ENABLE_GZIP
286 unsigned char *data = EASYLOGO_DECOMP_BUFFER;
287 unsigned long src_len = EASYLOGO_ENABLE_GZIP;
288 if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
289 puts("Failed to decompress logo\n");
290 free(dst);
291 return -1;
292 }
293 bfin_logo.data = data;
294#endif
295
296 memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
297
298 dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
299 (LCD_X_RES - bfin_logo.width) / 2,
300 (LCD_Y_RES - bfin_logo.height) / 2);
301
302 video_init(dst); /* Video initialization */
303
304 memset(&videodev, 0, sizeof(videodev));
305
306 strcpy(videodev.name, "video");
307 videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
308 videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
309 videodev.putc = video_putc; /* 'putc' function */
310 videodev.puts = video_puts; /* 'puts' function */
311
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200312 error = stdio_register(&videodev);
Mike Frysingerd9a5d112008-10-12 20:59:12 -0400313
314 return (error == 0) ? devices : error;
315}