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Stefan Roese7644f162005-09-22 09:16:57 +02001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkf013dac2005-12-04 00:40:34 +010015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Stefan Roese7644f162005-09-22 09:16:57 +020016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
Matthias Fuchs049216f2009-02-20 10:19:18 +010026#include <asm/io.h>
Stefan Roese7644f162005-09-22 09:16:57 +020027#include <command.h>
28#include <malloc.h>
29
Wolfgang Denkd87080b2006-03-31 18:32:53 +020030DECLARE_GLOBAL_DATA_PTR;
31
Stefan Roese7644f162005-09-22 09:16:57 +020032int board_early_init_f (void)
33{
Stefan Roesed1c3b272009-09-09 16:25:29 +020034 unsigned long CPC0_CR0Reg;
Stefan Roese7644f162005-09-22 09:16:57 +020035
36 /*
Stefan Roese2076d0a2006-01-18 20:03:15 +010037 * Setup GPIO pins
Stefan Roese7644f162005-09-22 09:16:57 +020038 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020039 CPC0_CR0Reg = mfdcr(CPC0_CR0);
40 mtdcr(CPC0_CR0, CPC0_CR0Reg |
Matthias Fuchs049216f2009-02-20 10:19:18 +010041 ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
42 CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
Stefan Roese7644f162005-09-22 09:16:57 +020043
Wolfgang Denkbfc81252006-03-06 13:03:37 +010044 /* set output pins to high */
Matthias Fuchs049216f2009-02-20 10:19:18 +010045 out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP);
Wolfgang Denkbfc81252006-03-06 13:03:37 +010046 /* setup for output (LED=off) */
Matthias Fuchs049216f2009-02-20 10:19:18 +010047 out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
Stefan Roese7644f162005-09-22 09:16:57 +020048
49 /*
50 * IRQ 0-15 405GP internally generated; active high; level sensitive
51 * IRQ 16 405GP internally generated; active low; level sensitive
52 * IRQ 17-24 RESERVED
53 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
54 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
55 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
56 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
57 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
58 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
59 * IRQ 31 (EXT IRQ 6) unused
60 */
Stefan Roese952e7762009-09-24 09:55:50 +020061 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
62 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
63 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
64 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
Stefan Roese7644f162005-09-22 09:16:57 +020065
Stefan Roese952e7762009-09-24 09:55:50 +020066 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
67 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
68 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
Stefan Roese7644f162005-09-22 09:16:57 +020069
70 return 0;
71}
72
Stefan Roese7644f162005-09-22 09:16:57 +020073int misc_init_r (void)
74{
Stefan Roesed1c3b272009-09-09 16:25:29 +020075 unsigned long CPC0_CR0Reg;
Stefan Roese7644f162005-09-22 09:16:57 +020076
77 /* adjust flash start and offset */
78 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
79 gd->bd->bi_flashoffset = 0;
80
81 /*
82 * Select cts (and not dsr) on uart1
83 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020084 CPC0_CR0Reg = mfdcr(CPC0_CR0);
85 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
Stefan Roese7644f162005-09-22 09:16:57 +020086
87 return (0);
88}
89
90
91/*
92 * Check Board Identity:
93 */
94int checkboard (void)
95{
Wolfgang Denk77ddac92005-10-13 16:45:02 +020096 char str[64];
Stefan Roese7644f162005-09-22 09:16:57 +020097 int i = getenv_r ("serial#", str, sizeof(str));
98
99 puts ("Board: ");
100
101 if (i == -1) {
102 puts ("### No HW ID - assuming CPCI2DP");
103 } else {
104 puts(str);
105 }
106
107 printf(" (Ver 1.0)");
108
109 putc ('\n');
110
111 return 0;
112}
113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#if defined(CONFIG_SYS_EEPROM_WREN)
Stefan Roese7644f162005-09-22 09:16:57 +0200115/* Input: <dev_addr> I2C address of EEPROM device to enable.
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100116 * <state> -1: deliver current state
117 * 0: disable write
Stefan Roese7644f162005-09-22 09:16:57 +0200118 * 1: enable write
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100119 * Returns: -1: wrong device address
120 * 0: dis-/en- able done
Stefan Roese7644f162005-09-22 09:16:57 +0200121 * 0/1: current state if <state> was -1.
122 */
123int eeprom_write_enable (unsigned dev_addr, int state) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
Stefan Roese7644f162005-09-22 09:16:57 +0200125 return -1;
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100126 } else {
Stefan Roese7644f162005-09-22 09:16:57 +0200127 switch (state) {
128 case 1:
129 /* Enable write access, clear bit GPIO_SINT2. */
Matthias Fuchs049216f2009-02-20 10:19:18 +0100130 out_be32((void *)GPIO0_OR,
131 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
Stefan Roese7644f162005-09-22 09:16:57 +0200132 state = 0;
133 break;
134 case 0:
135 /* Disable write access, set bit GPIO_SINT2. */
Matthias Fuchs049216f2009-02-20 10:19:18 +0100136 out_be32((void *)GPIO0_OR,
137 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
Stefan Roese7644f162005-09-22 09:16:57 +0200138 state = 0;
139 break;
140 default:
141 /* Read current status back. */
Matthias Fuchs049216f2009-02-20 10:19:18 +0100142 state = (0 == (in_be32((void *)GPIO0_OR) &
143 CONFIG_SYS_EEPROM_WP));
Stefan Roese7644f162005-09-22 09:16:57 +0200144 break;
145 }
146 }
147 return state;
148}
149#endif
150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#if defined(CONFIG_SYS_EEPROM_WREN)
Stefan Roese7644f162005-09-22 09:16:57 +0200152int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
153{
154 int query = argc == 1;
155 int state = 0;
156
157 if (query) {
158 /* Query write access state. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
Stefan Roese7644f162005-09-22 09:16:57 +0200160 if (state < 0) {
161 puts ("Query of write access state failed.\n");
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100162 } else {
Stefan Roese7644f162005-09-22 09:16:57 +0200163 printf ("Write access for device 0x%0x is %sabled.\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
Stefan Roese7644f162005-09-22 09:16:57 +0200165 state = 0;
166 }
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100167 } else {
Stefan Roese7644f162005-09-22 09:16:57 +0200168 if ('0' == argv[1][0]) {
169 /* Disable write access. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100171 } else {
Stefan Roese7644f162005-09-22 09:16:57 +0200172 /* Enable write access. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
Stefan Roese7644f162005-09-22 09:16:57 +0200174 }
175 if (state < 0) {
176 puts ("Setup of write access state failed.\n");
177 }
178 }
179
180 return state;
181}
182
183U_BOOT_CMD(
Stefan Roese2076d0a2006-01-18 20:03:15 +0100184 eepwren, 2, 0, do_eep_wren,
Peter Tyser2fb26042009-01-27 18:03:12 -0600185 "Enable / disable / query EEPROM write access",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200186 ""
187);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */