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wdenk507bbe32004-04-18 21:13:41 +00001/*
Michal Simekcfc67112007-03-11 13:48:24 +01002 * (C) Copyright 2007 Michal Simek
wdenk507bbe32004-04-18 21:13:41 +00003 * (C) Copyright 2004 Atmark Techno, Inc.
4 *
Michal Simekcfc67112007-03-11 13:48:24 +01005 * Michal SIMEK <monstr@monstr.eu>
wdenk507bbe32004-04-18 21:13:41 +00006 * Yasushi SHOJI <yashi@atmark-techno.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Michal Simekcfc67112007-03-11 13:48:24 +010018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk507bbe32004-04-18 21:13:41 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
28
29 .text
30 .global _start
31_start:
Michal Simekcfc67112007-03-11 13:48:24 +010032 mts rmsr, r0 /* disable cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033 addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
Michal Simek17980492007-03-26 01:39:07 +020034 addi r1, r1, -4 /* Decrement SP to top of memory */
Michal Simekcfc67112007-03-11 13:48:24 +010035 /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
Michal Simek07319332007-09-24 00:19:48 +020036 addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
Michal Simekcfc67112007-03-11 13:48:24 +010037 swi r6, r0, 0x0 /* reset address */
38 swi r6, r0, 0x8 /* user vector exception */
39 swi r6, r0, 0x10 /* interrupt */
40 swi r6, r0, 0x20 /* hardware exception */
wdenk507bbe32004-04-18 21:13:41 +000041
Michal Simek07319332007-09-24 00:19:48 +020042 addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
Michal Simekcfc67112007-03-11 13:48:24 +010043 swi r6, r0, 0x4 /* reset address */
44 swi r6, r0, 0xC /* user vector exception */
45 swi r6, r0, 0x14 /* interrupt */
46 swi r6, r0, 0x24 /* hardware exception */
wdenk507bbe32004-04-18 21:13:41 +000047
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#ifdef CONFIG_SYS_RESET_ADDRESS
Michal Simekcfc67112007-03-11 13:48:24 +010049 /* reset address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 addik r6, r0, CONFIG_SYS_RESET_ADDRESS
Michal Simekcfc67112007-03-11 13:48:24 +010051 sw r6, r1, r0
52 lhu r7, r1, r0
53 shi r7, r0, 0x2
54 shi r6, r0, 0x6
Wolfgang Denk31c98a82007-04-04 02:09:30 +020055/*
Michal Simek17980492007-03-26 01:39:07 +020056 * Copy U-Boot code to TEXT_BASE
57 * solve problem with sbrk_base
58 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#if (CONFIG_SYS_RESET_ADDRESS != TEXT_BASE)
Michal Simek17980492007-03-26 01:39:07 +020060 addi r4, r0, __end
61 addi r5, r0, __text_start
62 rsub r4, r5, r4 /* size = __end - __text_start */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 addi r6, r0, CONFIG_SYS_RESET_ADDRESS /* source address */
Michal Simek17980492007-03-26 01:39:07 +020064 addi r7, r0, 0 /* counter */
654:
66 lw r8, r6, r7
67 sw r8, r5, r7
68 addi r7, r7, 0x4
69 cmp r8, r4, r7
70 blti r8, 4b
71#endif
Michal Simekcfc67112007-03-11 13:48:24 +010072#endif
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#ifdef CONFIG_SYS_USR_EXCEP
Michal Simekcfc67112007-03-11 13:48:24 +010075 /* user_vector_exception */
76 addik r6, r0, _exception_handler
77 sw r6, r1, r0
78 lhu r7, r1, r0
79 shi r7, r0, 0xa
80 shi r6, r0, 0xe
81#endif
82
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#ifdef CONFIG_SYS_INTC_0
Michal Simekcfc67112007-03-11 13:48:24 +010084 /* interrupt_handler */
85 addik r6, r0, _interrupt_handler
86 sw r6, r1, r0
87 lhu r7, r1, r0
88 shi r7, r0, 0x12
89 shi r6, r0, 0x16
90#endif
91
92 /* hardware exception */
93 addik r6, r0, _hw_exception_handler
94 sw r6, r1, r0
95 lhu r7, r1, r0
96 shi r7, r0, 0x22
97 shi r6, r0, 0x26
98
99 /* enable instruction and data cache */
100 mfs r12, rmsr
101 ori r12, r12, 0xa0
102 mts rmsr, r12
103
Michal Simek17980492007-03-26 01:39:07 +0200104clear_bss:
105 /* clear BSS segments */
106 addi r5, r0, __bss_start
107 addi r4, r0, __bss_end
108 cmp r6, r5, r4
109 beqi r6, 3f
1102:
111 swi r0, r5, 0 /* write zero to loc */
112 addi r5, r5, 4 /* increment to next loc */
113 cmp r6, r5, r4 /* check if we have reach the end */
114 bnei r6, 2b
1153: /* jumping to board_init */
wdenk507bbe32004-04-18 21:13:41 +0000116 brai board_init
wdenk507bbe32004-04-18 21:13:41 +00001171: bri 1b
Michal Simek06436312007-04-21 21:02:40 +0200118
119/*
120 * Read 16bit little endian
121 */
122 .text
123 .global in16
124 .ent in16
125 .align 2
126in16: lhu r3, r0, r5
127 bslli r4, r3, 8
128 bsrli r3, r3, 8
129 andi r4, r4, 0xffff
130 or r3, r3, r4
131 rtsd r15, 8
132 sext16 r3, r3
133 .end in16
134
135/*
136 * Write 16bit little endian
137 * first parameter(r5) - address, second(r6) - short value
138 */
139 .text
140 .global out16
141 .ent out16
142 .align 2
143out16: bslli r3, r6, 8
144 bsrli r6, r6, 8
145 andi r3, r3, 0xffff
146 or r3, r3, r6
147 sh r3, r0, r5
148 rtsd r15, 8
149 or r0, r0, r0
150 .end out16