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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +05302/*
Jagan Teki86e99b92015-09-02 11:39:45 +05303 * (C) Copyright 2013 Xilinx, Inc.
Jagan Tekib1c82da2015-06-27 00:51:31 +05304 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +05305 *
6 * Xilinx Zynq PS SPI controller driver (master mode only)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +05307 */
8
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +05309#include <common.h>
Jagan Tekib1c82da2015-06-27 00:51:31 +053010#include <dm.h>
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053011#include <malloc.h>
12#include <spi.h>
Simon Glass10453152019-11-14 12:57:30 -070013#include <time.h>
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053014#include <asm/io.h>
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053015
Jagan Tekicdc9dd02015-06-27 00:51:34 +053016DECLARE_GLOBAL_DATA_PTR;
17
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053018/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
Jagan Teki736b4df2015-10-22 20:40:16 +053019#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
20#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
Jagan Teki9cf2ffb2015-10-22 21:06:37 +053021#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
22#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
Jagan Teki736b4df2015-10-22 20:40:16 +053023#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
24#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
25#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
26#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
27#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
Jagan Teki9cf2ffb2015-10-22 21:06:37 +053028#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
Jagan Teki736b4df2015-10-22 20:40:16 +053029#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053030
Jagan Teki46ab8a62015-08-17 18:25:03 +053031#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
32#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
33#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
34
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053035#define ZYNQ_SPI_FIFO_DEPTH 128
36#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
37#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
38#endif
39
40/* zynq spi register set */
41struct zynq_spi_regs {
42 u32 cr; /* 0x00 */
43 u32 isr; /* 0x04 */
44 u32 ier; /* 0x08 */
45 u32 idr; /* 0x0C */
46 u32 imr; /* 0x10 */
47 u32 enr; /* 0x14 */
48 u32 dr; /* 0x18 */
49 u32 txdr; /* 0x1C */
50 u32 rxdr; /* 0x20 */
51};
52
Jagan Tekib1c82da2015-06-27 00:51:31 +053053
54/* zynq spi platform data */
55struct zynq_spi_platdata {
56 struct zynq_spi_regs *regs;
57 u32 frequency; /* input frequency */
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053058 u32 speed_hz;
Moritz Fischerac6991f2016-12-08 12:11:09 -080059 uint deactivate_delay_us; /* Delay to wait after deactivate */
60 uint activate_delay_us; /* Delay to wait after activate */
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053061};
62
Jagan Tekib1c82da2015-06-27 00:51:31 +053063/* zynq spi priv */
64struct zynq_spi_priv {
65 struct zynq_spi_regs *regs;
Jagan Teki19126992015-08-17 18:31:39 +053066 u8 cs;
Jagan Tekib1c82da2015-06-27 00:51:31 +053067 u8 mode;
Moritz Fischerac6991f2016-12-08 12:11:09 -080068 ulong last_transaction_us; /* Time of last transaction end */
Jagan Tekib1c82da2015-06-27 00:51:31 +053069 u8 fifo_depth;
70 u32 freq; /* required frequency */
71};
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053072
Jagan Tekib1c82da2015-06-27 00:51:31 +053073static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053074{
Jagan Tekib1c82da2015-06-27 00:51:31 +053075 struct zynq_spi_platdata *plat = bus->platdata;
Jagan Tekicdc9dd02015-06-27 00:51:34 +053076 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -070077 int node = dev_of_offset(bus);
Jagan Tekib1c82da2015-06-27 00:51:31 +053078
Simon Glassa821c4a2017-05-17 17:18:05 -060079 plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus);
Jagan Tekicdc9dd02015-06-27 00:51:34 +053080
81 /* FIXME: Use 250MHz as a suitable default */
82 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
83 250000000);
Moritz Fischerac6991f2016-12-08 12:11:09 -080084 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
85 "spi-deactivate-delay", 0);
86 plat->activate_delay_us = fdtdec_get_int(blob, node,
87 "spi-activate-delay", 0);
Jagan Tekib1c82da2015-06-27 00:51:31 +053088 plat->speed_hz = plat->frequency / 2;
89
Michal Simek80fd9792015-07-21 07:54:11 +020090 debug("%s: regs=%p max-frequency=%d\n", __func__,
Jagan Tekicdc9dd02015-06-27 00:51:34 +053091 plat->regs, plat->frequency);
92
Jagan Tekib1c82da2015-06-27 00:51:31 +053093 return 0;
94}
95
96static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
97{
98 struct zynq_spi_regs *regs = priv->regs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053099 u32 confr;
100
101 /* Disable SPI */
Michal Simek5f647c22016-09-01 12:51:27 +0200102 confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
103 writel(~confr, &regs->enr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530104
105 /* Disable Interrupts */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530106 writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530107
108 /* Clear RX FIFO */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530109 while (readl(&regs->isr) &
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530110 ZYNQ_SPI_IXR_RXNEMPTY_MASK)
Jagan Tekib1c82da2015-06-27 00:51:31 +0530111 readl(&regs->rxdr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530112
113 /* Clear Interrupts */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530114 writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530115
116 /* Manual slave select and Auto start */
117 confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
118 ZYNQ_SPI_CR_MSTREN_MASK;
119 confr &= ~ZYNQ_SPI_CR_MSA_MASK;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530120 writel(confr, &regs->cr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530121
122 /* Enable SPI */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530123 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530124}
125
Jagan Tekib1c82da2015-06-27 00:51:31 +0530126static int zynq_spi_probe(struct udevice *bus)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530127{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530128 struct zynq_spi_platdata *plat = dev_get_platdata(bus);
129 struct zynq_spi_priv *priv = dev_get_priv(bus);
130
131 priv->regs = plat->regs;
132 priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
133
134 /* init the zynq spi hw */
135 zynq_spi_init_hw(priv);
136
137 return 0;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530138}
139
Jagan Teki19126992015-08-17 18:31:39 +0530140static void spi_cs_activate(struct udevice *dev)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530141{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530142 struct udevice *bus = dev->parent;
Moritz Fischerac6991f2016-12-08 12:11:09 -0800143 struct zynq_spi_platdata *plat = bus->platdata;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530144 struct zynq_spi_priv *priv = dev_get_priv(bus);
145 struct zynq_spi_regs *regs = priv->regs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530146 u32 cr;
147
Moritz Fischerac6991f2016-12-08 12:11:09 -0800148 /* If it's too soon to do another transaction, wait */
149 if (plat->deactivate_delay_us && priv->last_transaction_us) {
150 ulong delay_us; /* The delay completed so far */
151 delay_us = timer_get_us() - priv->last_transaction_us;
152 if (delay_us < plat->deactivate_delay_us)
153 udelay(plat->deactivate_delay_us - delay_us);
154 }
155
Jagan Tekib1c82da2015-06-27 00:51:31 +0530156 clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
157 cr = readl(&regs->cr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530158 /*
159 * CS cal logic: CS[13:10]
160 * xxx0 - cs0
161 * xx01 - cs1
162 * x011 - cs2
163 */
Jagan Teki19126992015-08-17 18:31:39 +0530164 cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530165 writel(cr, &regs->cr);
Moritz Fischerac6991f2016-12-08 12:11:09 -0800166
167 if (plat->activate_delay_us)
168 udelay(plat->activate_delay_us);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530169}
170
Jagan Tekib1c82da2015-06-27 00:51:31 +0530171static void spi_cs_deactivate(struct udevice *dev)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530172{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530173 struct udevice *bus = dev->parent;
Moritz Fischerac6991f2016-12-08 12:11:09 -0800174 struct zynq_spi_platdata *plat = bus->platdata;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530175 struct zynq_spi_priv *priv = dev_get_priv(bus);
176 struct zynq_spi_regs *regs = priv->regs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530177
Jagan Tekib1c82da2015-06-27 00:51:31 +0530178 setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
Moritz Fischerac6991f2016-12-08 12:11:09 -0800179
180 /* Remember time of this transaction so we can honour the bus delay */
181 if (plat->deactivate_delay_us)
182 priv->last_transaction_us = timer_get_us();
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530183}
184
Jagan Tekib1c82da2015-06-27 00:51:31 +0530185static int zynq_spi_claim_bus(struct udevice *dev)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530186{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530187 struct udevice *bus = dev->parent;
188 struct zynq_spi_priv *priv = dev_get_priv(bus);
189 struct zynq_spi_regs *regs = priv->regs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530190
Jagan Tekib1c82da2015-06-27 00:51:31 +0530191 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530192
193 return 0;
194}
195
Jagan Tekib1c82da2015-06-27 00:51:31 +0530196static int zynq_spi_release_bus(struct udevice *dev)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530197{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530198 struct udevice *bus = dev->parent;
199 struct zynq_spi_priv *priv = dev_get_priv(bus);
200 struct zynq_spi_regs *regs = priv->regs;
Michal Simek5f647c22016-09-01 12:51:27 +0200201 u32 confr;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530202
Michal Simek5f647c22016-09-01 12:51:27 +0200203 confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
204 writel(~confr, &regs->enr);
Jagan Tekib1c82da2015-06-27 00:51:31 +0530205
206 return 0;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530207}
208
Jagan Tekib1c82da2015-06-27 00:51:31 +0530209static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
210 const void *dout, void *din, unsigned long flags)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530211{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530212 struct udevice *bus = dev->parent;
213 struct zynq_spi_priv *priv = dev_get_priv(bus);
214 struct zynq_spi_regs *regs = priv->regs;
215 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530216 u32 len = bitlen / 8;
217 u32 tx_len = len, rx_len = len, tx_tvl;
218 const u8 *tx_buf = dout;
219 u8 *rx_buf = din, buf;
220 u32 ts, status;
221
222 debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
Jagan Tekib1c82da2015-06-27 00:51:31 +0530223 bus->seq, slave_plat->cs, bitlen, len, flags);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530224
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530225 if (bitlen % 8) {
226 debug("spi_xfer: Non byte aligned SPI transfer\n");
227 return -1;
228 }
229
Jagan Teki19126992015-08-17 18:31:39 +0530230 priv->cs = slave_plat->cs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530231 if (flags & SPI_XFER_BEGIN)
Jagan Teki19126992015-08-17 18:31:39 +0530232 spi_cs_activate(dev);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530233
234 while (rx_len > 0) {
235 /* Write the data into TX FIFO - tx threshold is fifo_depth */
236 tx_tvl = 0;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530237 while ((tx_tvl < priv->fifo_depth) && tx_len) {
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530238 if (tx_buf)
239 buf = *tx_buf++;
240 else
241 buf = 0;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530242 writel(buf, &regs->txdr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530243 tx_len--;
244 tx_tvl++;
245 }
246
247 /* Check TX FIFO completion */
248 ts = get_timer(0);
Jagan Tekib1c82da2015-06-27 00:51:31 +0530249 status = readl(&regs->isr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530250 while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
251 if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
252 printf("spi_xfer: Timeout! TX FIFO not full\n");
253 return -1;
254 }
Jagan Tekib1c82da2015-06-27 00:51:31 +0530255 status = readl(&regs->isr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530256 }
257
258 /* Read the data from RX FIFO */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530259 status = readl(&regs->isr);
Lad, Prabhakard2998282016-07-30 22:28:24 +0100260 while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
Jagan Tekib1c82da2015-06-27 00:51:31 +0530261 buf = readl(&regs->rxdr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530262 if (rx_buf)
263 *rx_buf++ = buf;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530264 status = readl(&regs->isr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530265 rx_len--;
266 }
267 }
268
269 if (flags & SPI_XFER_END)
Jagan Tekib1c82da2015-06-27 00:51:31 +0530270 spi_cs_deactivate(dev);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530271
272 return 0;
273}
Jagan Tekib1c82da2015-06-27 00:51:31 +0530274
275static int zynq_spi_set_speed(struct udevice *bus, uint speed)
276{
277 struct zynq_spi_platdata *plat = bus->platdata;
278 struct zynq_spi_priv *priv = dev_get_priv(bus);
279 struct zynq_spi_regs *regs = priv->regs;
280 uint32_t confr;
281 u8 baud_rate_val = 0;
282
283 if (speed > plat->frequency)
284 speed = plat->frequency;
285
286 /* Set the clock frequency */
287 confr = readl(&regs->cr);
288 if (speed == 0) {
289 /* Set baudrate x8, if the freq is 0 */
290 baud_rate_val = 0x2;
291 } else if (plat->speed_hz != speed) {
Jagan Teki46ab8a62015-08-17 18:25:03 +0530292 while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
Jagan Tekib1c82da2015-06-27 00:51:31 +0530293 ((plat->frequency /
294 (2 << baud_rate_val)) > speed))
295 baud_rate_val++;
296 plat->speed_hz = speed / (2 << baud_rate_val);
297 }
Jagan Tekidda62412015-08-17 18:27:47 +0530298 confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
Jagan Teki46ab8a62015-08-17 18:25:03 +0530299 confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
Jagan Tekib1c82da2015-06-27 00:51:31 +0530300
301 writel(confr, &regs->cr);
302 priv->freq = speed;
303
Jagan Tekia22bba82015-09-08 01:38:50 +0530304 debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
305 priv->regs, priv->freq);
Jagan Tekib1c82da2015-06-27 00:51:31 +0530306
307 return 0;
308}
309
310static int zynq_spi_set_mode(struct udevice *bus, uint mode)
311{
312 struct zynq_spi_priv *priv = dev_get_priv(bus);
313 struct zynq_spi_regs *regs = priv->regs;
314 uint32_t confr;
315
316 /* Set the SPI Clock phase and polarities */
317 confr = readl(&regs->cr);
318 confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
319
Jagan Tekia22bba82015-09-08 01:38:50 +0530320 if (mode & SPI_CPHA)
Jagan Tekib1c82da2015-06-27 00:51:31 +0530321 confr |= ZYNQ_SPI_CR_CPHA_MASK;
Jagan Tekia22bba82015-09-08 01:38:50 +0530322 if (mode & SPI_CPOL)
Jagan Tekib1c82da2015-06-27 00:51:31 +0530323 confr |= ZYNQ_SPI_CR_CPOL_MASK;
324
325 writel(confr, &regs->cr);
326 priv->mode = mode;
327
328 debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
329
330 return 0;
331}
332
333static const struct dm_spi_ops zynq_spi_ops = {
334 .claim_bus = zynq_spi_claim_bus,
335 .release_bus = zynq_spi_release_bus,
336 .xfer = zynq_spi_xfer,
337 .set_speed = zynq_spi_set_speed,
338 .set_mode = zynq_spi_set_mode,
339};
340
341static const struct udevice_id zynq_spi_ids[] = {
Michal Simek40b383f2015-07-22 10:47:33 +0200342 { .compatible = "xlnx,zynq-spi-r1p6" },
Michal Simek23ef5ae2015-12-07 13:06:54 +0100343 { .compatible = "cdns,spi-r1p6" },
Jagan Tekib1c82da2015-06-27 00:51:31 +0530344 { }
345};
346
347U_BOOT_DRIVER(zynq_spi) = {
348 .name = "zynq_spi",
349 .id = UCLASS_SPI,
350 .of_match = zynq_spi_ids,
351 .ops = &zynq_spi_ops,
352 .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
353 .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
354 .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
355 .probe = zynq_spi_probe,
356};