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Shengzhou Liuc4d0e812013-11-22 17:39:11 +08001/*
2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
Shengzhou Liu254887a2014-02-21 13:16:19 +08008 * T2080/T2081 QDS board configuration file
Shengzhou Liuc4d0e812013-11-22 17:39:11 +08009 */
10
Shengzhou Liu254887a2014-02-21 13:16:19 +080011#ifndef __T208xQDS_H
12#define __T208xQDS_H
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080013
Shengzhou Liufb536872014-07-23 15:54:16 +080014#define CONFIG_DISPLAY_BOARDINFO
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080015#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
16#define CONFIG_MMC
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080017#define CONFIG_USB_EHCI
Shengzhou Liu254887a2014-02-21 13:16:19 +080018#if defined(CONFIG_PPC_T2080)
19#define CONFIG_T2080QDS
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080020#define CONFIG_FSL_SATA_V2
21#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
22#define CONFIG_SRIO1 /* SRIO port 1 */
23#define CONFIG_SRIO2 /* SRIO port 2 */
Shengzhou Liu254887a2014-02-21 13:16:19 +080024#elif defined(CONFIG_PPC_T2081)
25#define CONFIG_T2081QDS
26#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080027
28/* High Level Configuration Options */
29#define CONFIG_PHYS_64BIT
30#define CONFIG_BOOKE
31#define CONFIG_E500 /* BOOKE e500 family */
32#define CONFIG_E500MC /* BOOKE e500mc family */
33#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080034#define CONFIG_MP /* support multiple processors */
35#define CONFIG_ENABLE_36BIT_PHYS
36
37#ifdef CONFIG_PHYS_64BIT
38#define CONFIG_ADDR_MAP 1
39#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
40#endif
41
42#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
43#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
44#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053045#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080046#define CONFIG_FSL_LAW /* Use common FSL init code */
47#define CONFIG_ENV_OVERWRITE
48
49#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090050#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080051#if defined(CONFIG_PPC_T2080)
Masahiro Yamadae4536f82014-03-11 11:05:16 +090052#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080053#elif defined(CONFIG_PPC_T2081)
Masahiro Yamadae4536f82014-03-11 11:05:16 +090054#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080055#endif
Shengzhou Liub19e2882014-04-18 16:43:39 +080056
Shengzhou Liub19e2882014-04-18 16:43:39 +080057#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
58#define CONFIG_SPL_ENV_SUPPORT
59#define CONFIG_SPL_SERIAL_SUPPORT
60#define CONFIG_SPL_FLUSH_IMAGE
61#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
62#define CONFIG_SPL_LIBGENERIC_SUPPORT
63#define CONFIG_SPL_LIBCOMMON_SUPPORT
64#define CONFIG_SPL_I2C_SUPPORT
65#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
66#define CONFIG_FSL_LAW /* Use common FSL init code */
67#define CONFIG_SYS_TEXT_BASE 0x00201000
68#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
69#define CONFIG_SPL_PAD_TO 0x40000
70#define CONFIG_SPL_MAX_SIZE 0x28000
71#define RESET_VECTOR_OFFSET 0x27FFC
72#define BOOT_PAGE_OFFSET 0x27000
73#ifdef CONFIG_SPL_BUILD
74#define CONFIG_SPL_SKIP_RELOCATE
75#define CONFIG_SPL_COMMON_INIT_DDR
76#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
77#define CONFIG_SYS_NO_FLASH
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080078#endif
79
Shengzhou Liub19e2882014-04-18 16:43:39 +080080#ifdef CONFIG_NAND
81#define CONFIG_SPL_NAND_SUPPORT
82#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
83#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
84#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
85#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
86#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
87#define CONFIG_SPL_NAND_BOOT
88#endif
89
90#ifdef CONFIG_SPIFLASH
91#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
92#define CONFIG_SPL_SPI_SUPPORT
93#define CONFIG_SPL_SPI_FLASH_SUPPORT
94#define CONFIG_SPL_SPI_FLASH_MINIMAL
95#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
96#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
97#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
98#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
99#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
100#ifndef CONFIG_SPL_BUILD
101#define CONFIG_SYS_MPC85XX_NO_RESETVEC
102#endif
103#define CONFIG_SPL_SPI_BOOT
104#endif
105
106#ifdef CONFIG_SDCARD
107#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
108#define CONFIG_SPL_MMC_SUPPORT
109#define CONFIG_SPL_MMC_MINIMAL
110#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
111#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
112#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
113#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
114#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
115#ifndef CONFIG_SPL_BUILD
116#define CONFIG_SYS_MPC85XX_NO_RESETVEC
117#endif
118#define CONFIG_SPL_MMC_BOOT
119#endif
120
121#endif /* CONFIG_RAMBOOT_PBL */
122
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800123#define CONFIG_SRIO_PCIE_BOOT_MASTER
124#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
125/* Set 1M boot space */
126#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
127#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
128 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
129#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
130#define CONFIG_SYS_NO_FLASH
131#endif
132
133#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530134#define CONFIG_SYS_TEXT_BASE 0xeff40000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800135#endif
136
137#ifndef CONFIG_RESET_VECTOR_ADDRESS
138#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
139#endif
140
141/*
142 * These can be toggled for performance analysis, otherwise use default.
143 */
144#define CONFIG_SYS_CACHE_STASHING
145#define CONFIG_BTB /* toggle branch predition */
146#define CONFIG_DDR_ECC
147#ifdef CONFIG_DDR_ECC
148#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
149#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
150#endif
151
Shengzhou Liub19e2882014-04-18 16:43:39 +0800152#ifndef CONFIG_SYS_NO_FLASH
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800153#define CONFIG_FLASH_CFI_DRIVER
154#define CONFIG_SYS_FLASH_CFI
155#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
156#endif
157
158#if defined(CONFIG_SPIFLASH)
159#define CONFIG_SYS_EXTRA_ENV_RELOC
160#define CONFIG_ENV_IS_IN_SPI_FLASH
161#define CONFIG_ENV_SPI_BUS 0
162#define CONFIG_ENV_SPI_CS 0
163#define CONFIG_ENV_SPI_MAX_HZ 10000000
164#define CONFIG_ENV_SPI_MODE 0
165#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
166#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
167#define CONFIG_ENV_SECT_SIZE 0x10000
168#elif defined(CONFIG_SDCARD)
169#define CONFIG_SYS_EXTRA_ENV_RELOC
170#define CONFIG_ENV_IS_IN_MMC
171#define CONFIG_SYS_MMC_ENV_DEV 0
172#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liub19e2882014-04-18 16:43:39 +0800173#define CONFIG_ENV_OFFSET (512 * 0x800)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800174#elif defined(CONFIG_NAND)
175#define CONFIG_SYS_EXTRA_ENV_RELOC
176#define CONFIG_ENV_IS_IN_NAND
Shengzhou Liub19e2882014-04-18 16:43:39 +0800177#define CONFIG_ENV_SIZE 0x2000
178#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800179#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
180#define CONFIG_ENV_IS_IN_REMOTE
181#define CONFIG_ENV_ADDR 0xffe20000
182#define CONFIG_ENV_SIZE 0x2000
183#elif defined(CONFIG_ENV_IS_NOWHERE)
184#define CONFIG_ENV_SIZE 0x2000
185#else
186#define CONFIG_ENV_IS_IN_FLASH
187#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
188#define CONFIG_ENV_SIZE 0x2000
189#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
190#endif
191
192#ifndef __ASSEMBLY__
193unsigned long get_board_sys_clk(void);
194unsigned long get_board_ddr_clk(void);
195#endif
196
197#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
198#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
199
200/*
201 * Config the L3 Cache as L3 SRAM
202 */
Shengzhou Liub19e2882014-04-18 16:43:39 +0800203#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
204#define CONFIG_SYS_L3_SIZE (512 << 10)
205#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
206#ifdef CONFIG_RAMBOOT_PBL
207#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
208#endif
209#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
210#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
211#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
212#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800213
214#define CONFIG_SYS_DCSRBAR 0xf0000000
215#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
216
217/* EEPROM */
218#define CONFIG_ID_EEPROM
219#define CONFIG_SYS_I2C_EEPROM_NXID
220#define CONFIG_SYS_EEPROM_BUS_NUM 0
221#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
222#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
223
224/*
225 * DDR Setup
226 */
227#define CONFIG_VERY_BIG_RAM
228#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
229#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shengzhou Liu40483e12014-05-20 12:08:20 +0800230#define CONFIG_DIMM_SLOTS_PER_CTLR 2
231#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
232#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800233#define CONFIG_DDR_SPD
234#define CONFIG_SYS_FSL_DDR3
York Suned9e4e42014-10-27 11:31:32 -0700235#define CONFIG_FSL_DDR_INTERACTIVE
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800236#define CONFIG_SYS_SPD_BUS_NUM 0
237#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
238#define SPD_EEPROM_ADDRESS1 0x51
239#define SPD_EEPROM_ADDRESS2 0x52
240#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
241#define CTRL_INTLV_PREFERED cacheline
242
243/*
244 * IFC Definitions
245 */
246#define CONFIG_SYS_FLASH_BASE 0xe0000000
247#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
248#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
249#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
250 + 0x8000000) | \
251 CSPR_PORT_SIZE_16 | \
252 CSPR_MSEL_NOR | \
253 CSPR_V)
254#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
255#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
256 CSPR_PORT_SIZE_16 | \
257 CSPR_MSEL_NOR | \
258 CSPR_V)
259#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
260/* NOR Flash Timing Params */
261#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
262
263#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
264 FTIM0_NOR_TEADC(0x5) | \
265 FTIM0_NOR_TEAHC(0x5))
266#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
267 FTIM1_NOR_TRAD_NOR(0x1A) |\
268 FTIM1_NOR_TSEQRAD_NOR(0x13))
269#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
270 FTIM2_NOR_TCH(0x4) | \
271 FTIM2_NOR_TWPH(0x0E) | \
272 FTIM2_NOR_TWP(0x1c))
273#define CONFIG_SYS_NOR_FTIM3 0x0
274
275#define CONFIG_SYS_FLASH_QUIET_TEST
276#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
277
278#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
279#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
280#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
281#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
282
283#define CONFIG_SYS_FLASH_EMPTY_INFO
284#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
285 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
286
287#define CONFIG_FSL_QIXIS /* use common QIXIS code */
288#define QIXIS_BASE 0xffdf0000
289#define QIXIS_LBMAP_SWITCH 6
290#define QIXIS_LBMAP_MASK 0x0f
291#define QIXIS_LBMAP_SHIFT 0
292#define QIXIS_LBMAP_DFLTBANK 0x00
293#define QIXIS_LBMAP_ALTBANK 0x04
294#define QIXIS_RST_CTL_RESET 0x83
295#define QIXIS_RST_FORCE_MEM 0x1
296#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
297#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
298#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
299#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
300
301#define CONFIG_SYS_CSPR3_EXT (0xf)
302#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
303 | CSPR_PORT_SIZE_8 \
304 | CSPR_MSEL_GPCM \
305 | CSPR_V)
306#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
307#define CONFIG_SYS_CSOR3 0x0
308/* QIXIS Timing parameters for IFC CS3 */
309#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
310 FTIM0_GPCM_TEADC(0x0e) | \
311 FTIM0_GPCM_TEAHC(0x0e))
312#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
313 FTIM1_GPCM_TRAD(0x3f))
314#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shengzhou Liu6b7679c2014-03-06 15:07:39 +0800315 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800316 FTIM2_GPCM_TWP(0x1f))
317#define CONFIG_SYS_CS3_FTIM3 0x0
318
319/* NAND Flash on IFC */
320#define CONFIG_NAND_FSL_IFC
321#define CONFIG_SYS_NAND_BASE 0xff800000
322#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
323
324#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
325#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
326 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
327 | CSPR_MSEL_NAND /* MSEL = NAND */ \
328 | CSPR_V)
329#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
330
331#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
332 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
333 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
334 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
335 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
336 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
337 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
338
339#define CONFIG_SYS_NAND_ONFI_DETECTION
340
341/* ONFI NAND Flash mode0 Timing Params */
342#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
343 FTIM0_NAND_TWP(0x18) | \
344 FTIM0_NAND_TWCHT(0x07) | \
345 FTIM0_NAND_TWH(0x0a))
346#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
347 FTIM1_NAND_TWBE(0x39) | \
348 FTIM1_NAND_TRR(0x0e) | \
349 FTIM1_NAND_TRP(0x18))
350#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
351 FTIM2_NAND_TREH(0x0a) | \
352 FTIM2_NAND_TWHRE(0x1e))
353#define CONFIG_SYS_NAND_FTIM3 0x0
354
355#define CONFIG_SYS_NAND_DDR_LAW 11
356#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
357#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800358#define CONFIG_CMD_NAND
359#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
360
361#if defined(CONFIG_NAND)
362#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
363#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
364#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
365#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
366#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
367#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
368#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
369#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
Shengzhou Liu22cbf962014-03-13 10:19:00 +0800370#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
371#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
372#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
373#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
374#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
375#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
376#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
377#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
378#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
379#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800380#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
381#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
382#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
383#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
384#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
385#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
386#else
387#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
388#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
389#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
390#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
391#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
392#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
393#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
394#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liu22cbf962014-03-13 10:19:00 +0800395#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
396#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
397#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
398#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
399#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
400#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
401#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
402#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800403#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
404#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
405#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
406#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
407#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
408#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
409#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
410#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
411#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800412
413#if defined(CONFIG_RAMBOOT_PBL)
414#define CONFIG_SYS_RAMBOOT
415#endif
416
Shengzhou Liub19e2882014-04-18 16:43:39 +0800417#ifdef CONFIG_SPL_BUILD
418#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
419#else
420#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
421#endif
422
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800423#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
424#define CONFIG_MISC_INIT_R
425#define CONFIG_HWCONFIG
426
427/* define to use L1 as initial stack */
428#define CONFIG_L1_INIT_RAM
429#define CONFIG_SYS_INIT_RAM_LOCK
430#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
431#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700432#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800433/* The assembler doesn't like typecast */
434#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
435 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
436 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
437#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
438#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
439 GENERATED_GBL_DATA_SIZE)
440#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530441#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800442#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
443
444/*
445 * Serial Port
446 */
447#define CONFIG_CONS_INDEX 1
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800448#define CONFIG_SYS_NS16550_SERIAL
449#define CONFIG_SYS_NS16550_REG_SIZE 1
450#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
451#define CONFIG_SYS_BAUDRATE_TABLE \
452 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
453#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
454#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
455#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
456#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
457
458/* Use the HUSH parser */
459#define CONFIG_SYS_HUSH_PARSER
460#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
461
462/* pass open firmware flat tree */
463#define CONFIG_OF_LIBFDT
464#define CONFIG_OF_BOARD_SETUP
465#define CONFIG_OF_STDOUT_VIA_ALIAS
466
467/* new uImage format support */
468#define CONFIG_FIT
469#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
470
471/*
472 * I2C
473 */
474#define CONFIG_SYS_I2C
475#define CONFIG_SYS_I2C_FSL
476#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
477#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
478#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
479#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
480#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
481#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
482#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
483#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
484#define CONFIG_SYS_FSL_I2C_SPEED 100000
485#define CONFIG_SYS_FSL_I2C2_SPEED 100000
486#define CONFIG_SYS_FSL_I2C3_SPEED 100000
487#define CONFIG_SYS_FSL_I2C4_SPEED 100000
488#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
489#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
490#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
491#define I2C_MUX_CH_DEFAULT 0x8
492
Ying Zhang3ad27372014-10-31 18:06:18 +0800493#define I2C_MUX_CH_VOL_MONITOR 0xa
494
495/* Voltage monitor on channel 2*/
496#define I2C_VOL_MONITOR_ADDR 0x40
497#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
498#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
499#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
500
501#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
502#ifndef CONFIG_SPL_BUILD
503#define CONFIG_VID
504#endif
505#define CONFIG_VOL_MONITOR_IR36021_SET
506#define CONFIG_VOL_MONITOR_IR36021_READ
507/* The lowest and highest voltage allowed for T208xQDS */
508#define VDD_MV_MIN 819
509#define VDD_MV_MAX 1212
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800510
511/*
512 * RapidIO
513 */
514#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
515#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
516#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
517#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
518#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
519#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
520/*
521 * for slave u-boot IMAGE instored in master memory space,
522 * PHYS must be aligned based on the SIZE
523 */
Liu Gange4911812014-05-15 14:30:34 +0800524#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
525#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
526#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
527#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800528/*
529 * for slave UCODE and ENV instored in master memory space,
530 * PHYS must be aligned based on the SIZE
531 */
Liu Gange4911812014-05-15 14:30:34 +0800532#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800533#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
534#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
535
536/* slave core release by master*/
537#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
538#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
539
540/*
541 * SRIO_PCIE_BOOT - SLAVE
542 */
543#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
544#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
545#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
546 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
547#endif
548
549/*
550 * eSPI - Enhanced SPI
551 */
552#ifdef CONFIG_SPI_FLASH
Shengzhou Liu09c20462014-05-21 13:26:17 +0800553#ifndef CONFIG_SPL_BUILD
Shengzhou Liu254887a2014-02-21 13:16:19 +0800554#endif
555
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800556#define CONFIG_CMD_SF
Shengzhou Liub19e2882014-04-18 16:43:39 +0800557#define CONFIG_SPI_FLASH_BAR
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800558#define CONFIG_SF_DEFAULT_SPEED 10000000
559#define CONFIG_SF_DEFAULT_MODE 0
560#endif
561
562/*
563 * General PCI
564 * Memory space is mapped 1-1, but I/O space must start from 0.
565 */
566#define CONFIG_PCI /* Enable PCI/PCIE */
567#define CONFIG_PCIE1 /* PCIE controler 1 */
568#define CONFIG_PCIE2 /* PCIE controler 2 */
569#define CONFIG_PCIE3 /* PCIE controler 3 */
570#define CONFIG_PCIE4 /* PCIE controler 4 */
Zhao Qiang5066e622015-03-26 16:13:09 +0800571#define CONFIG_FSL_PCIE_RESET
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800572#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
573#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
574/* controller 1, direct to uli, tgtid 3, Base address 20000 */
575#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
576#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
577#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
578#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
579#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
580#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
581#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
582#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
583
584/* controller 2, Slot 2, tgtid 2, Base address 201000 */
585#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
586#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
587#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
588#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
589#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
590#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
591#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
592#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
593
594/* controller 3, Slot 1, tgtid 1, Base address 202000 */
595#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
596#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
597#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
598#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
599#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
600#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
601#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
602#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
603
604/* controller 4, Base address 203000 */
605#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
606#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
607#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
608#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
609#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
610#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
611#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
612
613#ifdef CONFIG_PCI
614#define CONFIG_PCI_INDIRECT_BRIDGE
Shengzhou Liu254887a2014-02-21 13:16:19 +0800615#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800616#define CONFIG_PCI_PNP /* do pci plug-and-play */
617#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
618#define CONFIG_DOS_PARTITION
619#endif
620
621/* Qman/Bman */
622#ifndef CONFIG_NOBQFMAN
623#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
624#define CONFIG_SYS_BMAN_NUM_PORTALS 18
625#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
626#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
627#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500628#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
629#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
630#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
631#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
632#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
633 CONFIG_SYS_BMAN_CENA_SIZE)
634#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
635#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800636#define CONFIG_SYS_QMAN_NUM_PORTALS 18
637#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
638#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
639#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500640#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
641#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
642#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
643#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
644#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
645 CONFIG_SYS_QMAN_CENA_SIZE)
646#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
647#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800648
649#define CONFIG_SYS_DPAA_FMAN
650#define CONFIG_SYS_DPAA_PME
651#define CONFIG_SYS_PMAN
652#define CONFIG_SYS_DPAA_DCE
653#define CONFIG_SYS_DPAA_RMAN /* RMan */
654#define CONFIG_SYS_INTERLAKEN
655
656/* Default address of microcode for the Linux Fman driver */
657#if defined(CONFIG_SPIFLASH)
658/*
659 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
660 * env, so we got 0x110000.
661 */
662#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800663#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800664#elif defined(CONFIG_SDCARD)
665/*
666 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liub19e2882014-04-18 16:43:39 +0800667 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
668 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800669 */
670#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Shengzhou Liub19e2882014-04-18 16:43:39 +0800671#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800672#elif defined(CONFIG_NAND)
673#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liub19e2882014-04-18 16:43:39 +0800674#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800675#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
676/*
677 * Slave has no ucode locally, it can fetch this from remote. When implementing
678 * in two corenet boards, slave's ucode could be stored in master's memory
679 * space, the address can be mapped from slave TLB->slave LAW->
680 * slave SRIO or PCIE outbound window->master inbound window->
681 * master LAW->the ucode address in master's memory space.
682 */
683#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800684#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800685#else
686#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800687#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800688#endif
689#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
690#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
691#endif /* CONFIG_NOBQFMAN */
692
693#ifdef CONFIG_SYS_DPAA_FMAN
694#define CONFIG_FMAN_ENET
695#define CONFIG_PHYLIB_10G
696#define CONFIG_PHY_VITESSE
697#define CONFIG_PHY_REALTEK
698#define CONFIG_PHY_TERANETICS
699#define RGMII_PHY1_ADDR 0x1
700#define RGMII_PHY2_ADDR 0x2
701#define FM1_10GEC1_PHY_ADDR 0x3
702#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
703#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
704#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
705#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
706#endif
707
708#ifdef CONFIG_FMAN_ENET
709#define CONFIG_MII /* MII PHY management */
710#define CONFIG_ETHPRIME "FM1@DTSEC3"
711#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
712#endif
713
714/*
715 * SATA
716 */
717#ifdef CONFIG_FSL_SATA_V2
718#define CONFIG_LIBATA
719#define CONFIG_FSL_SATA
720#define CONFIG_SYS_SATA_MAX_DEVICE 2
721#define CONFIG_SATA1
722#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
723#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
724#define CONFIG_SATA2
725#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
726#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
727#define CONFIG_LBA48
728#define CONFIG_CMD_SATA
729#define CONFIG_DOS_PARTITION
730#define CONFIG_CMD_EXT2
731#endif
732
733/*
734 * USB
735 */
736#ifdef CONFIG_USB_EHCI
737#define CONFIG_CMD_USB
738#define CONFIG_USB_STORAGE
739#define CONFIG_USB_EHCI_FSL
740#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
741#define CONFIG_CMD_EXT2
742#define CONFIG_HAS_FSL_DR_USB
743#endif
744
745/*
746 * SDHC
747 */
748#ifdef CONFIG_MMC
749#define CONFIG_CMD_MMC
750#define CONFIG_FSL_ESDHC
Yangbo Lu3285e6c2015-04-22 13:57:56 +0800751#define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800752#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
753#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
754#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
755#define CONFIG_GENERIC_MMC
756#define CONFIG_CMD_EXT2
757#define CONFIG_CMD_FAT
758#define CONFIG_DOS_PARTITION
Yangbo Lub46cf1b2015-04-22 13:57:21 +0800759#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800760#endif
761
Shengzhou Liu9941cf72014-04-02 14:28:34 +0800762
763/*
764 * Dynamic MTD Partition support with mtdparts
765 */
766#ifndef CONFIG_SYS_NO_FLASH
767#define CONFIG_MTD_DEVICE
768#define CONFIG_MTD_PARTITIONS
769#define CONFIG_CMD_MTDPARTS
770#define CONFIG_FLASH_CFI_MTD
771#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
772 "spi0=spife110000.0"
773#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
774 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
775 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
776 "1m(uboot),5m(kernel),128k(dtb),-(user)"
777#endif
778
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800779/*
780 * Environment
781 */
782#define CONFIG_LOADS_ECHO /* echo on for serial download */
783#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
784
785/*
786 * Command line configuration.
787 */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800788#define CONFIG_CMD_DHCP
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800789#define CONFIG_CMD_ERRATA
790#define CONFIG_CMD_GREPENV
791#define CONFIG_CMD_IRQ
792#define CONFIG_CMD_I2C
793#define CONFIG_CMD_MII
794#define CONFIG_CMD_PING
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800795#define CONFIG_CMD_REGINFO
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800796
797#ifdef CONFIG_PCI
798#define CONFIG_CMD_PCI
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800799#endif
800
Ruchika Gupta737537e2014-10-15 11:35:31 +0530801/* Hash command with SHA acceleration supported in hardware */
802#ifdef CONFIG_FSL_CAAM
803#define CONFIG_CMD_HASH
804#define CONFIG_SHA_HW_ACCEL
805#endif
806
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800807/*
808 * Miscellaneous configurable options
809 */
810#define CONFIG_SYS_LONGHELP /* undef to save memory */
811#define CONFIG_CMDLINE_EDITING /* Command-line editing */
812#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
813#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800814#ifdef CONFIG_CMD_KGDB
815#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
816#else
817#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
818#endif
819#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
820#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
821#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800822
823/*
824 * For booting Linux, the board info and command line data
825 * have to be in the first 64 MB of memory, since this is
826 * the maximum mapped by the Linux kernel during initialization.
827 */
828#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
829#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
830
831#ifdef CONFIG_CMD_KGDB
832#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
833#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
834#endif
835
836/*
837 * Environment Configuration
838 */
839#define CONFIG_ROOTPATH "/opt/nfsroot"
840#define CONFIG_BOOTFILE "uImage"
841#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
842
843/* default location for tftp and bootm */
844#define CONFIG_LOADADDR 1000000
845#define CONFIG_BAUDRATE 115200
846#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
847#define __USB_PHY_TYPE utmi
848
849#define CONFIG_EXTRA_ENV_SETTINGS \
850 "hwconfig=fsl_ddr:" \
851 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
852 "bank_intlv=auto;" \
853 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
854 "netdev=eth0\0" \
855 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
856 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
857 "tftpflash=tftpboot $loadaddr $uboot && " \
858 "protect off $ubootaddr +$filesize && " \
859 "erase $ubootaddr +$filesize && " \
860 "cp.b $loadaddr $ubootaddr $filesize && " \
861 "protect on $ubootaddr +$filesize && " \
862 "cmp.b $loadaddr $ubootaddr $filesize\0" \
863 "consoledev=ttyS0\0" \
864 "ramdiskaddr=2000000\0" \
865 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
866 "fdtaddr=c00000\0" \
867 "fdtfile=t2080qds/t2080qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500868 "bdev=sda3\0"
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800869
870/*
871 * For emulation this causes u-boot to jump to the start of the
872 * proof point app code automatically
873 */
874#define CONFIG_PROOF_POINTS \
875 "setenv bootargs root=/dev/$bdev rw " \
876 "console=$consoledev,$baudrate $othbootargs;" \
877 "cpu 1 release 0x29000000 - - -;" \
878 "cpu 2 release 0x29000000 - - -;" \
879 "cpu 3 release 0x29000000 - - -;" \
880 "cpu 4 release 0x29000000 - - -;" \
881 "cpu 5 release 0x29000000 - - -;" \
882 "cpu 6 release 0x29000000 - - -;" \
883 "cpu 7 release 0x29000000 - - -;" \
884 "go 0x29000000"
885
886#define CONFIG_HVBOOT \
887 "setenv bootargs config-addr=0x60000000; " \
888 "bootm 0x01000000 - 0x00f00000"
889
890#define CONFIG_ALU \
891 "setenv bootargs root=/dev/$bdev rw " \
892 "console=$consoledev,$baudrate $othbootargs;" \
893 "cpu 1 release 0x01000000 - - -;" \
894 "cpu 2 release 0x01000000 - - -;" \
895 "cpu 3 release 0x01000000 - - -;" \
896 "cpu 4 release 0x01000000 - - -;" \
897 "cpu 5 release 0x01000000 - - -;" \
898 "cpu 6 release 0x01000000 - - -;" \
899 "cpu 7 release 0x01000000 - - -;" \
900 "go 0x01000000"
901
902#define CONFIG_LINUX \
903 "setenv bootargs root=/dev/ram rw " \
904 "console=$consoledev,$baudrate $othbootargs;" \
905 "setenv ramdiskaddr 0x02000000;" \
906 "setenv fdtaddr 0x00c00000;" \
907 "setenv loadaddr 0x1000000;" \
908 "bootm $loadaddr $ramdiskaddr $fdtaddr"
909
910#define CONFIG_HDBOOT \
911 "setenv bootargs root=/dev/$bdev rw " \
912 "console=$consoledev,$baudrate $othbootargs;" \
913 "tftp $loadaddr $bootfile;" \
914 "tftp $fdtaddr $fdtfile;" \
915 "bootm $loadaddr - $fdtaddr"
916
917#define CONFIG_NFSBOOTCOMMAND \
918 "setenv bootargs root=/dev/nfs rw " \
919 "nfsroot=$serverip:$rootpath " \
920 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
921 "console=$consoledev,$baudrate $othbootargs;" \
922 "tftp $loadaddr $bootfile;" \
923 "tftp $fdtaddr $fdtfile;" \
924 "bootm $loadaddr - $fdtaddr"
925
926#define CONFIG_RAMBOOTCOMMAND \
927 "setenv bootargs root=/dev/ram rw " \
928 "console=$consoledev,$baudrate $othbootargs;" \
929 "tftp $ramdiskaddr $ramdiskfile;" \
930 "tftp $loadaddr $bootfile;" \
931 "tftp $fdtaddr $fdtfile;" \
932 "bootm $loadaddr $ramdiskaddr $fdtaddr"
933
934#define CONFIG_BOOTCOMMAND CONFIG_LINUX
935
936#ifdef CONFIG_SECURE_BOOT
937#include <asm/fsl_secure_boot.h>
Ruchika Gupta789490b2014-10-07 15:48:46 +0530938#define CONFIG_CMD_BLOB
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800939#undef CONFIG_CMD_USB
940#endif
941
Shengzhou Liu254887a2014-02-21 13:16:19 +0800942#endif /* __T208xQDS_H */