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Bartlomiej Sieka038ccac2006-02-24 09:37:22 +01001/*
2 * (C) Copyright 2006 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
William Juulcfa460a2007-10-31 13:53:06 +010024#include <asm/io.h>
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010025
Jon Loeligerb9307262007-07-09 18:24:55 -050026#if defined(CONFIG_CMD_NAND)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010027
28#include <nand.h>
29
30/*
31 * hardware specific access to control-lines
32 * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
33 */
William Juulcfa460a2007-10-31 13:53:06 +010034static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010035{
William Juulcfa460a2007-10-31 13:53:06 +010036 struct nand_chip *this = mtd->priv;
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010037 ulong base = (ulong) this->IO_ADDR_W;
38
William Juul5e1dae52007-11-09 13:32:30 +010039 if (ctrl & NAND_CTRL_CHANGE) {
William Juulcfa460a2007-10-31 13:53:06 +010040 if ( ctrl & NAND_CLE )
41 MACRO_NAND_CTL_SETCLE((unsigned long)base);
42 else
43 MACRO_NAND_CTL_CLRCLE((unsigned long)base);
44 if ( ctrl & NAND_ALE )
45 MACRO_NAND_CTL_CLRCLE((unsigned long)base);
46 else
47 MACRO_NAND_CTL_CLRALE((unsigned long)base);
48 if ( ctrl & NAND_NCE )
49 MACRO_NAND_ENABLE_CE((unsigned long)base);
50 else
51 MACRO_NAND_DISABLE_CE((unsigned long)base);
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010052 }
William Juulcfa460a2007-10-31 13:53:06 +010053
William Juul5e1dae52007-11-09 13:32:30 +010054 if (cmd != NAND_CMD_NONE)
William Juul4cbb6512007-11-08 10:39:53 +010055 writeb(cmd, this->IO_ADDR_W);
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010056}
57
58
59/*
60 * read device ready pin
61 * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
62 */
63static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
64{
65 struct nand_chip *this = mtdinfo->priv;
66 ulong rb_gpio_pin;
67
68 /* use the base addr to find out which chip are we dealing with */
69 switch((ulong) this->IO_ADDR_W) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070 case CONFIG_SYS_NAND0_BASE:
71 rb_gpio_pin = CONFIG_SYS_NAND0_RDY;
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010072 break;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073 case CONFIG_SYS_NAND1_BASE:
74 rb_gpio_pin = CONFIG_SYS_NAND1_RDY;
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010075 break;
76 default: /* this should never happen */
77 return 0;
78 break;
79 }
80
Wolfgang Denkbfc81252006-03-06 13:03:37 +010081 if (in32(GPIO0_IR) & rb_gpio_pin)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010082 return 1;
83 return 0;
84}
85
86
87/*
88 * Board-specific NAND initialization. The following members of the
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010089 * argument are board-specific (per include/linux/mtd/nand.h):
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010090 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
91 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
William Juulcfa460a2007-10-31 13:53:06 +010092 * - cmd_ctrl: hardwarespecific function for accesing control-lines
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010093 * - dev_ready: hardwarespecific function for accesing device ready/busy line
94 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
95 * only be provided if a hardware ECC is available
William Juulcfa460a2007-10-31 13:53:06 +010096 * - ecc.mode: mode of ecc, see defines
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +010097 * - chip_delay: chip dependent delay for transfering data from array to
98 * read regs (tR)
99 * - options: various chip options. They can partly be set to inform
100 * nand_scan about special functionality. See the defines for further
101 * explanation
102 * Members with a "?" were not set in the merged testing-NAND branch,
103 * so they are not set here either.
104 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100105int board_nand_init(struct nand_chip *nand)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100106{
107
William Juulcfa460a2007-10-31 13:53:06 +0100108 nand->cmd_ctrl = ppchameleonevb_hwcontrol;
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100109 nand->dev_ready = ppchameleonevb_device_ready;
William Juulcfa460a2007-10-31 13:53:06 +0100110 nand->ecc.mode = NAND_ECC_SOFT;
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100111 nand->chip_delay = NAND_BIG_DELAY_US;
112 nand->options = NAND_SAMSUNG_LP_OPTIONS;
Heiko Schocherfa230442006-12-21 17:17:02 +0100113 return 0;
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100114}
Jon Loeligerb9307262007-07-09 18:24:55 -0500115#endif