blob: cbba399f0f85e7efb395d1b10dba3c02cecf09bb [file] [log] [blame]
Jon Loeliger126aa702006-05-30 17:47:00 -05001/*
Timur Tabi2feb4af2010-03-31 17:44:13 -05002 * Copyright 2006,2010 Freescale Semiconductor
Jon Loeliger126aa702006-05-30 17:47:00 -05003 * Jeff Brown
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jon Loeliger126aa702006-05-30 17:47:00 -05007 */
8
9#include <common.h>
Jon Loeliger126aa702006-05-30 17:47:00 -050010#include <command.h>
Andy Fleming5a8a1632008-08-31 16:33:30 -050011#include <asm/io.h>
Jon Loeligerad8f8682008-01-15 13:42:41 -060012
Timur Tabi2feb4af2010-03-31 17:44:13 -050013#define pixis_base (u8 *)PIXIS_BASE
Haiying Wang3d98b852007-01-22 12:37:30 -060014
15/*
16 * Simple board reset.
17 */
18void pixis_reset(void)
19{
Kumar Gala048e7ef2009-07-22 10:12:39 -050020 out_8(pixis_base + PIXIS_RST, 0);
Haiying Wang3d98b852007-01-22 12:37:30 -060021
Timur Tabi2feb4af2010-03-31 17:44:13 -050022 while (1);
23}
Haiying Wang3d98b852007-01-22 12:37:30 -060024
Jon Loeliger126aa702006-05-30 17:47:00 -050025/*
26 * Per table 27, page 58 of MPC8641HPCN spec.
27 */
Timur Tabi2feb4af2010-03-31 17:44:13 -050028static int set_px_sysclk(unsigned long sysclk)
Jon Loeliger126aa702006-05-30 17:47:00 -050029{
30 u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
31
32 switch (sysclk) {
33 case 33:
34 sysclk_s = 0x04;
35 sysclk_r = 0x04;
36 sysclk_v = 0x07;
37 sysclk_aux = 0x00;
38 break;
39 case 40:
40 sysclk_s = 0x01;
41 sysclk_r = 0x1F;
42 sysclk_v = 0x20;
43 sysclk_aux = 0x01;
44 break;
45 case 50:
46 sysclk_s = 0x01;
47 sysclk_r = 0x1F;
48 sysclk_v = 0x2A;
49 sysclk_aux = 0x02;
50 break;
51 case 66:
52 sysclk_s = 0x01;
53 sysclk_r = 0x04;
54 sysclk_v = 0x04;
55 sysclk_aux = 0x03;
56 break;
57 case 83:
58 sysclk_s = 0x01;
59 sysclk_r = 0x1F;
60 sysclk_v = 0x4B;
61 sysclk_aux = 0x04;
62 break;
63 case 100:
64 sysclk_s = 0x01;
65 sysclk_r = 0x1F;
66 sysclk_v = 0x5C;
67 sysclk_aux = 0x05;
68 break;
69 case 134:
70 sysclk_s = 0x06;
71 sysclk_r = 0x1F;
72 sysclk_v = 0x3B;
73 sysclk_aux = 0x06;
74 break;
75 case 166:
76 sysclk_s = 0x06;
77 sysclk_r = 0x1F;
78 sysclk_v = 0x4B;
79 sysclk_aux = 0x07;
80 break;
81 default:
82 printf("Unsupported SYSCLK frequency.\n");
83 return 0;
84 }
85
Jon Loeliger80e955c2006-08-22 12:25:27 -050086 vclkh = (sysclk_s << 5) | sysclk_r;
Jon Loeliger126aa702006-05-30 17:47:00 -050087 vclkl = sysclk_v;
88
Kumar Gala048e7ef2009-07-22 10:12:39 -050089 out_8(pixis_base + PIXIS_VCLKH, vclkh);
90 out_8(pixis_base + PIXIS_VCLKL, vclkl);
Jon Loeliger126aa702006-05-30 17:47:00 -050091
Kumar Gala048e7ef2009-07-22 10:12:39 -050092 out_8(pixis_base + PIXIS_AUX, sysclk_aux);
Jon Loeliger126aa702006-05-30 17:47:00 -050093
94 return 1;
95}
96
Timur Tabi2feb4af2010-03-31 17:44:13 -050097/* Set the CFG_SYSPLL bits
98 *
99 * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
100 * read_from_px_regs() is called.
101 */
102static int set_px_mpxpll(unsigned long mpxpll)
Jon Loeliger126aa702006-05-30 17:47:00 -0500103{
Jon Loeliger126aa702006-05-30 17:47:00 -0500104 switch (mpxpll) {
105 case 2:
106 case 4:
107 case 6:
108 case 8:
109 case 10:
110 case 12:
111 case 14:
112 case 16:
Timur Tabi2feb4af2010-03-31 17:44:13 -0500113 clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
114 return 1;
Jon Loeliger126aa702006-05-30 17:47:00 -0500115 }
116
Timur Tabi2feb4af2010-03-31 17:44:13 -0500117 printf("Unsupported MPXPLL ratio.\n");
118 return 0;
Jon Loeliger126aa702006-05-30 17:47:00 -0500119}
120
Timur Tabi2feb4af2010-03-31 17:44:13 -0500121static int set_px_corepll(unsigned long corepll)
Jon Loeliger126aa702006-05-30 17:47:00 -0500122{
Jon Loeliger126aa702006-05-30 17:47:00 -0500123 u8 val;
124
Timur Tabi2feb4af2010-03-31 17:44:13 -0500125 switch (corepll) {
Jon Loeliger126aa702006-05-30 17:47:00 -0500126 case 20:
127 val = 0x08;
128 break;
129 case 25:
130 val = 0x0C;
131 break;
132 case 30:
133 val = 0x10;
134 break;
135 case 35:
136 val = 0x1C;
137 break;
138 case 40:
139 val = 0x14;
140 break;
141 case 45:
142 val = 0x0E;
143 break;
144 default:
145 printf("Unsupported COREPLL ratio.\n");
146 return 0;
147 }
148
Timur Tabi2feb4af2010-03-31 17:44:13 -0500149 clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
Jon Loeliger126aa702006-05-30 17:47:00 -0500150 return 1;
151}
152
Timur Tabi2feb4af2010-03-31 17:44:13 -0500153#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
154#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
155#endif
Jon Loeliger126aa702006-05-30 17:47:00 -0500156
Timur Tabi2feb4af2010-03-31 17:44:13 -0500157/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
158 *
159 * The PIXIS can be programmed to look at either the on-board dip switches
160 * or various other PIXIS registers to determine the values for COREPLL,
161 * MPXPLL, and SYSCLK.
162 *
163 * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
164 * register that tells the pixis to use the various PIXIS register.
165 */
166static void read_from_px_regs(int set)
Jon Loeliger126aa702006-05-30 17:47:00 -0500167{
Kumar Gala048e7ef2009-07-22 10:12:39 -0500168 u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
Jon Loeliger126aa702006-05-30 17:47:00 -0500169
170 if (set)
Timur Tabi2feb4af2010-03-31 17:44:13 -0500171 tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
Jon Loeliger126aa702006-05-30 17:47:00 -0500172 else
Timur Tabi2feb4af2010-03-31 17:44:13 -0500173 tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
174
Kumar Gala048e7ef2009-07-22 10:12:39 -0500175 out_8(pixis_base + PIXIS_VCFGEN0, tmp);
Jon Loeliger126aa702006-05-30 17:47:00 -0500176}
177
Timur Tabi2feb4af2010-03-31 17:44:13 -0500178/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
179 * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
180 */
181#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
182#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
183#endif
Jon Loeliger126aa702006-05-30 17:47:00 -0500184
Timur Tabi2feb4af2010-03-31 17:44:13 -0500185/* Configure the source of the boot location
186 *
187 * The PIXIS can be programmed to look at either the on-board dip switches
188 * or the PX_VBOOT[LBMAP] register to determine where we should boot.
189 *
190 * If we want to boot from the alternate boot bank, we need to tell the PIXIS
191 * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
192 */
193static void read_from_px_regs_altbank(int set)
Jon Loeliger126aa702006-05-30 17:47:00 -0500194{
Kumar Gala048e7ef2009-07-22 10:12:39 -0500195 u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500196
197 if (set)
Timur Tabi2feb4af2010-03-31 17:44:13 -0500198 tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
Jon Loeliger126aa702006-05-30 17:47:00 -0500199 else
Timur Tabi2feb4af2010-03-31 17:44:13 -0500200 tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
201
Kumar Gala048e7ef2009-07-22 10:12:39 -0500202 out_8(pixis_base + PIXIS_VCFGEN1, tmp);
Jon Loeliger126aa702006-05-30 17:47:00 -0500203}
204
Timur Tabi2feb4af2010-03-31 17:44:13 -0500205/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
206 * tells the PIXIS what the alternate flash bank is.
207 *
208 * Note that it's not really a mask. It contains the actual LBMAP bits that
209 * must be set to select the alternate bank. This code assumes that the
210 * primary bank has these bits set to 0, and the alternate bank has these
211 * bits set to 1.
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
214#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
Jason Jindb74b3c2007-10-29 19:26:21 +0800215#endif
Jon Loeliger126aa702006-05-30 17:47:00 -0500216
Timur Tabi2feb4af2010-03-31 17:44:13 -0500217/* Tell the PIXIS to boot from the default flash bank
218 *
219 * Program the default flash bank into the VBOOT register. This register is
220 * used only if PX_VCFGEN1[FLASH]=1.
221 */
222static void clear_altbank(void)
James Yang16c3cde2008-01-16 11:58:08 -0600223{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500224 clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
James Yang16c3cde2008-01-16 11:58:08 -0600225}
226
Timur Tabi2feb4af2010-03-31 17:44:13 -0500227/* Tell the PIXIS to boot from the alternate flash bank
228 *
229 * Program the alternate flash bank into the VBOOT register. This register is
230 * used only if PX_VCFGEN1[FLASH]=1.
231 */
232static void set_altbank(void)
Jon Loeliger126aa702006-05-30 17:47:00 -0500233{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500234 setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
Jon Loeliger126aa702006-05-30 17:47:00 -0500235}
236
Timur Tabi2feb4af2010-03-31 17:44:13 -0500237/* Reset the board with watchdog disabled.
238 *
239 * This respects the altbank setting.
240 */
241static void set_px_go(void)
Jon Loeliger126aa702006-05-30 17:47:00 -0500242{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500243 /* Disable the VELA sequencer and watchdog */
244 clrbits_8(pixis_base + PIXIS_VCTL, 9);
Jon Loeliger126aa702006-05-30 17:47:00 -0500245
Timur Tabi2feb4af2010-03-31 17:44:13 -0500246 /* Reboot by starting the VELA sequencer */
247 setbits_8(pixis_base + PIXIS_VCTL, 0x1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500248
Timur Tabi2feb4af2010-03-31 17:44:13 -0500249 while (1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500250}
251
Timur Tabi2feb4af2010-03-31 17:44:13 -0500252/* Reset the board with watchdog enabled.
253 *
254 * This respects the altbank setting.
255 */
256static void set_px_go_with_watchdog(void)
Jon Loeliger126aa702006-05-30 17:47:00 -0500257{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500258 /* Disable the VELA sequencer */
259 clrbits_8(pixis_base + PIXIS_VCTL, 1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500260
Timur Tabi2feb4af2010-03-31 17:44:13 -0500261 /* Enable the watchdog and reboot by starting the VELA sequencer */
262 setbits_8(pixis_base + PIXIS_VCTL, 0x9);
Jon Loeliger126aa702006-05-30 17:47:00 -0500263
Timur Tabi2feb4af2010-03-31 17:44:13 -0500264 while (1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500265}
266
Timur Tabi2feb4af2010-03-31 17:44:13 -0500267/* Disable the watchdog
268 *
269 */
270static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200271 char * const argv[])
Jon Loeliger126aa702006-05-30 17:47:00 -0500272{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500273 /* Disable the VELA sequencer and the watchdog */
274 clrbits_8(pixis_base + PIXIS_VCTL, 9);
Jon Loeliger126aa702006-05-30 17:47:00 -0500275
276 return 0;
277}
278
Jon Loeliger126aa702006-05-30 17:47:00 -0500279U_BOOT_CMD(
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200280 diswd, 1, 0, pixis_disable_watchdog_cmd,
281 "Disable watchdog timer",
282 ""
283);
Jon Loeliger126aa702006-05-30 17:47:00 -0500284
Liu Yubff188b2008-10-10 11:40:58 +0800285#ifdef CONFIG_PIXIS_SGMII_CMD
Timur Tabi2feb4af2010-03-31 17:44:13 -0500286
287/* Enable or disable SGMII mode for a TSEC
288 */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200289static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Andy Fleming5a8a1632008-08-31 16:33:30 -0500290{
291 int which_tsec = -1;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500292 unsigned char mask;
293 unsigned char switch_mask;
Andy Fleming5a8a1632008-08-31 16:33:30 -0500294
Timur Tabi2feb4af2010-03-31 17:44:13 -0500295 if ((argc > 2) && (strcmp(argv[1], "all") != 0))
296 which_tsec = simple_strtoul(argv[1], NULL, 0);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500297
298 switch (which_tsec) {
Liu Yubff188b2008-10-10 11:40:58 +0800299#ifdef CONFIG_TSEC1
Andy Fleming5a8a1632008-08-31 16:33:30 -0500300 case 1:
301 mask = PIXIS_VSPEED2_TSEC1SER;
302 switch_mask = PIXIS_VCFGEN1_TSEC1SER;
303 break;
Liu Yubff188b2008-10-10 11:40:58 +0800304#endif
305#ifdef CONFIG_TSEC2
306 case 2:
307 mask = PIXIS_VSPEED2_TSEC2SER;
308 switch_mask = PIXIS_VCFGEN1_TSEC2SER;
309 break;
310#endif
311#ifdef CONFIG_TSEC3
Andy Fleming5a8a1632008-08-31 16:33:30 -0500312 case 3:
313 mask = PIXIS_VSPEED2_TSEC3SER;
314 switch_mask = PIXIS_VCFGEN1_TSEC3SER;
315 break;
Liu Yubff188b2008-10-10 11:40:58 +0800316#endif
317#ifdef CONFIG_TSEC4
318 case 4:
319 mask = PIXIS_VSPEED2_TSEC4SER;
320 switch_mask = PIXIS_VCFGEN1_TSEC4SER;
321 break;
322#endif
Andy Fleming5a8a1632008-08-31 16:33:30 -0500323 default:
Liu Yubff188b2008-10-10 11:40:58 +0800324 mask = PIXIS_VSPEED2_MASK;
325 switch_mask = PIXIS_VCFGEN1_MASK;
Andy Fleming5a8a1632008-08-31 16:33:30 -0500326 break;
327 }
328
329 /* Toggle whether the switches or FPGA control the settings */
330 if (!strcmp(argv[argc - 1], "switch"))
Kumar Gala048e7ef2009-07-22 10:12:39 -0500331 clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500332 else
Kumar Gala048e7ef2009-07-22 10:12:39 -0500333 setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500334
335 /* If it's not the switches, enable or disable SGMII, as specified */
336 if (!strcmp(argv[argc - 1], "on"))
Kumar Gala048e7ef2009-07-22 10:12:39 -0500337 clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500338 else if (!strcmp(argv[argc - 1], "off"))
Kumar Gala048e7ef2009-07-22 10:12:39 -0500339 setbits_8(pixis_base + PIXIS_VSPEED2, mask);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500340
341 return 0;
342}
343
344U_BOOT_CMD(
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200345 pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
346 "pixis_set_sgmii"
347 " - Enable or disable SGMII mode for a given TSEC \n",
348 "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
349 " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
350 " on - enables SGMII\n"
351 " off - disables SGMII\n"
352 " switch - use switch settings"
353);
Timur Tabi2feb4af2010-03-31 17:44:13 -0500354
Andy Fleming5a8a1632008-08-31 16:33:30 -0500355#endif
356
Jon Loeliger126aa702006-05-30 17:47:00 -0500357/*
358 * This function takes the non-integral cpu:mpx pll ratio
359 * and converts it to an integer that can be used to assign
360 * FPGA register values.
361 * input: strptr i.e. argv[2]
362 */
Timur Tabi2feb4af2010-03-31 17:44:13 -0500363static unsigned long strfractoint(char *strptr)
Jon Loeliger126aa702006-05-30 17:47:00 -0500364{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500365 int i, j;
Jon Loeliger126aa702006-05-30 17:47:00 -0500366 int mulconst;
Kumar Gala8dbd4b72011-11-09 10:02:11 -0600367 int no_dec = 0;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500368 unsigned long intval = 0, decval = 0;
369 char intarr[3], decarr[3];
Jon Loeliger126aa702006-05-30 17:47:00 -0500370
371 /* Assign the integer part to intarr[]
372 * If there is no decimal point i.e.
373 * if the ratio is an integral value
374 * simply create the intarr.
375 */
376 i = 0;
James Yang16c3cde2008-01-16 11:58:08 -0600377 while (strptr[i] != '.') {
Jon Loeliger126aa702006-05-30 17:47:00 -0500378 if (strptr[i] == 0) {
379 no_dec = 1;
380 break;
381 }
382 intarr[i] = strptr[i];
383 i++;
384 }
385
Jon Loeliger126aa702006-05-30 17:47:00 -0500386 intarr[i] = '\0';
387
388 if (no_dec) {
389 /* Currently needed only for single digit corepll ratios */
Jon Loeliger80e955c2006-08-22 12:25:27 -0500390 mulconst = 10;
Jon Loeliger126aa702006-05-30 17:47:00 -0500391 decval = 0;
392 } else {
393 j = 0;
Jon Loeliger80e955c2006-08-22 12:25:27 -0500394 i++; /* Skipping the decimal point */
James Yang16c3cde2008-01-16 11:58:08 -0600395 while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
Jon Loeliger126aa702006-05-30 17:47:00 -0500396 decarr[j] = strptr[i];
397 i++;
398 j++;
399 }
400
Jon Loeliger126aa702006-05-30 17:47:00 -0500401 decarr[j] = '\0';
402
403 mulconst = 1;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500404 for (i = 0; i < j; i++)
Jon Loeliger126aa702006-05-30 17:47:00 -0500405 mulconst *= 10;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500406 decval = simple_strtoul(decarr, NULL, 10);
Jon Loeliger126aa702006-05-30 17:47:00 -0500407 }
408
Timur Tabi2feb4af2010-03-31 17:44:13 -0500409 intval = simple_strtoul(intarr, NULL, 10);
Jon Loeliger126aa702006-05-30 17:47:00 -0500410 intval = intval * mulconst;
411
Timur Tabi2feb4af2010-03-31 17:44:13 -0500412 return intval + decval;
Jon Loeliger126aa702006-05-30 17:47:00 -0500413}
Haiying Wang3d98b852007-01-22 12:37:30 -0600414
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200415static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Haiying Wang3d98b852007-01-22 12:37:30 -0600416{
James Yang16c3cde2008-01-16 11:58:08 -0600417 unsigned int i;
418 char *p_cf = NULL;
419 char *p_cf_sysclk = NULL;
420 char *p_cf_corepll = NULL;
421 char *p_cf_mpxpll = NULL;
422 char *p_altbank = NULL;
423 char *p_wd = NULL;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500424 int unknown_param = 0;
Haiying Wang3d98b852007-01-22 12:37:30 -0600425
426 /*
427 * No args is a simple reset request.
428 */
429 if (argc <= 1) {
430 pixis_reset();
431 /* not reached */
432 }
433
James Yang16c3cde2008-01-16 11:58:08 -0600434 for (i = 1; i < argc; i++) {
435 if (strcmp(argv[i], "cf") == 0) {
436 p_cf = argv[i];
437 if (i + 3 >= argc) {
438 break;
Haiying Wang3d98b852007-01-22 12:37:30 -0600439 }
James Yang16c3cde2008-01-16 11:58:08 -0600440 p_cf_sysclk = argv[i+1];
441 p_cf_corepll = argv[i+2];
442 p_cf_mpxpll = argv[i+3];
443 i += 3;
444 continue;
Haiying Wang3d98b852007-01-22 12:37:30 -0600445 }
446
James Yang16c3cde2008-01-16 11:58:08 -0600447 if (strcmp(argv[i], "altbank") == 0) {
448 p_altbank = argv[i];
449 continue;
450 }
451
452 if (strcmp(argv[i], "wd") == 0) {
453 p_wd = argv[i];
454 continue;
455 }
456
457 unknown_param = 1;
458 }
459
460 /*
461 * Check that cf has all required parms
462 */
463 if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200464 || unknown_param) {
Ed Swarthoutf7fecc32008-10-08 23:38:01 -0500465#ifdef CONFIG_SYS_LONGHELP
James Yang16c3cde2008-01-16 11:58:08 -0600466 puts(cmdtp->help);
York Sun5bdeff32013-05-31 08:48:04 -0700467 putc('\n');
Ed Swarthoutf7fecc32008-10-08 23:38:01 -0500468#endif
Haiying Wang3d98b852007-01-22 12:37:30 -0600469 return 1;
470 }
471
James Yang16c3cde2008-01-16 11:58:08 -0600472 /*
473 * PIXIS seems to be sensitive to the ordering of
474 * the registers that are touched.
475 */
476 read_from_px_regs(0);
477
Timur Tabi2feb4af2010-03-31 17:44:13 -0500478 if (p_altbank)
James Yang16c3cde2008-01-16 11:58:08 -0600479 read_from_px_regs_altbank(0);
Timur Tabi2feb4af2010-03-31 17:44:13 -0500480
James Yang16c3cde2008-01-16 11:58:08 -0600481 clear_altbank();
482
483 /*
484 * Clock configuration specified.
485 */
486 if (p_cf) {
487 unsigned long sysclk;
488 unsigned long corepll;
489 unsigned long mpxpll;
490
491 sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
Timur Tabi2feb4af2010-03-31 17:44:13 -0500492 corepll = strfractoint(p_cf_corepll);
James Yang16c3cde2008-01-16 11:58:08 -0600493 mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
494
495 if (!(set_px_sysclk(sysclk)
496 && set_px_corepll(corepll)
497 && set_px_mpxpll(mpxpll))) {
Ed Swarthoutf7fecc32008-10-08 23:38:01 -0500498#ifdef CONFIG_SYS_LONGHELP
James Yang16c3cde2008-01-16 11:58:08 -0600499 puts(cmdtp->help);
York Sun5bdeff32013-05-31 08:48:04 -0700500 putc('\n');
Ed Swarthoutf7fecc32008-10-08 23:38:01 -0500501#endif
James Yang16c3cde2008-01-16 11:58:08 -0600502 return 1;
503 }
504 read_from_px_regs(1);
505 }
506
507 /*
508 * Altbank specified
509 *
510 * NOTE CHANGE IN BEHAVIOR: previous code would default
511 * to enabling watchdog if altbank is specified.
512 * Now the watchdog must be enabled explicitly using 'wd'.
513 */
514 if (p_altbank) {
515 set_altbank();
516 read_from_px_regs_altbank(1);
517 }
518
519 /*
520 * Reset with watchdog specified.
521 */
Timur Tabi2feb4af2010-03-31 17:44:13 -0500522 if (p_wd)
James Yang16c3cde2008-01-16 11:58:08 -0600523 set_px_go_with_watchdog();
Timur Tabi2feb4af2010-03-31 17:44:13 -0500524 else
James Yang16c3cde2008-01-16 11:58:08 -0600525 set_px_go();
James Yang16c3cde2008-01-16 11:58:08 -0600526
527 /*
528 * Shouldn't be reached.
529 */
Haiying Wang3d98b852007-01-22 12:37:30 -0600530 return 0;
531}
532
533
534U_BOOT_CMD(
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535 pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
Peter Tyser2fb26042009-01-27 18:03:12 -0600536 "Reset the board using the FPGA sequencer",
Haiying Wang3d98b852007-01-22 12:37:30 -0600537 " pixis_reset\n"
538 " pixis_reset [altbank]\n"
539 " pixis_reset altbank wd\n"
540 " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200541 " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
542);