blob: f7df7f0388000c654df8dcea38c4846c674b3126 [file] [log] [blame]
Andy Fleming67431052007-04-23 02:54:25 -05001/*
Kumar Gala5f7bbd12011-01-04 18:01:49 -06002 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
Andy Fleming67431052007-04-23 02:54:25 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8568mds board configuration file
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/* High Level Configuration Options */
30#define CONFIG_BOOKE 1 /* BOOKE */
Andy Flemingda9d4612007-08-14 00:14:25 -050031#define CONFIG_E500 1 /* BOOKE e500 family */
Andy Fleming67431052007-04-23 02:54:25 -050032#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
33#define CONFIG_MPC8568 1 /* MPC8568 specific */
34#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
35
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036#define CONFIG_SYS_TEXT_BASE 0xfff80000
37
Kumar Gala5f7bbd12011-01-04 18:01:49 -060038#define CONFIG_SYS_SRIO
39#define CONFIG_SRIO1 /* SRIO port 1 */
40
Haiying Wang1563f562007-11-14 15:52:06 -050041#define CONFIG_PCI 1 /* Enable PCI/PCIE */
42#define CONFIG_PCI1 1 /* PCI controller */
43#define CONFIG_PCIE1 1 /* PCIE controller */
44#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
Kumar Gala8ff3de62007-12-07 12:17:34 -060045#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050046#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020047#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingb96c83d2007-08-15 20:03:34 -050048#define CONFIG_QE /* Enable QE */
Andy Fleming67431052007-04-23 02:54:25 -050049#define CONFIG_ENV_OVERWRITE
Kumar Gala4d3521c2008-01-16 09:15:29 -060050#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Andy Fleming67431052007-04-23 02:54:25 -050051
Andy Fleming67431052007-04-23 02:54:25 -050052#ifndef __ASSEMBLY__
53extern unsigned long get_clock_freq(void);
54#endif /*Replace a call to get_clock_freq (after it is implemented)*/
55#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
56
57/*
58 * These can be toggled for performance analysis, otherwise use default.
59 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020060#define CONFIG_L2_CACHE /* toggle L2 cache */
Haiying Wang7a1ac412007-08-23 15:20:54 -040061#define CONFIG_BTB /* toggle branch predition */
Andy Fleming67431052007-04-23 02:54:25 -050062
63/*
64 * Only possible on E500 Version 2 or newer cores.
65 */
66#define CONFIG_ENABLE_36BIT_PHYS 1
67
68
69#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
70
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
72#define CONFIG_SYS_MEMTEST_END 0x00400000
Andy Fleming67431052007-04-23 02:54:25 -050073
74/*
75 * Base addresses -- Note these are effective addresses where the
76 * actual resources get mapped (not physical addresses)
77 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
79#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
80#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
81#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Andy Fleming67431052007-04-23 02:54:25 -050082
Jon Loeligere6f5b352008-03-18 13:51:05 -050083/* DDR Setup */
84#define CONFIG_FSL_DDR2
85#undef CONFIG_FSL_DDR_INTERACTIVE
86#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
87#define CONFIG_DDR_SPD
Dave Liu9b0ad1b2008-10-28 17:53:38 +080088#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeligere6f5b352008-03-18 13:51:05 -050089
90#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
91
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
93#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Andy Fleming67431052007-04-23 02:54:25 -050094
Jon Loeligere6f5b352008-03-18 13:51:05 -050095#define CONFIG_NUM_DDR_CONTROLLERS 1
96#define CONFIG_DIMM_SLOTS_PER_CTLR 1
97#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Andy Fleming67431052007-04-23 02:54:25 -050098
Jon Loeligere6f5b352008-03-18 13:51:05 -050099/* I2C addresses of SPD EEPROMs */
100#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
101
102/* Make sure required options are set */
Andy Fleming67431052007-04-23 02:54:25 -0500103#ifndef CONFIG_SPD_EEPROM
104#error ("CONFIG_SPD_EEPROM is required")
105#endif
106
107#undef CONFIG_CLOCKS_IN_MHZ
108
Andy Fleming67431052007-04-23 02:54:25 -0500109/*
110 * Local Bus Definitions
111 */
112
113/*
114 * FLASH on the Local Bus
115 * Two banks, 8M each, using the CFI driver.
116 * Boot from BR0/OR0 bank at 0xff00_0000
117 * Alternate BR1/OR1 bank at 0xff80_0000
118 *
119 * BR0, BR1:
120 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
121 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
122 * Port Size = 16 bits = BRx[19:20] = 10
123 * Use GPCM = BRx[24:26] = 000
124 * Valid = BRx[31] = 1
125 *
126 * 0 4 8 12 16 20 24 28
127 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
128 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
129 *
130 * OR0, OR1:
131 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
132 * Reserved ORx[17:18] = 11, confusion here?
133 * CSNT = ORx[20] = 1
134 * ACS = half cycle delay = ORx[21:22] = 11
135 * SCY = 6 = ORx[24:27] = 0110
136 * TRLX = use relaxed timing = ORx[29] = 1
137 * EAD = use external address latch delay = OR[31] = 1
138 *
139 * 0 4 8 12 16 20 24 28
140 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BCSR_BASE 0xf8000000
Andy Fleming67431052007-04-23 02:54:25 -0500143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
Andy Fleming67431052007-04-23 02:54:25 -0500145
146/*Chip select 0 - Flash*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_BR0_PRELIM 0xfe001001
148#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
Andy Fleming67431052007-04-23 02:54:25 -0500149
150/*Chip slelect 1 - BCSR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_BR1_PRELIM 0xf8000801
152#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
Andy Fleming67431052007-04-23 02:54:25 -0500153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
155#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
156#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
157#undef CONFIG_SYS_FLASH_CHECKSUM
158#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
159#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Andy Fleming67431052007-04-23 02:54:25 -0500160
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200161#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Andy Fleming67431052007-04-23 02:54:25 -0500162
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200163#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_CFI
165#define CONFIG_SYS_FLASH_EMPTY_INFO
Andy Fleming67431052007-04-23 02:54:25 -0500166
167
168/*
169 * SDRAM on the LocalBus
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
172#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Andy Fleming67431052007-04-23 02:54:25 -0500173
174
175/*Chip select 2 - SDRAM*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_BR2_PRELIM 0xf0001861
177#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Andy Fleming67431052007-04-23 02:54:25 -0500178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
180#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
181#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
182#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Andy Fleming67431052007-04-23 02:54:25 -0500183
184/*
Andy Fleming67431052007-04-23 02:54:25 -0500185 * Common settings for all Local Bus SDRAM commands.
186 * At run time, either BSMA1516 (for CPU 1.1)
187 * or BSMA1617 (for CPU 1.0) (old)
188 * is OR'ed in too.
189 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500190#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
191 | LSDMR_PRETOACT7 \
192 | LSDMR_ACTTORW7 \
193 | LSDMR_BL8 \
194 | LSDMR_WRC4 \
195 | LSDMR_CL3 \
196 | LSDMR_RFEN \
Andy Fleming67431052007-04-23 02:54:25 -0500197 )
198
199/*
200 * The bcsr registers are connected to CS3 on MDS.
201 * The new memory map places bcsr at 0xf8000000.
202 *
203 * For BR3, need:
204 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
205 * port-size = 8-bits = BR[19:20] = 01
206 * no parity checking = BR[21:22] = 00
207 * GPMC for MSEL = BR[24:26] = 000
208 * Valid = BR[31] = 1
209 *
210 * 0 4 8 12 16 20 24 28
211 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
212 *
213 * For OR3, need:
214 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
215 * disable buffer ctrl OR[19] = 0
216 * CSNT OR[20] = 1
217 * ACS OR[21:22] = 11
218 * XACS OR[23] = 1
219 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
220 * SETA OR[28] = 0
221 * TRLX OR[29] = 1
222 * EHTR OR[30] = 1
223 * EAD extra time OR[31] = 1
224 *
225 * 0 4 8 12 16 20 24 28
226 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_BCSR (0xf8000000)
Andy Fleming67431052007-04-23 02:54:25 -0500229
230/*Chip slelect 4 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_BR4_PRELIM 0xf8008801
232#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
Andy Fleming67431052007-04-23 02:54:25 -0500233
234/*Chip select 5 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_BR5_PRELIM 0xf8010801
236#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
Andy Fleming67431052007-04-23 02:54:25 -0500237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_INIT_RAM_LOCK 1
239#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200240#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Andy Fleming67431052007-04-23 02:54:25 -0500241
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200242#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andy Fleming67431052007-04-23 02:54:25 -0500244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
246#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Andy Fleming67431052007-04-23 02:54:25 -0500247
248/* Serial Port */
249#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_NS16550
251#define CONFIG_SYS_NS16550_SERIAL
252#define CONFIG_SYS_NS16550_REG_SIZE 1
253#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Andy Fleming67431052007-04-23 02:54:25 -0500254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_BAUDRATE_TABLE \
Andy Fleming67431052007-04-23 02:54:25 -0500256 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
259#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Andy Fleming67431052007-04-23 02:54:25 -0500260
261/* Use the HUSH parser*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_HUSH_PARSER
263#ifdef CONFIG_SYS_HUSH_PARSER
264#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Andy Fleming67431052007-04-23 02:54:25 -0500265#endif
266
267/* pass open firmware flat tree */
Kumar Galac4808612007-11-29 01:06:19 -0600268#define CONFIG_OF_LIBFDT 1
269#define CONFIG_OF_BOARD_SETUP 1
270#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Andy Fleming67431052007-04-23 02:54:25 -0500271
272/*
273 * I2C
274 */
275#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
276#define CONFIG_HARD_I2C /* I2C with hardware support*/
277#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Haiying Wangc59e4092007-06-19 14:18:34 -0400278#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
280#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
281#define CONFIG_SYS_I2C_SLAVE 0x7F
282#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
283#define CONFIG_SYS_I2C_OFFSET 0x3000
284#define CONFIG_SYS_I2C2_OFFSET 0x3100
Andy Fleming67431052007-04-23 02:54:25 -0500285
286/*
287 * General PCI
288 * Memory Addresses are mapped 1-1. I/O is mapped from 0
289 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600290#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600291#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600292#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600294#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600295#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
297#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming67431052007-04-23 02:54:25 -0500298
Kumar Gala3f6f9d72010-12-17 10:13:19 -0600299#define CONFIG_SYS_PCIE1_NAME "Slot"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600300#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600301#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600302#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600304#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600305#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
307#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming67431052007-04-23 02:54:25 -0500308
Kumar Gala5f7bbd12011-01-04 18:01:49 -0600309#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
310#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
311#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
312#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Andy Fleming67431052007-04-23 02:54:25 -0500313
Andy Flemingda9d4612007-08-14 00:14:25 -0500314#ifdef CONFIG_QE
315/*
316 * QE UEC ethernet configuration
317 */
318#define CONFIG_UEC_ETH
319#ifndef CONFIG_TSEC_ENET
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500320#define CONFIG_ETHPRIME "UEC0"
Andy Flemingda9d4612007-08-14 00:14:25 -0500321#endif
322#define CONFIG_PHY_MODE_NEED_CHANGE
323#define CONFIG_eTSEC_MDIO_BUS
324
325#ifdef CONFIG_eTSEC_MDIO_BUS
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200326#define CONFIG_MIIM_ADDRESS 0xE0024520
Andy Flemingda9d4612007-08-14 00:14:25 -0500327#endif
328
329#define CONFIG_UEC_ETH1 /* GETH1 */
330
331#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
333#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
334#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
335#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
336#define CONFIG_SYS_UEC1_PHY_ADDR 7
Andy Fleming865ff852011-04-13 00:37:12 -0500337#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100338#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Andy Flemingda9d4612007-08-14 00:14:25 -0500339#endif
340
341#define CONFIG_UEC_ETH2 /* GETH2 */
342
343#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
345#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
346#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
347#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
348#define CONFIG_SYS_UEC2_PHY_ADDR 1
Andy Fleming865ff852011-04-13 00:37:12 -0500349#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100350#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Andy Flemingda9d4612007-08-14 00:14:25 -0500351#endif
352#endif /* CONFIG_QE */
353
Haiying Wangf30ad492007-11-19 10:02:13 -0500354#if defined(CONFIG_PCI)
355
356#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200357#define CONFIG_PCI_PNP /* do pci plug-and-play */
Haiying Wangf30ad492007-11-19 10:02:13 -0500358
Andy Fleming67431052007-04-23 02:54:25 -0500359#undef CONFIG_EEPRO100
360#undef CONFIG_TULIP
361
362#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Andy Fleming67431052007-04-23 02:54:25 -0500364
365#endif /* CONFIG_PCI */
366
Andy Fleming67431052007-04-23 02:54:25 -0500367#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200368#define CONFIG_NET_MULTI 1
Andy Fleming67431052007-04-23 02:54:25 -0500369#endif
370
Andy Flemingda9d4612007-08-14 00:14:25 -0500371#if defined(CONFIG_TSEC_ENET)
372
Andy Fleming67431052007-04-23 02:54:25 -0500373#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500374#define CONFIG_TSEC1 1
375#define CONFIG_TSEC1_NAME "eTSEC0"
376#define CONFIG_TSEC2 1
377#define CONFIG_TSEC2_NAME "eTSEC1"
Andy Fleming67431052007-04-23 02:54:25 -0500378
379#define TSEC1_PHY_ADDR 2
380#define TSEC2_PHY_ADDR 3
381
382#define TSEC1_PHYIDX 0
383#define TSEC2_PHYIDX 0
384
Andy Fleming3a790132007-08-15 20:03:25 -0500385#define TSEC1_FLAGS TSEC_GIGABIT
386#define TSEC2_FLAGS TSEC_GIGABIT
387
Andy Flemingb96c83d2007-08-15 20:03:34 -0500388/* Options are: eTSEC[0-1] */
Andy Fleming67431052007-04-23 02:54:25 -0500389#define CONFIG_ETHPRIME "eTSEC0"
390
391#endif /* CONFIG_TSEC_ENET */
392
393/*
394 * Environment
395 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200396#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200398#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
399#define CONFIG_ENV_SIZE 0x2000
Andy Fleming67431052007-04-23 02:54:25 -0500400
401#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Andy Fleming67431052007-04-23 02:54:25 -0500403
Jon Loeliger2835e512007-06-13 13:22:08 -0500404
405/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500406 * BOOTP options
407 */
408#define CONFIG_BOOTP_BOOTFILESIZE
409#define CONFIG_BOOTP_BOOTPATH
410#define CONFIG_BOOTP_GATEWAY
411#define CONFIG_BOOTP_HOSTNAME
412
413
414/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500415 * Command line configuration.
416 */
417#include <config_cmd_default.h>
418
419#define CONFIG_CMD_PING
420#define CONFIG_CMD_I2C
421#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600422#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500423#define CONFIG_CMD_IRQ
424#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500425#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500426
Andy Fleming67431052007-04-23 02:54:25 -0500427#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500428 #define CONFIG_CMD_PCI
Andy Fleming67431052007-04-23 02:54:25 -0500429#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500430
Andy Fleming67431052007-04-23 02:54:25 -0500431
432#undef CONFIG_WATCHDOG /* watchdog disabled */
433
434/*
435 * Miscellaneous configurable options
436 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500438#define CONFIG_CMDLINE_EDITING /* Command-line editing */
439#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
441#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500442#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500444#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500446#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
448#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
449#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
450#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Andy Fleming67431052007-04-23 02:54:25 -0500451
452/*
453 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500454 * have to be in the first 64 MB of memory, since this is
Andy Fleming67431052007-04-23 02:54:25 -0500455 * the maximum mapped by the Linux kernel during initialization.
456 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500457#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
458#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Andy Fleming67431052007-04-23 02:54:25 -0500459
Jon Loeliger2835e512007-06-13 13:22:08 -0500460#if defined(CONFIG_CMD_KGDB)
Andy Fleming67431052007-04-23 02:54:25 -0500461#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
462#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
463#endif
464
465/*
466 * Environment Configuration
467 */
468
469/* The mac addresses for all ethernet interface */
Andy Flemingda9d4612007-08-14 00:14:25 -0500470#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
471#define CONFIG_HAS_ETH0
Andy Fleming67431052007-04-23 02:54:25 -0500472#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
473#define CONFIG_HAS_ETH1
474#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
475#define CONFIG_HAS_ETH2
476#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Andy Flemingda9d4612007-08-14 00:14:25 -0500477#define CONFIG_HAS_ETH3
478#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
Andy Fleming67431052007-04-23 02:54:25 -0500479#endif
480
481#define CONFIG_IPADDR 192.168.1.253
482
483#define CONFIG_HOSTNAME unknown
484#define CONFIG_ROOTPATH /nfsroot
485#define CONFIG_BOOTFILE your.uImage
486
487#define CONFIG_SERVERIP 192.168.1.1
488#define CONFIG_GATEWAYIP 192.168.1.1
489#define CONFIG_NETMASK 255.255.255.0
490
491#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
492
493#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
494#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
495
496#define CONFIG_BAUDRATE 115200
497
498#define CONFIG_EXTRA_ENV_SETTINGS \
499 "netdev=eth0\0" \
500 "consoledev=ttyS0\0" \
501 "ramdiskaddr=600000\0" \
502 "ramdiskfile=your.ramdisk.u-boot\0" \
503 "fdtaddr=400000\0" \
504 "fdtfile=your.fdt.dtb\0" \
505 "nfsargs=setenv bootargs root=/dev/nfs rw " \
506 "nfsroot=$serverip:$rootpath " \
507 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
508 "console=$consoledev,$baudrate $othbootargs\0" \
509 "ramargs=setenv bootargs root=/dev/ram rw " \
510 "console=$consoledev,$baudrate $othbootargs\0" \
511
512
513#define CONFIG_NFSBOOTCOMMAND \
514 "run nfsargs;" \
515 "tftp $loadaddr $bootfile;" \
516 "tftp $fdtaddr $fdtfile;" \
517 "bootm $loadaddr - $fdtaddr"
518
519
520#define CONFIG_RAMBOOTCOMMAND \
521 "run ramargs;" \
522 "tftp $ramdiskaddr $ramdiskfile;" \
523 "tftp $loadaddr $bootfile;" \
524 "bootm $loadaddr $ramdiskaddr"
525
526#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
527
528#endif /* __CONFIG_H */