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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a87273bc4085854584a19abb65da7562c0967f9e / . / arch / arm / dts / ast2600.dtsi
blob: 4b23d25ede0a5ded83b3530e97dcf6f9000c84ba [file] [log] [blame]
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
Billy Tsai5b66ebb2022-03-08 11:04:07 +0800[diff] [blame]116 pwm_tach: pwm_tach@1e610000 {
117 compatible = "aspeed,ast2600-pwm-tach", "simple-mfd", "syscon";
118 reg = <0x1e610000 0x100>;
119 clocks = <&scu ASPEED_CLK_AHB>;
120 resets = <&rst ASPEED_RESET_PWM>;
121
122 pwm: pwm {
123 compatible = "aspeed,ast2600-pwm";
124 #pwm-cells = <3>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127 status = "disabled";
128 };
129 };
130
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]131 fmc: flash-controller@1e620000 {
132 reg = < 0x1e620000 0xc4
133 0x20000000 0x10000000 >;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "aspeed,ast2600-fmc";
137 status = "disabled";
138 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&scu ASPEED_CLK_AHB>;
140 num-cs = <3>;
141 flash@0 {
142 reg = < 0 >;
143 compatible = "jedec,spi-nor";
144 status = "disabled";
145 };
146 flash@1 {
147 reg = < 1 >;
148 compatible = "jedec,spi-nor";
149 status = "disabled";
150 };
151 flash@2 {
152 reg = < 2 >;
153 compatible = "jedec,spi-nor";
154 status = "disabled";
155 };
156 };
157
158 spi1: flash-controller@1e630000 {
159 reg = < 0x1e630000 0xc4
160 0x30000000 0x08000000 >;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "aspeed,ast2600-spi";
164 clocks = <&scu ASPEED_CLK_AHB>;
165 num-cs = <2>;
166 status = "disabled";
167 flash@0 {
168 reg = < 0 >;
169 compatible = "jedec,spi-nor";
170 status = "disabled";
171 };
172 flash@1 {
173 reg = < 1 >;
174 compatible = "jedec,spi-nor";
175 status = "disabled";
176 };
177 };
178
179 spi2: flash-controller@1e631000 {
180 reg = < 0x1e631000 0xc4
181 0x50000000 0x08000000 >;
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "aspeed,ast2600-spi";
185 clocks = <&scu ASPEED_CLK_AHB>;
186 num-cs = <3>;
187 status = "disabled";
188 flash@0 {
189 reg = < 0 >;
190 compatible = "jedec,spi-nor";
191 status = "disabled";
192 };
193 flash@1 {
194 reg = < 1 >;
195 compatible = "jedec,spi-nor";
196 status = "disabled";
197 };
198 flash@2 {
199 reg = < 2 >;
200 compatible = "jedec,spi-nor";
201 status = "disabled";
202 };
203 };
204
Joel Stanleya2f16d02021-10-27 14:17:28 +0800[diff] [blame]205 hace: hace@1e6d0000 {
206 compatible = "aspeed,ast2600-hace";
207 reg = <0x1e6d0000 0x200>;
208 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&scu ASPEED_CLK_GATE_YCLK>;
210 status = "disabled";
211 };
212
Chia-Wei Wangf0552272021-10-27 14:17:31 +0800[diff] [blame]213 acry: acry@1e6fa000 {
214 compatible = "aspeed,ast2600-acry";
215 reg = <0x1e6fa000 0x1000>,
216 <0x1e710000 0x10000>;
217 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
219 status = "disabled";
220 };
221
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]222 edac: sdram@1e6e0000 {
223 compatible = "aspeed,ast2600-sdram-edac";
224 reg = <0x1e6e0000 0x174>;
225 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
226 };
227
Dylan Hungabc75892021-12-09 10:12:26 +0800[diff] [blame]228 mdio: bus@1e650000 {
229 compatible = "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0 0x1e650000 0x100>;
233
234 mdio0: mdio@0 {
235 compatible = "aspeed,ast2600-mdio";
236 reg = <0 0x8>;
237 resets = <&rst ASPEED_RESET_MII>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_mdio1_default>;
240 status = "disabled";
241 };
242
243 mdio1: mdio@8 {
244 compatible = "aspeed,ast2600-mdio";
245 reg = <0x8 0x8>;
246 resets = <&rst ASPEED_RESET_MII>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_mdio2_default>;
249 status = "disabled";
250 };
251
252 mdio2: mdio@10 {
253 compatible = "aspeed,ast2600-mdio";
254 reg = <0x10 0x8>;
255 resets = <&rst ASPEED_RESET_MII>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_mdio3_default>;
258 status = "disabled";
259 };
260
261 mdio3: mdio@18 {
262 compatible = "aspeed,ast2600-mdio";
263 reg = <0x18 0x8>;
264 resets = <&rst ASPEED_RESET_MII>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_mdio4_default>;
267 status = "disabled";
268 };
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]269 };
270
271 mac0: ftgmac@1e660000 {
272 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
273 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
274 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
276 status = "disabled";
277 };
278
279 mac1: ftgmac@1e680000 {
280 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
281 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
286 status = "disabled";
287 };
288
289 mac2: ftgmac@1e670000 {
290 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
291 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
296 status = "disabled";
297 };
298
299 mac3: ftgmac@1e690000 {
300 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
301 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
306 status = "disabled";
307 };
308
309 ehci0: usb@1e6a1000 {
310 compatible = "aspeed,aspeed-ehci", "usb-ehci";
311 reg = <0x1e6a1000 0x100>;
312 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usb2ah_default>;
316 status = "disabled";
317 };
318
319 ehci1: usb@1e6a3000 {
320 compatible = "aspeed,aspeed-ehci", "usb-ehci";
321 reg = <0x1e6a3000 0x100>;
322 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_usb2bh_default>;
326 status = "disabled";
327 };
328
329 apb {
330 compatible = "simple-bus";
331 #address-cells = <1>;
332 #size-cells = <1>;
333 ranges;
334
335 syscon: syscon@1e6e2000 {
336 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
337 reg = <0x1e6e2000 0x1000>;
338 #address-cells = <1>;
339 #size-cells = <1>;
340 #clock-cells = <1>;
341 #reset-cells = <1>;
342 ranges = <0 0x1e6e2000 0x1000>;
343
344 pinctrl: pinctrl {
345 compatible = "aspeed,g6-pinctrl";
346 aspeed,external-nodes = <&gfx &lhc>;
347
348 };
349
350 vga_scratch: scratch {
351 compatible = "aspeed,bmc-misc";
352 };
353
354 scu_ic0: interrupt-controller@0 {
355 #interrupt-cells = <1>;
356 compatible = "aspeed,ast2600-scu-ic";
357 reg = <0x560 0x10>;
358 interrupt-parent = <&gic>;
359 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-controller;
361 };
362
363 scu_ic1: interrupt-controller@1 {
364 #interrupt-cells = <1>;
365 compatible = "aspeed,ast2600-scu-ic";
366 reg = <0x570 0x10>;
367 interrupt-parent = <&gic>;
368 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-controller;
370 };
371
372 };
373
374 smp-memram@0 {
375 compatible = "aspeed,ast2600-smpmem", "syscon";
376 reg = <0x1e6e2180 0x40>;
377 };
378
379 gfx: display@1e6e6000 {
380 compatible = "aspeed,ast2500-gfx", "syscon";
381 reg = <0x1e6e6000 0x1000>;
382 reg-io-width = <4>;
383 };
384
385 pcie_bridge0: pcie@1e6ed000 {
386 compatible = "aspeed,ast2600-pcie";
387 #address-cells = <3>;
388 #size-cells = <2>;
389 reg = <0x1e6ed000 0x100>;
390 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
391 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
392 device_type = "pci";
393 bus-range = <0x00 0xff>;
394 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
395 cfg-handle = <&pcie_cfg0>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_pcie0rc_default>;
398
399 status = "disabled";
400 };
401
402 pcie_bridge1: pcie@1e6ed200 {
403 compatible = "aspeed,ast2600-pcie";
404 #address-cells = <3>;
405 #size-cells = <2>;
406 reg = <0x1e6ed200 0x100>;
407 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
408 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
409 device_type = "pci";
410 bus-range = <0x00 0xff>;
411 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
412 cfg-handle = <&pcie_cfg1>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_pcie1rc_default>;
415
416 status = "disabled";
417 };
418
419 sdhci: sdhci@1e740000 {
420 #interrupt-cells = <1>;
421 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
422 reg = <0x1e740000 0x1000>;
423 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-controller;
425 clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
426 <&scu ASPEED_CLK_GATE_SDEXTCLK>;
427 clock-names = "ctrlclk", "extclk";
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0x1e740000 0x1000>;
431
432 sdhci_slot0: sdhci_slot0@100 {
433 compatible = "aspeed,sdhci-ast2600";
434 reg = <0x100 0x100>;
435 interrupts = <0>;
436 interrupt-parent = <&sdhci>;
437 sdhci,auto-cmd12;
438 clocks = <&scu ASPEED_CLK_SDIO>;
439 status = "disabled";
440 };
441
442 sdhci_slot1: sdhci_slot1@200 {
443 compatible = "aspeed,sdhci-ast2600";
444 reg = <0x200 0x100>;
445 interrupts = <1>;
446 interrupt-parent = <&sdhci>;
447 sdhci,auto-cmd12;
448 clocks = <&scu ASPEED_CLK_SDIO>;
449 status = "disabled";
450 };
451 };
452
453 emmc: emmc@1e750000 {
454 #interrupt-cells = <1>;
455 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
456 reg = <0x1e750000 0x1000>;
457 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-controller;
459 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
460 <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
461 clock-names = "ctrlclk", "extclk";
462 #address-cells = <1>;
463 #size-cells = <1>;
464 ranges = <0x0 0x1e750000 0x1000>;
465
466 emmc_slot0: emmc_slot0@100 {
467 compatible = "aspeed,emmc-ast2600";
468 reg = <0x100 0x100>;
469 interrupts = <0>;
470 interrupt-parent = <&emmc>;
471 clocks = <&scu ASPEED_CLK_EMMC>;
472 status = "disabled";
473 };
474 };
475
476 h2x: h2x@1e770000 {
477 compatible = "aspeed,ast2600-h2x";
478 reg = <0x1e770000 0x100>;
479 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
480 resets = <&rst ASPEED_RESET_H2X>;
481 #address-cells = <1>;
482 #size-cells = <1>;
483 ranges = <0x0 0x1e770000 0x100>;
484
485 status = "disabled";
486
487 pcie_cfg0: cfg0@80 {
488 reg = <0x80 0x80>;
489 compatible = "aspeed,ast2600-pcie-cfg";
490 };
491
492 pcie_cfg1: cfg1@C0 {
493 compatible = "aspeed,ast2600-pcie-cfg";
494 reg = <0xC0 0x80>;
495 };
496 };
497
498 gpio0: gpio@1e780000 {
499 compatible = "aspeed,ast2600-gpio";
500 reg = <0x1e780000 0x1000>;
501 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
502 #gpio-cells = <2>;
503 gpio-controller;
504 interrupt-controller;
505 gpio-ranges = <&pinctrl 0 0 220>;
506 ngpios = <208>;
507 };
508
509 gpio1: gpio@1e780800 {
510 compatible = "aspeed,ast2600-gpio";
511 reg = <0x1e780800 0x800>;
512 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
513 #gpio-cells = <2>;
514 gpio-controller;
515 interrupt-controller;
516 gpio-ranges = <&pinctrl 0 0 208>;
517 ngpios = <36>;
518 };
519
520 uart1: serial@1e783000 {
521 compatible = "ns16550a";
522 reg = <0x1e783000 0x20>;
523 reg-shift = <2>;
524 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
526 clock-frequency = <1846154>;
527 no-loopback-test;
528 status = "disabled";
529 };
530
531 uart5: serial@1e784000 {
532 compatible = "ns16550a";
533 reg = <0x1e784000 0x1000>;
534 reg-shift = <2>;
535 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
537 clock-frequency = <1846154>;
538 no-loopback-test;
539 status = "disabled";
540 };
541
542 wdt1: watchdog@1e785000 {
543 compatible = "aspeed,ast2600-wdt";
544 reg = <0x1e785000 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]545 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]546 };
547
548 wdt2: watchdog@1e785040 {
549 compatible = "aspeed,ast2600-wdt";
550 reg = <0x1e785040 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]551 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]552 };
553
554 wdt3: watchdog@1e785080 {
555 compatible = "aspeed,ast2600-wdt";
556 reg = <0x1e785080 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]557 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]558 };
559
560 wdt4: watchdog@1e7850C0 {
561 compatible = "aspeed,ast2600-wdt";
562 reg = <0x1e7850C0 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]563 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]564 };
565
566 lpc: lpc@1e789000 {
567 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
568 reg = <0x1e789000 0x1000>;
569
570 #address-cells = <1>;
571 #size-cells = <1>;
572 ranges = <0x0 0x1e789000 0x1000>;
573
574 kcs1: kcs1@0 {
575 compatible = "aspeed,ast2600-kcs-bmc";
576 reg = <0x0 0x80>;
577 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
578 kcs_chan = <1>;
579 kcs_addr = <0xCA0>;
580 status = "disabled";
581 };
582
583 kcs2: kcs2@0 {
584 compatible = "aspeed,ast2600-kcs-bmc";
585 reg = <0x0 0x80>;
586 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
587 kcs_chan = <2>;
588 kcs_addr = <0xCA8>;
589 status = "disabled";
590 };
591
592 kcs3: kcs3@0 {
593 compatible = "aspeed,ast2600-kcs-bmc";
594 reg = <0x0 0x80>;
595 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
596 kcs_chan = <3>;
597 kcs_addr = <0xCA2>;
598 };
599
600 kcs4: kcs4@0 {
601 compatible = "aspeed,ast2600-kcs-bmc";
602 reg = <0x0 0x120>;
603 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
604 kcs_chan = <4>;
605 kcs_addr = <0xCA4>;
606 status = "disabled";
607 };
608
609 lpc_ctrl: lpc-ctrl@80 {
610 compatible = "aspeed,ast2600-lpc-ctrl";
611 reg = <0x80 0x80>;
612 status = "disabled";
613 };
614
615 lpc_snoop: lpc-snoop@80 {
616 compatible = "aspeed,ast2600-lpc-snoop";
617 reg = <0x80 0x80>;
618 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
619 status = "disabled";
620 };
621
622 lhc: lhc@a0 {
623 compatible = "aspeed,ast2600-lhc";
624 reg = <0xa0 0x24 0xc8 0x8>;
625 };
626
627 lpc_reset: reset-controller@98 {
628 compatible = "aspeed,ast2600-lpc-reset";
629 reg = <0x98 0x4>;
630 #reset-cells = <1>;
631 status = "disabled";
632 };
633
634 ibt: ibt@140 {
635 compatible = "aspeed,ast2600-ibt-bmc";
636 reg = <0x140 0x18>;
637 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
638 status = "disabled";
639 };
640
641 sio_regs: regs {
642 compatible = "aspeed,bmc-misc";
643 };
644
645 mbox: mbox@200 {
646 compatible = "aspeed,ast2600-mbox";
647 reg = <0x200 0x5c>;
648 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
649 #mbox-cells = <1>;
650 status = "disabled";
651 };
652 };
653
654 uart2: serial@1e78d000 {
655 compatible = "ns16550a";
656 reg = <0x1e78d000 0x20>;
657 reg-shift = <2>;
658 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
660 clock-frequency = <1846154>;
661 no-loopback-test;
662 status = "disabled";
663 };
664
665 uart3: serial@1e78e000 {
666 compatible = "ns16550a";
667 reg = <0x1e78e000 0x20>;
668 reg-shift = <2>;
669 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
671 clock-frequency = <1846154>;
672 no-loopback-test;
673 status = "disabled";
674 };
675
676 uart4: serial@1e78f000 {
677 compatible = "ns16550a";
678 reg = <0x1e78f000 0x20>;
679 reg-shift = <2>;
680 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
682 clock-frequency = <1846154>;
683 no-loopback-test;
684 status = "disabled";
685 };
686
687 i2c: bus@1e78a000 {
688 compatible = "simple-bus";
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0 0x1e78a000 0x1000>;
692 };
693
694 fsim0: fsi@1e79b000 {
695 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
696 reg = <0x1e79b000 0x94>;
697 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_fsi1_default>;
700 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
701 status = "disabled";
702 };
703
704 fsim1: fsi@1e79b100 {
705 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
706 reg = <0x1e79b100 0x94>;
707 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&pinctrl_fsi2_default>;
710 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
711 status = "disabled";
712 };
713
714 uart6: serial@1e790000 {
715 compatible = "ns16550a";
716 reg = <0x1e790000 0x20>;
717 reg-shift = <2>;
718 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
720 clock-frequency = <1846154>;
721 no-loopback-test;
722 status = "disabled";
723 };
724
725 uart7: serial@1e790100 {
726 compatible = "ns16550a";
727 reg = <0x1e790100 0x20>;
728 reg-shift = <2>;
729 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
731 clock-frequency = <1846154>;
732 no-loopback-test;
733 status = "disabled";
734 };
735
736 uart8: serial@1e790200 {
737 compatible = "ns16550a";
738 reg = <0x1e790200 0x20>;
739 reg-shift = <2>;
740 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
742 clock-frequency = <1846154>;
743 no-loopback-test;
744 status = "disabled";
745 };
746
747 uart9: serial@1e790300 {
748 compatible = "ns16550a";
749 reg = <0x1e790300 0x20>;
750 reg-shift = <2>;
751 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
753 clock-frequency = <1846154>;
754 no-loopback-test;
755 status = "disabled";
756 };
757
758 uart10: serial@1e790400 {
759 compatible = "ns16550a";
760 reg = <0x1e790400 0x20>;
761 reg-shift = <2>;
762 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
764 clock-frequency = <1846154>;
765 no-loopback-test;
766 status = "disabled";
767 };
768
769 uart11: serial@1e790500 {
770 compatible = "ns16550a";
771 reg = <0x1e790400 0x20>;
772 reg-shift = <2>;
773 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
775 clock-frequency = <1846154>;
776 no-loopback-test;
777 status = "disabled";
778 };
779
780 uart12: serial@1e790600 {
781 compatible = "ns16550a";
782 reg = <0x1e790600 0x20>;
783 reg-shift = <2>;
784 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
786 clock-frequency = <1846154>;
787 no-loopback-test;
788 status = "disabled";
789 };
790
791 uart13: serial@1e790700 {
792 compatible = "ns16550a";
793 reg = <0x1e790700 0x20>;
794 reg-shift = <2>;
795 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
797 clock-frequency = <1846154>;
798 no-loopback-test;
799 status = "disabled";
800 };
801
802 display_port: dp@1e6eb000 {
803 compatible = "aspeed,ast2600-displayport";
804 reg = <0x1e6eb000 0x200>;
805 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
806 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
807 status = "disabled";
808 };
809
810 };
811
812 };
813
814};
815
816&i2c {
817 i2cglobal: i2cg@00 {
818 compatible = "aspeed,ast2600-i2c-global";
819 reg = <0x0 0x40>;
820 resets = <&rst ASPEED_RESET_I2C>;
821#if 0
822 new-mode;
823#endif
824 };
825
826 i2c0: i2c@80 {
827 #address-cells = <1>;
828 #size-cells = <0>;
829 #interrupt-cells = <1>;
830
831 reg = <0x80 0x80 0xC00 0x20>;
832 compatible = "aspeed,ast2600-i2c-bus";
833 bus-frequency = <100000>;
834 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]835 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]836 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]837 pinctrl-names = "default";
838 pinctrl-0 = <&pinctrl_i2c1_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]839 status = "disabled";
840 };
841
842 i2c1: i2c@100 {
843 #address-cells = <1>;
844 #size-cells = <0>;
845 #interrupt-cells = <1>;
846
847 reg = <0x100 0x80 0xC20 0x20>;
848 compatible = "aspeed,ast2600-i2c-bus";
849 bus-frequency = <100000>;
850 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]851 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]852 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]853 pinctrl-names = "default";
854 pinctrl-0 = <&pinctrl_i2c2_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]855 status = "disabled";
856 };
857
858 i2c2: i2c@180 {
859 #address-cells = <1>;
860 #size-cells = <0>;
861 #interrupt-cells = <1>;
862
863 reg = <0x180 0x80 0xC40 0x20>;
864 compatible = "aspeed,ast2600-i2c-bus";
865 bus-frequency = <100000>;
866 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]867 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]868 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]869 pinctrl-names = "default";
870 pinctrl-0 = <&pinctrl_i2c3_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]871 };
872
873 i2c3: i2c@200 {
874 #address-cells = <1>;
875 #size-cells = <0>;
876 #interrupt-cells = <1>;
877
878 reg = <0x200 0x40 0xC60 0x20>;
879 compatible = "aspeed,ast2600-i2c-bus";
880 bus-frequency = <100000>;
881 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]882 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]883 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]884 pinctrl-names = "default";
885 pinctrl-0 = <&pinctrl_i2c4_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]886 };
887
888 i2c4: i2c@280 {
889 #address-cells = <1>;
890 #size-cells = <0>;
891 #interrupt-cells = <1>;
892
893 reg = <0x280 0x80 0xC80 0x20>;
894 compatible = "aspeed,ast2600-i2c-bus";
895 bus-frequency = <100000>;
896 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]897 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]898 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]899 pinctrl-names = "default";
900 pinctrl-0 = <&pinctrl_i2c5_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]901 };
902
903 i2c5: i2c@300 {
904 #address-cells = <1>;
905 #size-cells = <0>;
906 #interrupt-cells = <1>;
907
908 reg = <0x300 0x40 0xCA0 0x20>;
909 compatible = "aspeed,ast2600-i2c-bus";
910 bus-frequency = <100000>;
911 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]912 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]913 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]914 pinctrl-names = "default";
915 pinctrl-0 = <&pinctrl_i2c6_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]916 };
917
918 i2c6: i2c@380 {
919 #address-cells = <1>;
920 #size-cells = <0>;
921 #interrupt-cells = <1>;
922
923 reg = <0x380 0x80 0xCC0 0x20>;
924 compatible = "aspeed,ast2600-i2c-bus";
925 bus-frequency = <100000>;
926 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]927 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]928 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]929 pinctrl-names = "default";
930 pinctrl-0 = <&pinctrl_i2c7_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]931 };
932
933 i2c7: i2c@400 {
934 #address-cells = <1>;
935 #size-cells = <0>;
936 #interrupt-cells = <1>;
937
938 reg = <0x400 0x80 0xCE0 0x20>;
939 compatible = "aspeed,ast2600-i2c-bus";
940 bus-frequency = <100000>;
941 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]942 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]943 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]944 pinctrl-names = "default";
945 pinctrl-0 = <&pinctrl_i2c8_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]946 };
947
948 i2c8: i2c@480 {
949 #address-cells = <1>;
950 #size-cells = <0>;
951 #interrupt-cells = <1>;
952
953 reg = <0x480 0x80 0xD00 0x20>;
954 compatible = "aspeed,ast2600-i2c-bus";
955 bus-frequency = <100000>;
956 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]957 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]958 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]959 pinctrl-names = "default";
960 pinctrl-0 = <&pinctrl_i2c9_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]961 };
962
963 i2c9: i2c@500 {
964 #address-cells = <1>;
965 #size-cells = <0>;
966 #interrupt-cells = <1>;
967
968 reg = <0x500 0x80 0xD20 0x20>;
969 compatible = "aspeed,ast2600-i2c-bus";
970 bus-frequency = <100000>;
971 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]972 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]973 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]974 pinctrl-names = "default";
975 pinctrl-0 = <&pinctrl_i2c10_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]976 status = "disabled";
977 };
978
979 i2c10: i2c@580 {
980 #address-cells = <1>;
981 #size-cells = <0>;
982 #interrupt-cells = <1>;
983
984 reg = <0x580 0x80 0xD40 0x20>;
985 compatible = "aspeed,ast2600-i2c-bus";
986 bus-frequency = <100000>;
987 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]988 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]989 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]990 pinctrl-names = "default";
991 pinctrl-0 = <&pinctrl_i2c11_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]992 status = "disabled";
993 };
994
995 i2c11: i2c@600 {
996 #address-cells = <1>;
997 #size-cells = <0>;
998 #interrupt-cells = <1>;
999
1000 reg = <0x600 0x80 0xD60 0x20>;
1001 compatible = "aspeed,ast2600-i2c-bus";
1002 bus-frequency = <100000>;
1003 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]1004 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1005 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]1006 pinctrl-names = "default";
1007 pinctrl-0 = <&pinctrl_i2c12_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1008 status = "disabled";
1009 };
1010
1011 i2c12: i2c@680 {
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 #interrupt-cells = <1>;
1015
1016 reg = <0x680 0x80 0xD80 0x20>;
1017 compatible = "aspeed,ast2600-i2c-bus";
1018 bus-frequency = <100000>;
1019 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]1020 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1021 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]1022 pinctrl-names = "default";
1023 pinctrl-0 = <&pinctrl_i2c13_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1024 status = "disabled";
1025 };
1026
1027 i2c13: i2c@700 {
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 #interrupt-cells = <1>;
1031
1032 reg = <0x700 0x80 0xDA0 0x20>;
1033 compatible = "aspeed,ast2600-i2c-bus";
1034 bus-frequency = <100000>;
1035 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]1036 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1037 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]1038 pinctrl-names = "default";
1039 pinctrl-0 = <&pinctrl_i2c14_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1040 status = "disabled";
1041 };
1042
1043 i2c14: i2c@780 {
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046 #interrupt-cells = <1>;
1047
1048 reg = <0x780 0x80 0xDC0 0x20>;
1049 compatible = "aspeed,ast2600-i2c-bus";
1050 bus-frequency = <100000>;
1051 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]1052 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1053 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]1054 pinctrl-names = "default";
1055 pinctrl-0 = <&pinctrl_i2c15_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1056 status = "disabled";
1057 };
1058
1059 i2c15: i2c@800 {
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1062 #interrupt-cells = <1>;
1063
1064 reg = <0x800 0x80 0xDE0 0x20>;
1065 compatible = "aspeed,ast2600-i2c-bus";
1066 bus-frequency = <100000>;
1067 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanleya87273b2022-06-23 14:40:32 +0930[diff] [blame^]1068 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1069 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]1070 pinctrl-names = "default";
1071 pinctrl-0 = <&pinctrl_i2c16_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1072 status = "disabled";
1073 };
1074
1075};
1076
1077&pinctrl {
1078 pinctrl_fmcquad_default: fmcquad_default {
1079 function = "FMCQUAD";
1080 groups = "FMCQUAD";
1081 };
1082
1083 pinctrl_spi1_default: spi1_default {
1084 function = "SPI1";
1085 groups = "SPI1";
1086 };
1087
1088 pinctrl_spi1abr_default: spi1abr_default {
1089 function = "SPI1ABR";
1090 groups = "SPI1ABR";
1091 };
1092
1093 pinctrl_spi1cs1_default: spi1cs1_default {
1094 function = "SPI1CS1";
1095 groups = "SPI1CS1";
1096 };
1097
1098 pinctrl_spi1wp_default: spi1wp_default {
1099 function = "SPI1WP";
1100 groups = "SPI1WP";
1101 };
1102
1103 pinctrl_spi1quad_default: spi1quad_default {
1104 function = "SPI1QUAD";
1105 groups = "SPI1QUAD";
1106 };
1107
1108 pinctrl_spi2_default: spi2_default {
1109 function = "SPI2";
1110 groups = "SPI2";
1111 };
1112
1113 pinctrl_spi2cs1_default: spi2cs1_default {
1114 function = "SPI2CS1";
1115 groups = "SPI2CS1";
1116 };
1117
1118 pinctrl_spi2cs2_default: spi2cs2_default {
1119 function = "SPI2CS2";
1120 groups = "SPI2CS2";
1121 };
1122
1123 pinctrl_spi2quad_default: spi2quad_default {
1124 function = "SPI2QUAD";
1125 groups = "SPI2QUAD";
1126 };
1127
1128 pinctrl_acpi_default: acpi_default {
1129 function = "ACPI";
1130 groups = "ACPI";
1131 };
1132
1133 pinctrl_adc0_default: adc0_default {
1134 function = "ADC0";
1135 groups = "ADC0";
1136 };
1137
1138 pinctrl_adc1_default: adc1_default {
1139 function = "ADC1";
1140 groups = "ADC1";
1141 };
1142
1143 pinctrl_adc10_default: adc10_default {
1144 function = "ADC10";
1145 groups = "ADC10";
1146 };
1147
1148 pinctrl_adc11_default: adc11_default {
1149 function = "ADC11";
1150 groups = "ADC11";
1151 };
1152
1153 pinctrl_adc12_default: adc12_default {
1154 function = "ADC12";
1155 groups = "ADC12";
1156 };
1157
1158 pinctrl_adc13_default: adc13_default {
1159 function = "ADC13";
1160 groups = "ADC13";
1161 };
1162
1163 pinctrl_adc14_default: adc14_default {
1164 function = "ADC14";
1165 groups = "ADC14";
1166 };
1167
1168 pinctrl_adc15_default: adc15_default {
1169 function = "ADC15";
1170 groups = "ADC15";
1171 };
1172
1173 pinctrl_adc2_default: adc2_default {
1174 function = "ADC2";
1175 groups = "ADC2";
1176 };
1177
1178 pinctrl_adc3_default: adc3_default {
1179 function = "ADC3";
1180 groups = "ADC3";
1181 };
1182
1183 pinctrl_adc4_default: adc4_default {
1184 function = "ADC4";
1185 groups = "ADC4";
1186 };
1187
1188 pinctrl_adc5_default: adc5_default {
1189 function = "ADC5";
1190 groups = "ADC5";
1191 };
1192
1193 pinctrl_adc6_default: adc6_default {
1194 function = "ADC6";
1195 groups = "ADC6";
1196 };
1197
1198 pinctrl_adc7_default: adc7_default {
1199 function = "ADC7";
1200 groups = "ADC7";
1201 };
1202
1203 pinctrl_adc8_default: adc8_default {
1204 function = "ADC8";
1205 groups = "ADC8";
1206 };
1207
1208 pinctrl_adc9_default: adc9_default {
1209 function = "ADC9";
1210 groups = "ADC9";
1211 };
1212
1213 pinctrl_bmcint_default: bmcint_default {
1214 function = "BMCINT";
1215 groups = "BMCINT";
1216 };
1217
1218 pinctrl_ddcclk_default: ddcclk_default {
1219 function = "DDCCLK";
1220 groups = "DDCCLK";
1221 };
1222
1223 pinctrl_ddcdat_default: ddcdat_default {
1224 function = "DDCDAT";
1225 groups = "DDCDAT";
1226 };
1227
1228 pinctrl_espi_default: espi_default {
1229 function = "ESPI";
1230 groups = "ESPI";
1231 };
1232
1233 pinctrl_fsi1_default: fsi1_default {
1234 function = "FSI1";
1235 groups = "FSI1";
1236 };
1237
1238 pinctrl_fsi2_default: fsi2_default {
1239 function = "FSI2";
1240 groups = "FSI2";
1241 };
1242
1243 pinctrl_fwspics1_default: fwspics1_default {
1244 function = "FWSPICS1";
1245 groups = "FWSPICS1";
1246 };
1247
1248 pinctrl_fwspics2_default: fwspics2_default {
1249 function = "FWSPICS2";
1250 groups = "FWSPICS2";
1251 };
1252
1253 pinctrl_gpid0_default: gpid0_default {
1254 function = "GPID0";
1255 groups = "GPID0";
1256 };
1257
1258 pinctrl_gpid2_default: gpid2_default {
1259 function = "GPID2";
1260 groups = "GPID2";
1261 };
1262
1263 pinctrl_gpid4_default: gpid4_default {
1264 function = "GPID4";
1265 groups = "GPID4";
1266 };
1267
1268 pinctrl_gpid6_default: gpid6_default {
1269 function = "GPID6";
1270 groups = "GPID6";
1271 };
1272
1273 pinctrl_gpie0_default: gpie0_default {
1274 function = "GPIE0";
1275 groups = "GPIE0";
1276 };
1277
1278 pinctrl_gpie2_default: gpie2_default {
1279 function = "GPIE2";
1280 groups = "GPIE2";
1281 };
1282
1283 pinctrl_gpie4_default: gpie4_default {
1284 function = "GPIE4";
1285 groups = "GPIE4";
1286 };
1287
1288 pinctrl_gpie6_default: gpie6_default {
1289 function = "GPIE6";
1290 groups = "GPIE6";
1291 };
1292
1293 pinctrl_i2c1_default: i2c1_default {
1294 function = "I2C1";
1295 groups = "I2C1";
1296 };
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame]1297
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1298 pinctrl_i2c2_default: i2c2_default {
1299 function = "I2C2";
1300 groups = "I2C2";
1301 };
1302
1303 pinctrl_i2c3_default: i2c3_default {
1304 function = "I2C3";
1305 groups = "I2C3";
1306 };
1307
1308 pinctrl_i2c4_default: i2c4_default {
1309 function = "I2C4";
1310 groups = "I2C4";
1311 };
1312
1313 pinctrl_i2c5_default: i2c5_default {
1314 function = "I2C5";
1315 groups = "I2C5";
1316 };
1317
1318 pinctrl_i2c6_default: i2c6_default {
1319 function = "I2C6";
1320 groups = "I2C6";
1321 };
1322
1323 pinctrl_i2c7_default: i2c7_default {
1324 function = "I2C7";
1325 groups = "I2C7";
1326 };
1327
1328 pinctrl_i2c8_default: i2c8_default {
1329 function = "I2C8";
1330 groups = "I2C8";
1331 };
1332
1333 pinctrl_i2c9_default: i2c9_default {
1334 function = "I2C9";
1335 groups = "I2C9";
1336 };
1337
1338 pinctrl_i2c10_default: i2c10_default {
1339 function = "I2C10";
1340 groups = "I2C10";
1341 };
1342
1343 pinctrl_i2c11_default: i2c11_default {
1344 function = "I2C11";
1345 groups = "I2C11";
1346 };
1347
1348 pinctrl_i2c12_default: i2c12_default {
1349 function = "I2C12";
1350 groups = "I2C12";
1351 };
1352
1353 pinctrl_i2c13_default: i2c13_default {
1354 function = "I2C13";
1355 groups = "I2C13";
1356 };
1357
1358 pinctrl_i2c14_default: i2c14_default {
1359 function = "I2C14";
1360 groups = "I2C14";
1361 };
1362
1363 pinctrl_i2c15_default: i2c15_default {
1364 function = "I2C15";
1365 groups = "I2C15";
1366 };
1367
1368 pinctrl_i2c16_default: i2c16_default {
1369 function = "I2C16";
1370 groups = "I2C16";
1371 };
1372
1373 pinctrl_lad0_default: lad0_default {
1374 function = "LAD0";
1375 groups = "LAD0";
1376 };
1377
1378 pinctrl_lad1_default: lad1_default {
1379 function = "LAD1";
1380 groups = "LAD1";
1381 };
1382
1383 pinctrl_lad2_default: lad2_default {
1384 function = "LAD2";
1385 groups = "LAD2";
1386 };
1387
1388 pinctrl_lad3_default: lad3_default {
1389 function = "LAD3";
1390 groups = "LAD3";
1391 };
1392
1393 pinctrl_lclk_default: lclk_default {
1394 function = "LCLK";
1395 groups = "LCLK";
1396 };
1397
1398 pinctrl_lframe_default: lframe_default {
1399 function = "LFRAME";
1400 groups = "LFRAME";
1401 };
1402
1403 pinctrl_lpchc_default: lpchc_default {
1404 function = "LPCHC";
1405 groups = "LPCHC";
1406 };
1407
1408 pinctrl_lpcpd_default: lpcpd_default {
1409 function = "LPCPD";
1410 groups = "LPCPD";
1411 };
1412
1413 pinctrl_lpcplus_default: lpcplus_default {
1414 function = "LPCPLUS";
1415 groups = "LPCPLUS";
1416 };
1417
1418 pinctrl_lpcpme_default: lpcpme_default {
1419 function = "LPCPME";
1420 groups = "LPCPME";
1421 };
1422
1423 pinctrl_lpcrst_default: lpcrst_default {
1424 function = "LPCRST";
1425 groups = "LPCRST";
1426 };
1427
1428 pinctrl_lpcsmi_default: lpcsmi_default {
1429 function = "LPCSMI";
1430 groups = "LPCSMI";
1431 };
1432
1433 pinctrl_lsirq_default: lsirq_default {
1434 function = "LSIRQ";
1435 groups = "LSIRQ";
1436 };
1437
1438 pinctrl_mac1link_default: mac1link_default {
1439 function = "MAC1LINK";
1440 groups = "MAC1LINK";
1441 };
1442
1443 pinctrl_mac2link_default: mac2link_default {
1444 function = "MAC2LINK";
1445 groups = "MAC2LINK";
1446 };
1447
1448 pinctrl_mac3link_default: mac3link_default {
1449 function = "MAC3LINK";
1450 groups = "MAC3LINK";
1451 };
1452
1453 pinctrl_mac4link_default: mac4link_default {
1454 function = "MAC4LINK";
1455 groups = "MAC4LINK";
1456 };
1457
1458 pinctrl_mdio1_default: mdio1_default {
1459 function = "MDIO1";
1460 groups = "MDIO1";
1461 };
1462
1463 pinctrl_mdio2_default: mdio2_default {
1464 function = "MDIO2";
1465 groups = "MDIO2";
1466 };
1467
1468 pinctrl_mdio3_default: mdio3_default {
1469 function = "MDIO3";
1470 groups = "MDIO3";
1471 };
1472
1473 pinctrl_mdio4_default: mdio4_default {
1474 function = "MDIO4";
1475 groups = "MDIO4";
1476 };
1477
1478 pinctrl_rmii1_default: rmii1_default {
1479 function = "RMII1";
1480 groups = "RMII1";
1481 };
1482
1483 pinctrl_rmii2_default: rmii2_default {
1484 function = "RMII2";
1485 groups = "RMII2";
1486 };
1487
1488 pinctrl_rmii3_default: rmii3_default {
1489 function = "RMII3";
1490 groups = "RMII3";
1491 };
1492
1493 pinctrl_rmii4_default: rmii4_default {
1494 function = "RMII4";
1495 groups = "RMII4";
1496 };
1497
1498 pinctrl_rmii1rclk_default: rmii1rclk_default {
1499 function = "RMII1RCLK";
1500 groups = "RMII1RCLK";
1501 };
1502
1503 pinctrl_rmii2rclk_default: rmii2rclk_default {
1504 function = "RMII2RCLK";
1505 groups = "RMII2RCLK";
1506 };
1507
1508 pinctrl_rmii3rclk_default: rmii3rclk_default {
1509 function = "RMII3RCLK";
1510 groups = "RMII3RCLK";
1511 };
1512
1513 pinctrl_rmii4rclk_default: rmii4rclk_default {
1514 function = "RMII4RCLK";
1515 groups = "RMII4RCLK";
1516 };
1517
1518 pinctrl_ncts1_default: ncts1_default {
1519 function = "NCTS1";
1520 groups = "NCTS1";
1521 };
1522
1523 pinctrl_ncts2_default: ncts2_default {
1524 function = "NCTS2";
1525 groups = "NCTS2";
1526 };
1527
1528 pinctrl_ncts3_default: ncts3_default {
1529 function = "NCTS3";
1530 groups = "NCTS3";
1531 };
1532
1533 pinctrl_ncts4_default: ncts4_default {
1534 function = "NCTS4";
1535 groups = "NCTS4";
1536 };
1537
1538 pinctrl_ndcd1_default: ndcd1_default {
1539 function = "NDCD1";
1540 groups = "NDCD1";
1541 };
1542
1543 pinctrl_ndcd2_default: ndcd2_default {
1544 function = "NDCD2";
1545 groups = "NDCD2";
1546 };
1547
1548 pinctrl_ndcd3_default: ndcd3_default {
1549 function = "NDCD3";
1550 groups = "NDCD3";
1551 };
1552
1553 pinctrl_ndcd4_default: ndcd4_default {
1554 function = "NDCD4";
1555 groups = "NDCD4";
1556 };
1557
1558 pinctrl_ndsr1_default: ndsr1_default {
1559 function = "NDSR1";
1560 groups = "NDSR1";
1561 };
1562
1563 pinctrl_ndsr2_default: ndsr2_default {
1564 function = "NDSR2";
1565 groups = "NDSR2";
1566 };
1567
1568 pinctrl_ndsr3_default: ndsr3_default {
1569 function = "NDSR3";
1570 groups = "NDSR3";
1571 };
1572
1573 pinctrl_ndsr4_default: ndsr4_default {
1574 function = "NDSR4";
1575 groups = "NDSR4";
1576 };
1577
1578 pinctrl_ndtr1_default: ndtr1_default {
1579 function = "NDTR1";
1580 groups = "NDTR1";
1581 };
1582
1583 pinctrl_ndtr2_default: ndtr2_default {
1584 function = "NDTR2";
1585 groups = "NDTR2";
1586 };
1587
1588 pinctrl_ndtr3_default: ndtr3_default {
1589 function = "NDTR3";
1590 groups = "NDTR3";
1591 };
1592
1593 pinctrl_ndtr4_default: ndtr4_default {
1594 function = "NDTR4";
1595 groups = "NDTR4";
1596 };
1597
1598 pinctrl_nri1_default: nri1_default {
1599 function = "NRI1";
1600 groups = "NRI1";
1601 };
1602
1603 pinctrl_nri2_default: nri2_default {
1604 function = "NRI2";
1605 groups = "NRI2";
1606 };
1607
1608 pinctrl_nri3_default: nri3_default {
1609 function = "NRI3";
1610 groups = "NRI3";
1611 };
1612
1613 pinctrl_nri4_default: nri4_default {
1614 function = "NRI4";
1615 groups = "NRI4";
1616 };
1617
1618 pinctrl_nrts1_default: nrts1_default {
1619 function = "NRTS1";
1620 groups = "NRTS1";
1621 };
1622
1623 pinctrl_nrts2_default: nrts2_default {
1624 function = "NRTS2";
1625 groups = "NRTS2";
1626 };
1627
1628 pinctrl_nrts3_default: nrts3_default {
1629 function = "NRTS3";
1630 groups = "NRTS3";
1631 };
1632
1633 pinctrl_nrts4_default: nrts4_default {
1634 function = "NRTS4";
1635 groups = "NRTS4";
1636 };
1637
1638 pinctrl_oscclk_default: oscclk_default {
1639 function = "OSCCLK";
1640 groups = "OSCCLK";
1641 };
1642
1643 pinctrl_pewake_default: pewake_default {
1644 function = "PEWAKE";
1645 groups = "PEWAKE";
1646 };
1647
1648 pinctrl_pnor_default: pnor_default {
1649 function = "PNOR";
1650 groups = "PNOR";
1651 };
1652
1653 pinctrl_pwm0_default: pwm0_default {
1654 function = "PWM0";
1655 groups = "PWM0";
1656 };
1657
1658 pinctrl_pwm1_default: pwm1_default {
1659 function = "PWM1";
1660 groups = "PWM1";
1661 };
1662
1663 pinctrl_pwm2_default: pwm2_default {
1664 function = "PWM2";
1665 groups = "PWM2";
1666 };
1667
1668 pinctrl_pwm3_default: pwm3_default {
1669 function = "PWM3";
1670 groups = "PWM3";
1671 };
1672
1673 pinctrl_pwm4_default: pwm4_default {
1674 function = "PWM4";
1675 groups = "PWM4";
1676 };
1677
1678 pinctrl_pwm5_default: pwm5_default {
1679 function = "PWM5";
1680 groups = "PWM5";
1681 };
1682
1683 pinctrl_pwm6_default: pwm6_default {
1684 function = "PWM6";
1685 groups = "PWM6";
1686 };
1687
1688 pinctrl_pwm7_default: pwm7_default {
1689 function = "PWM7";
1690 groups = "PWM7";
1691 };
1692
Billy Tsai73ee1f22022-03-08 11:04:06 +0800[diff] [blame]1693 pinctrl_pwm8g0_default: pwm8g0_default {
1694 function = "PWM8G0";
1695 groups = "PWM8G0";
1696 };
1697
1698 pinctrl_pwm8g1_default: pwm8g1_default {
1699 function = "PWM8G1";
1700 groups = "PWM8G1";
1701 };
1702
1703 pinctrl_pwm9g0_default: pwm9g0_default {
1704 function = "PWM9G0";
1705 groups = "PWM9G0";
1706 };
1707
1708 pinctrl_pwm9g1_default: pwm9g1_default {
1709 function = "PWM9G1";
1710 groups = "PWM9G1";
1711 };
1712
1713 pinctrl_pwm10g0_default: pwm10g0_default {
1714 function = "PWM10G0";
1715 groups = "PWM10G0";
1716 };
1717
1718 pinctrl_pwm10g1_default: pwm10g1_default {
1719 function = "PWM10G1";
1720 groups = "PWM10G1";
1721 };
1722
1723 pinctrl_pwm11g0_default: pwm11g0_default {
1724 function = "PWM11G0";
1725 groups = "PWM11G0";
1726 };
1727
1728 pinctrl_pwm11g1_default: pwm11g1_default {
1729 function = "PWM11G1";
1730 groups = "PWM11G1";
1731 };
1732
1733 pinctrl_pwm12g0_default: pwm12g0_default {
1734 function = "PWM12G0";
1735 groups = "PWM12G0";
1736 };
1737
1738 pinctrl_pwm12g1_default: pwm12g1_default {
1739 function = "PWM12G1";
1740 groups = "PWM12G1";
1741 };
1742
1743 pinctrl_pwm13g0_default: pwm13g0_default {
1744 function = "PWM13G0";
1745 groups = "PWM13G0";
1746 };
1747
1748 pinctrl_pwm13g1_default: pwm13g1_default {
1749 function = "PWM13G1";
1750 groups = "PWM13G1";
1751 };
1752
1753 pinctrl_pwm14g0_default: pwm14g0_default {
1754 function = "PWM14G0";
1755 groups = "PWM14G0";
1756 };
1757
1758 pinctrl_pwm14g1_default: pwm14g1_default {
1759 function = "PWM14G1";
1760 groups = "PWM14G1";
1761 };
1762
1763 pinctrl_pwm15g0_default: pwm15g0_default {
1764 function = "PWM15G0";
1765 groups = "PWM15G0";
1766 };
1767
1768 pinctrl_pwm15g1_default: pwm15g1_default {
1769 function = "PWM15G1";
1770 groups = "PWM15G1";
1771 };
1772
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1773 pinctrl_rgmii1_default: rgmii1_default {
1774 function = "RGMII1";
1775 groups = "RGMII1";
1776 };
1777
1778 pinctrl_rgmii2_default: rgmii2_default {
1779 function = "RGMII2";
1780 groups = "RGMII2";
1781 };
1782
1783 pinctrl_rgmii3_default: rgmii3_default {
1784 function = "RGMII3";
1785 groups = "RGMII3";
1786 };
1787
1788 pinctrl_rgmii4_default: rgmii4_default {
1789 function = "RGMII4";
1790 groups = "RGMII4";
1791 };
1792
1793 pinctrl_rmii1_default: rmii1_default {
1794 function = "RMII1";
1795 groups = "RMII1";
1796 };
1797
1798 pinctrl_rmii2_default: rmii2_default {
1799 function = "RMII2";
1800 groups = "RMII2";
1801 };
1802
1803 pinctrl_rxd1_default: rxd1_default {
1804 function = "RXD1";
1805 groups = "RXD1";
1806 };
1807
1808 pinctrl_rxd2_default: rxd2_default {
1809 function = "RXD2";
1810 groups = "RXD2";
1811 };
1812
1813 pinctrl_rxd3_default: rxd3_default {
1814 function = "RXD3";
1815 groups = "RXD3";
1816 };
1817
1818 pinctrl_rxd4_default: rxd4_default {
1819 function = "RXD4";
1820 groups = "RXD4";
1821 };
1822
1823 pinctrl_salt1_default: salt1_default {
1824 function = "SALT1";
1825 groups = "SALT1";
1826 };
1827
1828 pinctrl_salt10_default: salt10_default {
1829 function = "SALT10";
1830 groups = "SALT10";
1831 };
1832
1833 pinctrl_salt11_default: salt11_default {
1834 function = "SALT11";
1835 groups = "SALT11";
1836 };
1837
1838 pinctrl_salt12_default: salt12_default {
1839 function = "SALT12";
1840 groups = "SALT12";
1841 };
1842
1843 pinctrl_salt13_default: salt13_default {
1844 function = "SALT13";
1845 groups = "SALT13";
1846 };
1847
1848 pinctrl_salt14_default: salt14_default {
1849 function = "SALT14";
1850 groups = "SALT14";
1851 };
1852
1853 pinctrl_salt2_default: salt2_default {
1854 function = "SALT2";
1855 groups = "SALT2";
1856 };
1857
1858 pinctrl_salt3_default: salt3_default {
1859 function = "SALT3";
1860 groups = "SALT3";
1861 };
1862
1863 pinctrl_salt4_default: salt4_default {
1864 function = "SALT4";
1865 groups = "SALT4";
1866 };
1867
1868 pinctrl_salt5_default: salt5_default {
1869 function = "SALT5";
1870 groups = "SALT5";
1871 };
1872
1873 pinctrl_salt6_default: salt6_default {
1874 function = "SALT6";
1875 groups = "SALT6";
1876 };
1877
1878 pinctrl_salt7_default: salt7_default {
1879 function = "SALT7";
1880 groups = "SALT7";
1881 };
1882
1883 pinctrl_salt8_default: salt8_default {
1884 function = "SALT8";
1885 groups = "SALT8";
1886 };
1887
1888 pinctrl_salt9_default: salt9_default {
1889 function = "SALT9";
1890 groups = "SALT9";
1891 };
1892
1893 pinctrl_scl1_default: scl1_default {
1894 function = "SCL1";
1895 groups = "SCL1";
1896 };
1897
1898 pinctrl_scl2_default: scl2_default {
1899 function = "SCL2";
1900 groups = "SCL2";
1901 };
1902
1903 pinctrl_sd1_default: sd1_default {
1904 function = "SD1";
1905 groups = "SD1";
1906 };
1907
1908 pinctrl_sd2_default: sd2_default {
1909 function = "SD2";
1910 groups = "SD2";
1911 };
1912
1913 pinctrl_emmc_default: emmc_default {
1914 function = "EMMC";
1915 groups = "EMMC";
1916 };
1917
1918 pinctrl_emmcg8_default: emmcg8_default {
1919 function = "EMMCG8";
1920 groups = "EMMCG8";
1921 };
1922
1923 pinctrl_sda1_default: sda1_default {
1924 function = "SDA1";
1925 groups = "SDA1";
1926 };
1927
1928 pinctrl_sda2_default: sda2_default {
1929 function = "SDA2";
1930 groups = "SDA2";
1931 };
1932
1933 pinctrl_sgps1_default: sgps1_default {
1934 function = "SGPS1";
1935 groups = "SGPS1";
1936 };
1937
1938 pinctrl_sgps2_default: sgps2_default {
1939 function = "SGPS2";
1940 groups = "SGPS2";
1941 };
1942
1943 pinctrl_sioonctrl_default: sioonctrl_default {
1944 function = "SIOONCTRL";
1945 groups = "SIOONCTRL";
1946 };
1947
1948 pinctrl_siopbi_default: siopbi_default {
1949 function = "SIOPBI";
1950 groups = "SIOPBI";
1951 };
1952
1953 pinctrl_siopbo_default: siopbo_default {
1954 function = "SIOPBO";
1955 groups = "SIOPBO";
1956 };
1957
1958 pinctrl_siopwreq_default: siopwreq_default {
1959 function = "SIOPWREQ";
1960 groups = "SIOPWREQ";
1961 };
1962
1963 pinctrl_siopwrgd_default: siopwrgd_default {
1964 function = "SIOPWRGD";
1965 groups = "SIOPWRGD";
1966 };
1967
1968 pinctrl_sios3_default: sios3_default {
1969 function = "SIOS3";
1970 groups = "SIOS3";
1971 };
1972
1973 pinctrl_sios5_default: sios5_default {
1974 function = "SIOS5";
1975 groups = "SIOS5";
1976 };
1977
1978 pinctrl_siosci_default: siosci_default {
1979 function = "SIOSCI";
1980 groups = "SIOSCI";
1981 };
1982
1983 pinctrl_spi1_default: spi1_default {
1984 function = "SPI1";
1985 groups = "SPI1";
1986 };
1987
1988 pinctrl_spi1cs1_default: spi1cs1_default {
1989 function = "SPI1CS1";
1990 groups = "SPI1CS1";
1991 };
1992
1993 pinctrl_spi1debug_default: spi1debug_default {
1994 function = "SPI1DEBUG";
1995 groups = "SPI1DEBUG";
1996 };
1997
1998 pinctrl_spi1passthru_default: spi1passthru_default {
1999 function = "SPI1PASSTHRU";
2000 groups = "SPI1PASSTHRU";
2001 };
2002
2003 pinctrl_spi2ck_default: spi2ck_default {
2004 function = "SPI2CK";
2005 groups = "SPI2CK";
2006 };
2007
2008 pinctrl_spi2cs0_default: spi2cs0_default {
2009 function = "SPI2CS0";
2010 groups = "SPI2CS0";
2011 };
2012
2013 pinctrl_spi2cs1_default: spi2cs1_default {
2014 function = "SPI2CS1";
2015 groups = "SPI2CS1";
2016 };
2017
2018 pinctrl_spi2miso_default: spi2miso_default {
2019 function = "SPI2MISO";
2020 groups = "SPI2MISO";
2021 };
2022
2023 pinctrl_spi2mosi_default: spi2mosi_default {
2024 function = "SPI2MOSI";
2025 groups = "SPI2MOSI";
2026 };
2027
2028 pinctrl_timer3_default: timer3_default {
2029 function = "TIMER3";
2030 groups = "TIMER3";
2031 };
2032
2033 pinctrl_timer4_default: timer4_default {
2034 function = "TIMER4";
2035 groups = "TIMER4";
2036 };
2037
2038 pinctrl_timer5_default: timer5_default {
2039 function = "TIMER5";
2040 groups = "TIMER5";
2041 };
2042
2043 pinctrl_timer6_default: timer6_default {
2044 function = "TIMER6";
2045 groups = "TIMER6";
2046 };
2047
2048 pinctrl_timer7_default: timer7_default {
2049 function = "TIMER7";
2050 groups = "TIMER7";
2051 };
2052
2053 pinctrl_timer8_default: timer8_default {
2054 function = "TIMER8";
2055 groups = "TIMER8";
2056 };
2057
2058 pinctrl_txd1_default: txd1_default {
2059 function = "TXD1";
2060 groups = "TXD1";
2061 };
2062
2063 pinctrl_txd2_default: txd2_default {
2064 function = "TXD2";
2065 groups = "TXD2";
2066 };
2067
2068 pinctrl_txd3_default: txd3_default {
2069 function = "TXD3";
2070 groups = "TXD3";
2071 };
2072
2073 pinctrl_txd4_default: txd4_default {
2074 function = "TXD4";
2075 groups = "TXD4";
2076 };
2077
2078 pinctrl_uart6_default: uart6_default {
2079 function = "UART6";
2080 groups = "UART6";
2081 };
2082
2083 pinctrl_usbcki_default: usbcki_default {
2084 function = "USBCKI";
2085 groups = "USBCKI";
2086 };
2087
2088 pinctrl_usb2ah_default: usb2ah_default {
2089 function = "USB2AH";
2090 groups = "USB2AH";
2091 };
2092
2093 pinctrl_usb11bhid_default: usb11bhid_default {
2094 function = "USB11BHID";
2095 groups = "USB11BHID";
2096 };
2097
2098 pinctrl_usb2bh_default: usb2bh_default {
2099 function = "USB2BH";
2100 groups = "USB2BH";
2101 };
2102
2103 pinctrl_vgabiosrom_default: vgabiosrom_default {
2104 function = "VGABIOSROM";
2105 groups = "VGABIOSROM";
2106 };
2107
2108 pinctrl_vgahs_default: vgahs_default {
2109 function = "VGAHS";
2110 groups = "VGAHS";
2111 };
2112
2113 pinctrl_vgavs_default: vgavs_default {
2114 function = "VGAVS";
2115 groups = "VGAVS";
2116 };
2117
2118 pinctrl_vpi24_default: vpi24_default {
2119 function = "VPI24";
2120 groups = "VPI24";
2121 };
2122
2123 pinctrl_vpo_default: vpo_default {
2124 function = "VPO";
2125 groups = "VPO";
2126 };
2127
2128 pinctrl_wdtrst1_default: wdtrst1_default {
2129 function = "WDTRST1";
2130 groups = "WDTRST1";
2131 };
2132
2133 pinctrl_wdtrst2_default: wdtrst2_default {
2134 function = "WDTRST2";
2135 groups = "WDTRST2";
2136 };
2137
2138 pinctrl_pcie0rc_default: pcie0rc_default {
2139 function = "PCIE0RC";
2140 groups = "PCIE0RC";
2141 };
2142
2143 pinctrl_pcie1rc_default: pcie1rc_default {
2144 function = "PCIE1RC";
2145 groups = "PCIE1RC";
2146 };
2147};