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Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Poonam Aggrwal0e870982009-07-31 12:08:14 +05302 * Copyright 2004,2009 Freescale Semiconductor, Inc.
Jon Loeligerc934f652006-05-31 13:55:35 -05003 * Jeff Brown
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * cpu_init.c - low level cpu init
27 */
28
Becky Bruce2d0daa02008-08-04 14:02:26 -050029#include <config.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050030#include <common.h>
31#include <mpc86xx.h>
Becky Bruce2d0daa02008-08-04 14:02:26 -050032#include <asm/mmu.h>
Jean-Christophe PLAGNIOL-VILLARD83d1b382008-02-17 23:03:36 +010033#include <asm/fsl_law.h>
Kumar Gala7649a592009-03-31 23:02:38 -050034#include <asm/mp.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050035
Becky Bruce24bfb482008-11-05 14:55:30 -060036void setup_bats(void);
37
Wolfgang Denk1218abf2007-09-15 20:48:41 +020038DECLARE_GLOBAL_DATA_PTR;
39
Jon Loeligerdebb7352006-04-26 17:58:56 -050040/*
41 * Breathe some life into the CPU...
42 *
43 * Set up the memory map
44 * initialize a bunch of registers
45 */
46
Jon Loeliger5c9efb32006-04-27 10:15:16 -050047void cpu_init_f(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050048{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeligerdebb7352006-04-26 17:58:56 -050050 volatile ccsr_lbc_t *memctl = &immap->im_lbc;
Jon Loeliger5c9efb32006-04-27 10:15:16 -050051
Jon Loeligerffff3ae2006-08-22 12:06:18 -050052 /* Pointer is writable since we allocated a register for it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
Jon Loeligerdebb7352006-04-26 17:58:56 -050054
55 /* Clear initial global data */
56 memset ((void *) gd, 0, sizeof (gd_t));
57
Becky Bruce4933b912008-01-23 16:31:01 -060058#ifdef CONFIG_FSL_LAW
59 init_laws();
60#endif
61
Becky Bruce24bfb482008-11-05 14:55:30 -060062 setup_bats();
63
Jon Loeligerdebb7352006-04-26 17:58:56 -050064 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
65 * addresses - these have to be modified later when FLASH size
66 * has been determined
67 */
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#if defined(CONFIG_SYS_OR0_REMAP)
70 memctl->or0 = CONFIG_SYS_OR0_REMAP;
Jon Loeligerdebb7352006-04-26 17:58:56 -050071#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#if defined(CONFIG_SYS_OR1_REMAP)
73 memctl->or1 = CONFIG_SYS_OR1_REMAP;
Jon Loeligerdebb7352006-04-26 17:58:56 -050074#endif
75
76 /* now restrict to preliminary range */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
78 memctl->br0 = CONFIG_SYS_BR0_PRELIM;
79 memctl->or0 = CONFIG_SYS_OR0_PRELIM;
Jon Loeligerdebb7352006-04-26 17:58:56 -050080#endif
81
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
83 memctl->or1 = CONFIG_SYS_OR1_PRELIM;
84 memctl->br1 = CONFIG_SYS_BR1_PRELIM;
Jon Loeligerdebb7352006-04-26 17:58:56 -050085#endif
86
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
88 memctl->or2 = CONFIG_SYS_OR2_PRELIM;
89 memctl->br2 = CONFIG_SYS_BR2_PRELIM;
Jon Loeligerdebb7352006-04-26 17:58:56 -050090#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -050091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
93 memctl->or3 = CONFIG_SYS_OR3_PRELIM;
94 memctl->br3 = CONFIG_SYS_BR3_PRELIM;
Jon Loeligerdebb7352006-04-26 17:58:56 -050095#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -050096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
98 memctl->or4 = CONFIG_SYS_OR4_PRELIM;
99 memctl->br4 = CONFIG_SYS_BR4_PRELIM;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500100#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
103 memctl->or5 = CONFIG_SYS_OR5_PRELIM;
104 memctl->br5 = CONFIG_SYS_BR5_PRELIM;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500105#endif
106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
108 memctl->or6 = CONFIG_SYS_OR6_PRELIM;
109 memctl->br6 = CONFIG_SYS_BR6_PRELIM;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500110#endif
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
113 memctl->or7 = CONFIG_SYS_OR7_PRELIM;
114 memctl->br7 = CONFIG_SYS_BR7_PRELIM;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500115#endif
Peter Tyser79f43332009-06-30 17:15:47 -0500116#if defined(CONFIG_FSL_DMA)
117 dma_init();
118#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500119
120 /* enable the timebase bit in HID0 */
121 set_hid0(get_hid0() | 0x4000000);
122
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500123 /* enable EMCP, SYNCBE | ABE bits in HID1 */
124 set_hid1(get_hid1() | 0x80000C00);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500125}
126
127/*
128 * initialize higher level parts of CPU like timers
129 */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500130int cpu_init_r(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500131{
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530132#if defined(CONFIG_MP)
Becky Bruce1266df82008-11-03 15:44:01 -0600133 setup_mp();
134#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500135 return 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500136}
Becky Bruce2d0daa02008-08-04 14:02:26 -0500137
138/* Set up BAT registers */
139void setup_bats(void)
140{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
142 write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
143 write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
144 write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
145 write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
146 write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L);
147 write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L);
148 write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L);
149 write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L);
150 write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L);
151 write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L);
152 write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L);
153 write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
154 write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
155 write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L);
156 write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L);
Becky Bruce2d0daa02008-08-04 14:02:26 -0500157
158 return;
159}
Becky Brucec9315e62009-02-03 18:10:52 -0600160
161#ifdef CONFIG_ADDR_MAP
162/* Initialize address mapping array */
163void init_addr_map(void)
164{
165 int i;
166 ppc_bat_t bat = DBAT0;
167 phys_size_t size;
168 unsigned long upper, lower;
169
170 for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
171 if (read_bat(bat, &upper, &lower) != -1) {
172 if (!BATU_VALID(upper))
173 size = 0;
174 else
175 size = BATU_SIZE(upper);
176 addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
177 size, i);
178 }
179#ifdef CONFIG_HIGH_BATS
180 /* High bats are not contiguous with low BAT numbers */
181 if (bat == DBAT3)
182 bat = DBAT4 - 1;
183#endif
184 }
185}
186#endif