blob: 927c88c78f202556c693745d35456d25abc4f838 [file] [log] [blame]
wdenk0442ed82002-11-03 10:24:00 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
Stefan Roese3cb86f32007-03-24 15:45:34 +01005 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
Grant Ericksonc821b5f2008-05-22 14:44:14 -07006 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
wdenk0442ed82002-11-03 10:24:00 +00008 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020027/*------------------------------------------------------------------------------+
Josh Boyer31773492009-08-07 13:53:20 -040028 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020030 *
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
37 *
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
41 *
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
45 *
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
49 */
wdenk0442ed82002-11-03 10:24:00 +000050
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020051/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
wdenk0442ed82002-11-03 10:24:00 +000052 *
53 *
54 * The processor starts at 0xfffffffc and the code is executed
55 * from flash/rom.
56 * in memory, but as long we don't jump around before relocating.
57 * board_init lies at a quite high address and when the cpu has
58 * jumped there, everything is ok.
59 * This works because the cpu gives the FLASH (CS0) the whole
60 * address space at startup, and board_init lies as a echo of
61 * the flash somewhere up there in the memorymap.
62 *
63 * board_init will change CS0 to be positioned at the correct
64 * address and (s)dram will be positioned at address 0
65 */
66#include <config.h>
wdenk0442ed82002-11-03 10:24:00 +000067#include <ppc4xx.h>
Peter Tyser561858e2008-11-03 09:30:59 -060068#include <timestamp.h>
wdenk0442ed82002-11-03 10:24:00 +000069#include <version.h>
70
71#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
72
73#include <ppc_asm.tmpl>
74#include <ppc_defs.h>
75
76#include <asm/cache.h>
77#include <asm/mmu.h>
Dave Mitchellb14ca4b2008-11-20 14:00:49 -060078#include <asm/ppc4xx-isram.h>
wdenk0442ed82002-11-03 10:24:00 +000079
80#ifndef CONFIG_IDENT_STRING
81#define CONFIG_IDENT_STRING ""
82#endif
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#ifdef CONFIG_SYS_INIT_DCACHE_CS
85# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
Stefan Roesed1c3b272009-09-09 16:25:29 +020086# define PBxAP PB1AP
87# define PBxCR PB0CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
89# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
90# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -070091# endif
wdenk0442ed82002-11-03 10:24:00 +000092# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093# if (CONFIG_SYS_INIT_DCACHE_CS == 1)
Stefan Roesed1c3b272009-09-09 16:25:29 +020094# define PBxAP PB1AP
95# define PBxCR PB1CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
97# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
98# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -070099# endif
wdenk0442ed82002-11-03 10:24:00 +0000100# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101# if (CONFIG_SYS_INIT_DCACHE_CS == 2)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200102# define PBxAP PB2AP
103# define PBxCR PB2CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
105# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
106# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700107# endif
wdenk0442ed82002-11-03 10:24:00 +0000108# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# if (CONFIG_SYS_INIT_DCACHE_CS == 3)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200110# define PBxAP PB3AP
111# define PBxCR PB3CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
113# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
114# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700115# endif
wdenk0442ed82002-11-03 10:24:00 +0000116# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117# if (CONFIG_SYS_INIT_DCACHE_CS == 4)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200118# define PBxAP PB4AP
119# define PBxCR PB4CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
121# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
122# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700123# endif
wdenk0442ed82002-11-03 10:24:00 +0000124# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125# if (CONFIG_SYS_INIT_DCACHE_CS == 5)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200126# define PBxAP PB5AP
127# define PBxCR PB5CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
129# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
130# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700131# endif
wdenk0442ed82002-11-03 10:24:00 +0000132# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133# if (CONFIG_SYS_INIT_DCACHE_CS == 6)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200134# define PBxAP PB6AP
135# define PBxCR PB6CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
137# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
138# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700139# endif
wdenk0442ed82002-11-03 10:24:00 +0000140# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141# if (CONFIG_SYS_INIT_DCACHE_CS == 7)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200142# define PBxAP PB7AP
143# define PBxCR PB7CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
145# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
146# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700147# endif
148# endif
149# ifndef PBxAP_VAL
150# define PBxAP_VAL 0
151# endif
152# ifndef PBxCR_VAL
153# define PBxCR_VAL 0
154# endif
155/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700157 * used as temporary stack pointer for the primordial stack
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
160# define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700161 EBC_BXAP_TWT_ENCODE(7) | \
162 EBC_BXAP_BCE_DISABLE | \
163 EBC_BXAP_BCT_2TRANS | \
164 EBC_BXAP_CSN_ENCODE(0) | \
165 EBC_BXAP_OEN_ENCODE(0) | \
166 EBC_BXAP_WBN_ENCODE(0) | \
167 EBC_BXAP_WBF_ENCODE(0) | \
168 EBC_BXAP_TH_ENCODE(2) | \
169 EBC_BXAP_RE_DISABLED | \
170 EBC_BXAP_SOR_NONDELAYED | \
171 EBC_BXAP_BEM_WRITEONLY | \
172 EBC_BXAP_PEN_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
174# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
175# define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700176 EBC_BXCR_BS_64MB | \
177 EBC_BXCR_BU_RW | \
178 EBC_BXCR_BW_16BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
180# ifndef CONFIG_SYS_INIT_RAM_PATTERN
181# define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
wdenk0442ed82002-11-03 10:24:00 +0000182# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#endif /* CONFIG_SYS_INIT_DCACHE_CS */
wdenk0442ed82002-11-03 10:24:00 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
186#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
Stefan Roese28d77d92008-01-30 14:48:28 +0100187#endif
188
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700189/*
190 * Unless otherwise overriden, enable two 128MB cachable instruction regions
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
192 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#if !defined(CONFIG_SYS_FLASH_BASE)
Stefan Roese64852d02008-06-02 14:35:44 +0200195/* If not already defined, set it to the "last" 128MByte region */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196# define CONFIG_SYS_FLASH_BASE 0xf8000000
Stefan Roese64852d02008-06-02 14:35:44 +0200197#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
199# define CONFIG_SYS_ICACHE_SACR_VALUE \
200 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
201 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
202 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
203#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
206# define CONFIG_SYS_DCACHE_SACR_VALUE \
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700207 (0x00000000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700209
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200210#define function_prolog(func_name) .text; \
Stefan Roesecf959c72007-06-01 15:27:11 +0200211 .align 2; \
212 .globl func_name; \
213 func_name:
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200214#define function_epilog(func_name) .type func_name,@function; \
Stefan Roesecf959c72007-06-01 15:27:11 +0200215 .size func_name,.-func_name
216
wdenk0442ed82002-11-03 10:24:00 +0000217/* We don't want the MMU yet.
218*/
219#undef MSR_KERNEL
220#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
221
222
223 .extern ext_bus_cntlr_init
Stefan Roese887e2ec2006-09-07 11:51:23 +0200224#ifdef CONFIG_NAND_U_BOOT
225 .extern reconfig_tlb0
226#endif
wdenk0442ed82002-11-03 10:24:00 +0000227
228/*
229 * Set up GOT: Global Offset Table
230 *
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100231 * Use r12 to access the GOT
wdenk0442ed82002-11-03 10:24:00 +0000232 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200233#if !defined(CONFIG_NAND_SPL)
wdenk0442ed82002-11-03 10:24:00 +0000234 START_GOT
235 GOT_ENTRY(_GOT2_TABLE_)
236 GOT_ENTRY(_FIXUP_TABLE_)
237
238 GOT_ENTRY(_start)
239 GOT_ENTRY(_start_of_vectors)
240 GOT_ENTRY(_end_of_vectors)
241 GOT_ENTRY(transfer_to_handler)
242
wdenk3b57fe02003-05-30 12:48:29 +0000243 GOT_ENTRY(__init_end)
wdenk0442ed82002-11-03 10:24:00 +0000244 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +0000245 GOT_ENTRY(__bss_start)
wdenk0442ed82002-11-03 10:24:00 +0000246 END_GOT
Stefan Roese887e2ec2006-09-07 11:51:23 +0200247#endif /* CONFIG_NAND_SPL */
248
249#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
250 /*
251 * NAND U-Boot image is started from offset 0
252 */
253 .text
Stefan Roesec440bfe2007-06-06 11:42:13 +0200254#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200255 bl reconfig_tlb0
Stefan Roesec440bfe2007-06-06 11:42:13 +0200256#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200257 GET_GOT
258 bl cpu_init_f /* run low-level CPU init code (from Flash) */
259 bl board_init_f
260#endif
wdenk0442ed82002-11-03 10:24:00 +0000261
Stefan Roesed8731332009-05-11 13:46:14 +0200262#if defined(CONFIG_SYS_RAMBOOT)
263 /*
264 * 4xx RAM-booting U-Boot image is started from offset 0
265 */
266 .text
267 bl _start_440
268#endif
269
wdenk0442ed82002-11-03 10:24:00 +0000270/*
271 * 440 Startup -- on reset only the top 4k of the effective
272 * address space is mapped in by an entry in the instruction
273 * and data shadow TLB. The .bootpg section is located in the
274 * top 4k & does only what's necessary to map in the the rest
275 * of the boot rom. Once the boot rom is mapped in we can
276 * proceed with normal startup.
277 *
278 * NOTE: CS0 only covers the top 2MB of the effective address
279 * space after reset.
280 */
281
282#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200283#if !defined(CONFIG_NAND_SPL)
wdenk0442ed82002-11-03 10:24:00 +0000284 .section .bootpg,"ax"
Stefan Roese887e2ec2006-09-07 11:51:23 +0200285#endif
wdenk0442ed82002-11-03 10:24:00 +0000286 .globl _start_440
287
288/**************************************************************************/
289_start_440:
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200290 /*--------------------------------------------------------------------+
291 | 440EPX BUP Change - Hardware team request
292 +--------------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +0200293#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
294 sync
295 nop
296 nop
297#endif
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200298 /*----------------------------------------------------------------+
299 | Core bug fix. Clear the esr
300 +-----------------------------------------------------------------*/
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200301 li r0,0
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200302 mtspr SPRN_ESR,r0
wdenk0442ed82002-11-03 10:24:00 +0000303 /*----------------------------------------------------------------*/
304 /* Clear and set up some registers. */
305 /*----------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +0200306 iccci r0,r0 /* NOTE: operands not used for 440 */
307 dccci r0,r0 /* NOTE: operands not used for 440 */
wdenk0442ed82002-11-03 10:24:00 +0000308 sync
309 li r0,0
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200310 mtspr SPRN_SRR0,r0
311 mtspr SPRN_SRR1,r0
312 mtspr SPRN_CSRR0,r0
313 mtspr SPRN_CSRR1,r0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200314 /* NOTE: 440GX adds machine check status regs */
315#if defined(CONFIG_440) && !defined(CONFIG_440GP)
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200316 mtspr SPRN_MCSRR0,r0
317 mtspr SPRN_MCSRR1,r0
318 mfspr r1,SPRN_MCSR
319 mtspr SPRN_MCSR,r1
wdenkba56f622004-02-06 23:19:44 +0000320#endif
Stefan Roese20532832006-11-22 13:20:50 +0100321
322 /*----------------------------------------------------------------*/
323 /* CCR0 init */
324 /*----------------------------------------------------------------*/
325 /* Disable store gathering & broadcast, guarantee inst/data
326 * cache block touch, force load/store alignment
327 * (see errata 1.12: 440_33)
328 */
329 lis r1,0x0030 /* store gathering & broadcast disable */
330 ori r1,r1,0x6000 /* cache touch */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200331 mtspr SPRN_CCR0,r1
Stefan Roese20532832006-11-22 13:20:50 +0100332
wdenk0442ed82002-11-03 10:24:00 +0000333 /*----------------------------------------------------------------*/
334 /* Initialize debug */
335 /*----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200336 mfspr r1,SPRN_DBCR0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200337 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
338 bne skip_debug_init /* if set, don't clear debug register */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200339 mtspr SPRN_DBCR0,r0
340 mtspr SPRN_DBCR1,r0
341 mtspr SPRN_DBCR2,r0
342 mtspr SPRN_IAC1,r0
343 mtspr SPRN_IAC2,r0
344 mtspr SPRN_IAC3,r0
345 mtspr SPRN_DAC1,r0
346 mtspr SPRN_DAC2,r0
347 mtspr SPRN_DVC1,r0
348 mtspr SPRN_DVC2,r0
wdenk0442ed82002-11-03 10:24:00 +0000349
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200350 mfspr r1,SPRN_DBSR
351 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200352skip_debug_init:
wdenk0442ed82002-11-03 10:24:00 +0000353
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200354#if defined (CONFIG_440SPE)
355 /*----------------------------------------------------------------+
356 | Initialize Core Configuration Reg1.
357 | a. ICDPEI: Record even parity. Normal operation.
358 | b. ICTPEI: Record even parity. Normal operation.
359 | c. DCTPEI: Record even parity. Normal operation.
360 | d. DCDPEI: Record even parity. Normal operation.
361 | e. DCUPEI: Record even parity. Normal operation.
362 | f. DCMPEI: Record even parity. Normal operation.
363 | g. FCOM: Normal operation
364 | h. MMUPEI: Record even parity. Normal operation.
365 | i. FFF: Flush only as much data as necessary.
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200366 | j. TCS: Timebase increments from CPU clock.
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200367 +-----------------------------------------------------------------*/
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200368 li r0,0
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200369 mtspr SPRN_CCR1, r0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200370
371 /*----------------------------------------------------------------+
372 | Reset the timebase.
373 | The previous write to CCR1 sets the timebase source.
374 +-----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200375 mtspr SPRN_TBWL, r0
376 mtspr SPRN_TBWU, r0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200377#endif
378
wdenk0442ed82002-11-03 10:24:00 +0000379 /*----------------------------------------------------------------*/
380 /* Setup interrupt vectors */
381 /*----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200382 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200383 li r1,0x0100
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200384 mtspr SPRN_IVOR0,r1 /* Critical input */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200385 li r1,0x0200
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200386 mtspr SPRN_IVOR1,r1 /* Machine check */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200387 li r1,0x0300
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200388 mtspr SPRN_IVOR2,r1 /* Data storage */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200389 li r1,0x0400
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200390 mtspr SPRN_IVOR3,r1 /* Instruction storage */
wdenk0442ed82002-11-03 10:24:00 +0000391 li r1,0x0500
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200392 mtspr SPRN_IVOR4,r1 /* External interrupt */
wdenk0442ed82002-11-03 10:24:00 +0000393 li r1,0x0600
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200394 mtspr SPRN_IVOR5,r1 /* Alignment */
wdenk0442ed82002-11-03 10:24:00 +0000395 li r1,0x0700
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200396 mtspr SPRN_IVOR6,r1 /* Program check */
wdenk0442ed82002-11-03 10:24:00 +0000397 li r1,0x0800
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200398 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
wdenk0442ed82002-11-03 10:24:00 +0000399 li r1,0x0c00
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200400 mtspr SPRN_IVOR8,r1 /* System call */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200401 li r1,0x0a00
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200402 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200403 li r1,0x0900
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200404 mtspr SPRN_IVOR10,r1 /* Decrementer */
wdenk0442ed82002-11-03 10:24:00 +0000405 li r1,0x1300
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200406 mtspr SPRN_IVOR13,r1 /* Data TLB error */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200407 li r1,0x1400
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200408 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
wdenk0442ed82002-11-03 10:24:00 +0000409 li r1,0x2000
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200410 mtspr SPRN_IVOR15,r1 /* Debug */
wdenk0442ed82002-11-03 10:24:00 +0000411
412 /*----------------------------------------------------------------*/
413 /* Configure cache regions */
414 /*----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200415 mtspr SPRN_INV0,r0
416 mtspr SPRN_INV1,r0
417 mtspr SPRN_INV2,r0
418 mtspr SPRN_INV3,r0
419 mtspr SPRN_DNV0,r0
420 mtspr SPRN_DNV1,r0
421 mtspr SPRN_DNV2,r0
422 mtspr SPRN_DNV3,r0
423 mtspr SPRN_ITV0,r0
424 mtspr SPRN_ITV1,r0
425 mtspr SPRN_ITV2,r0
426 mtspr SPRN_ITV3,r0
427 mtspr SPRN_DTV0,r0
428 mtspr SPRN_DTV1,r0
429 mtspr SPRN_DTV2,r0
430 mtspr SPRN_DTV3,r0
wdenk0442ed82002-11-03 10:24:00 +0000431
432 /*----------------------------------------------------------------*/
433 /* Cache victim limits */
434 /*----------------------------------------------------------------*/
435 /* floors 0, ceiling max to use the entire cache -- nothing locked
436 */
437 lis r1,0x0001
438 ori r1,r1,0xf800
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200439 mtspr SPRN_IVLIM,r1
440 mtspr SPRN_DVLIM,r1
wdenk0442ed82002-11-03 10:24:00 +0000441
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200442 /*----------------------------------------------------------------+
443 |Initialize MMUCR[STID] = 0.
444 +-----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200445 mfspr r0,SPRN_MMUCR
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200446 addis r1,0,0xFFFF
447 ori r1,r1,0xFF00
448 and r0,r0,r1
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200449 mtspr SPRN_MMUCR,r0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200450
wdenk0442ed82002-11-03 10:24:00 +0000451 /*----------------------------------------------------------------*/
452 /* Clear all TLB entries -- TID = 0, TS = 0 */
453 /*----------------------------------------------------------------*/
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200454 addis r0,0,0x0000
Stefan Roese0a371ca2009-07-14 15:53:08 +0200455#ifdef CONFIG_SYS_RAMBOOT
Stefan Roesed8731332009-05-11 13:46:14 +0200456 li r4,0 /* Start with TLB #0 */
Stefan Roese0a371ca2009-07-14 15:53:08 +0200457#else
458 li r4,1 /* Start with TLB #1 */
459#endif
460 li r1,64 /* 64 TLB entries */
461 sub r1,r1,r4 /* calculate last TLB # */
462 mtctr r1
Stefan Roesed8731332009-05-11 13:46:14 +0200463rsttlb:
464#ifdef CONFIG_SYS_RAMBOOT
465 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
466 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
467 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
468#endif
469 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
470 tlbwe r0,r4,1
471 tlbwe r0,r4,2
472tlbnxt: addi r4,r4,1 /* Next TLB */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200473 bdnz rsttlb
wdenk0442ed82002-11-03 10:24:00 +0000474
475 /*----------------------------------------------------------------*/
476 /* TLB entry setup -- step thru tlbtab */
477 /*----------------------------------------------------------------*/
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200478#if defined(CONFIG_440SPE)
479 /*----------------------------------------------------------------*/
480 /* We have different TLB tables for revA and rev B of 440SPe */
481 /*----------------------------------------------------------------*/
482 mfspr r1, PVR
483 lis r0,0x5342
484 ori r0,r0,0x1891
485 cmpw r7,r1,r0
486 bne r7,..revA
487 bl tlbtabB
488 b ..goon
489..revA:
490 bl tlbtabA
491..goon:
492#else
wdenk0442ed82002-11-03 10:24:00 +0000493 bl tlbtab /* Get tlbtab pointer */
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200494#endif
wdenk0442ed82002-11-03 10:24:00 +0000495 mr r5,r0
496 li r1,0x003f /* 64 TLB entries max */
497 mtctr r1
498 li r4,0 /* TLB # */
499
500 addi r5,r5,-4
Stefan Roesed8731332009-05-11 13:46:14 +02005011:
502#ifdef CONFIG_SYS_RAMBOOT
503 tlbre r3,r4,0 /* Read contents from TLB word #0 */
504 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
505 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
506#endif
507 lwzu r0,4(r5)
wdenk0442ed82002-11-03 10:24:00 +0000508 cmpwi r0,0
509 beq 2f /* 0 marks end */
510 lwzu r1,4(r5)
511 lwzu r2,4(r5)
512 tlbwe r0,r4,0 /* TLB Word 0 */
513 tlbwe r1,r4,1 /* TLB Word 1 */
514 tlbwe r2,r4,2 /* TLB Word 2 */
Stefan Roesed8731332009-05-11 13:46:14 +0200515tlbnx2: addi r4,r4,1 /* Next TLB */
wdenk0442ed82002-11-03 10:24:00 +0000516 bdnz 1b
517
518 /*----------------------------------------------------------------*/
519 /* Continue from 'normal' start */
520 /*----------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +02005212:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200522 bl 3f
wdenk0442ed82002-11-03 10:24:00 +0000523 b _start
524
5253: li r0,0
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200526 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
wdenk0442ed82002-11-03 10:24:00 +0000527 mflr r1
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200528 mtspr SPRN_SRR0,r1
wdenk0442ed82002-11-03 10:24:00 +0000529 rfi
stroeseb867d702003-05-23 11:18:02 +0000530#endif /* CONFIG_440 */
wdenk0442ed82002-11-03 10:24:00 +0000531
532/*
533 * r3 - 1st arg to board_init(): IMMP pointer
534 * r4 - 2nd arg to board_init(): boot flag
535 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200536#ifndef CONFIG_NAND_SPL
wdenk0442ed82002-11-03 10:24:00 +0000537 .text
538 .long 0x27051956 /* U-Boot Magic Number */
539 .globl version_string
540version_string:
541 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600542 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
wdenk0442ed82002-11-03 10:24:00 +0000543 .ascii CONFIG_IDENT_STRING, "\0"
544
wdenk0442ed82002-11-03 10:24:00 +0000545 . = EXC_OFF_SYS_RESET
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200546 .globl _start_of_vectors
547_start_of_vectors:
548
549/* Critical input. */
550 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
551
552#ifdef CONFIG_440
553/* Machine check */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200554 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200555#else
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200556 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200557#endif /* CONFIG_440 */
558
559/* Data Storage exception. */
560 STD_EXCEPTION(0x300, DataStorage, UnknownException)
561
562/* Instruction Storage exception. */
563 STD_EXCEPTION(0x400, InstStorage, UnknownException)
564
565/* External Interrupt exception. */
566 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
567
568/* Alignment exception. */
569 . = 0x600
570Alignment:
571 EXCEPTION_PROLOG(SRR0, SRR1)
572 mfspr r4,DAR
573 stw r4,_DAR(r21)
574 mfspr r5,DSISR
575 stw r5,_DSISR(r21)
576 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100577 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200578
579/* Program check exception */
580 . = 0x700
581ProgramCheck:
582 EXCEPTION_PROLOG(SRR0, SRR1)
583 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100584 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
585 MSR_KERNEL, COPY_EE)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200586
587#ifdef CONFIG_440
588 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
589 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
590 STD_EXCEPTION(0xa00, APU, UnknownException)
Stefan Roesedf8a24c2007-06-19 16:42:31 +0200591#endif
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200592 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
593
594#ifdef CONFIG_440
595 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
596 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
597#else
598 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
599 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
600 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
601#endif
602 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
603
604 .globl _end_of_vectors
605_end_of_vectors:
606 . = _START_OFFSET
Stefan Roese887e2ec2006-09-07 11:51:23 +0200607#endif
wdenk0442ed82002-11-03 10:24:00 +0000608 .globl _start
609_start:
610
611/*****************************************************************************/
612#if defined(CONFIG_440)
613
614 /*----------------------------------------------------------------*/
615 /* Clear and set up some registers. */
616 /*----------------------------------------------------------------*/
617 li r0,0x0000
618 lis r1,0xffff
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200619 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
620 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
621 mtspr SPRN_TBWU,r0
622 mtspr SPRN_TSR,r1 /* clear all timer exception status */
623 mtspr SPRN_TCR,r0 /* disable all */
624 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
wdenk0442ed82002-11-03 10:24:00 +0000625 mtxer r0 /* clear integer exception register */
wdenk0442ed82002-11-03 10:24:00 +0000626
627 /*----------------------------------------------------------------*/
628 /* Debug setup -- some (not very good) ice's need an event*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200629 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
wdenk0442ed82002-11-03 10:24:00 +0000630 /* value you need in this case 0x8cff 0000 should do the trick */
631 /*----------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200632#if defined(CONFIG_SYS_INIT_DBCR)
wdenk0442ed82002-11-03 10:24:00 +0000633 lis r1,0xffff
634 ori r1,r1,0xffff
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200635 mtspr SPRN_DBSR,r1 /* Clear all status bits */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200636 lis r0,CONFIG_SYS_INIT_DBCR@h
637 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200638 mtspr SPRN_DBCR0,r0
wdenk0442ed82002-11-03 10:24:00 +0000639 isync
640#endif
641
642 /*----------------------------------------------------------------*/
643 /* Setup the internal SRAM */
644 /*----------------------------------------------------------------*/
645 li r0,0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200646
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200647#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Stefan Roesec157d8e2005-08-01 16:41:48 +0200648 /* Clear Dcache to use as RAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200649 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
650 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
651 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
652 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
Stefan Roesec157d8e2005-08-01 16:41:48 +0200653 rlwinm. r5,r4,0,27,31
Wolfgang Denkf901a832005-08-06 01:42:58 +0200654 rlwinm r5,r4,27,5,31
655 beq ..d_ran
656 addi r5,r5,0x0001
Stefan Roesec157d8e2005-08-01 16:41:48 +0200657..d_ran:
Wolfgang Denkf901a832005-08-06 01:42:58 +0200658 mtctr r5
Stefan Roesec157d8e2005-08-01 16:41:48 +0200659..d_ag:
Wolfgang Denkf901a832005-08-06 01:42:58 +0200660 dcbz r0,r3
661 addi r3,r3,32
662 bdnz ..d_ag
Stefan Roesee02c5212008-01-09 10:23:16 +0100663
664 /*
665 * Lock the init-ram/stack in d-cache, so that other regions
666 * may use d-cache as well
667 * Note, that this current implementation locks exactly 4k
668 * of d-cache, so please make sure that you don't define a
669 * bigger init-ram area. Take a look at the lwmon5 440EPx
670 * implementation as a reference.
671 */
672 msync
673 isync
674 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
675 lis r1,0x0201
676 ori r1,r1,0xf808
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200677 mtspr SPRN_DVLIM,r1
Stefan Roesee02c5212008-01-09 10:23:16 +0100678 lis r1,0x0808
679 ori r1,r1,0x0808
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200680 mtspr SPRN_DNV0,r1
681 mtspr SPRN_DNV1,r1
682 mtspr SPRN_DNV2,r1
683 mtspr SPRN_DNV3,r1
684 mtspr SPRN_DTV0,r1
685 mtspr SPRN_DTV1,r1
686 mtspr SPRN_DTV2,r1
687 mtspr SPRN_DTV3,r1
Stefan Roesee02c5212008-01-09 10:23:16 +0100688 msync
689 isync
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200690#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200691
692 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
693#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
694 /* not all PPC's have internal SRAM usable as L2-cache */
Stefan Roese2801b2d2008-03-11 15:05:50 +0100695#if defined(CONFIG_440GX) || \
696 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Feng Kan7d307932008-07-08 22:47:31 -0700697 defined(CONFIG_460SX)
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600698 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600699#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
700 lis r1, 0x0000
701 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
702 mtdcr L2_CACHE_CFG,r1
wdenkba56f622004-02-06 23:19:44 +0000703#endif
wdenk0442ed82002-11-03 10:24:00 +0000704
Stefan Roese887e2ec2006-09-07 11:51:23 +0200705 lis r2,0x7fff
wdenk0442ed82002-11-03 10:24:00 +0000706 ori r2,r2,0xffff
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600707 mfdcr r1,ISRAM0_DPC
wdenk0442ed82002-11-03 10:24:00 +0000708 and r1,r1,r2 /* Disable parity check */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600709 mtdcr ISRAM0_DPC,r1
710 mfdcr r1,ISRAM0_PMEG
Stefan Roese887e2ec2006-09-07 11:51:23 +0200711 and r1,r1,r2 /* Disable pwr mgmt */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600712 mtdcr ISRAM0_PMEG,r1
wdenk0442ed82002-11-03 10:24:00 +0000713
714 lis r1,0x8000 /* BAS = 8000_0000 */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100715#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
wdenkba56f622004-02-06 23:19:44 +0000716 ori r1,r1,0x0980 /* first 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600717 mtdcr ISRAM0_SB0CR,r1
wdenkba56f622004-02-06 23:19:44 +0000718 lis r1,0x8001
719 ori r1,r1,0x0980 /* second 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600720 mtdcr ISRAM0_SB1CR,r1
wdenkba56f622004-02-06 23:19:44 +0000721 lis r1, 0x8002
722 ori r1,r1, 0x0980 /* third 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600723 mtdcr ISRAM0_SB2CR,r1
wdenkba56f622004-02-06 23:19:44 +0000724 lis r1, 0x8003
725 ori r1,r1, 0x0980 /* fourth 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600726 mtdcr ISRAM0_SB3CR,r1
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600727#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
728 lis r1,0x0000 /* BAS = X_0000_0000 */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200729 ori r1,r1,0x0984 /* first 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600730 mtdcr ISRAM0_SB0CR,r1
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200731 lis r1,0x0001
732 ori r1,r1,0x0984 /* second 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600733 mtdcr ISRAM0_SB1CR,r1
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200734 lis r1, 0x0002
735 ori r1,r1, 0x0984 /* third 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600736 mtdcr ISRAM0_SB2CR,r1
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200737 lis r1, 0x0003
738 ori r1,r1, 0x0984 /* fourth 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600739 mtdcr ISRAM0_SB3CR,r1
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600740#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
741 lis r2,0x7fff
742 ori r2,r2,0xffff
743 mfdcr r1,ISRAM1_DPC
744 and r1,r1,r2 /* Disable parity check */
Wolfgang Denk455ae7e2008-12-16 01:02:17 +0100745 mtdcr ISRAM1_DPC,r1
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600746 mfdcr r1,ISRAM1_PMEG
747 and r1,r1,r2 /* Disable pwr mgmt */
748 mtdcr ISRAM1_PMEG,r1
749
750 lis r1,0x0004 /* BAS = 4_0004_0000 */
751 ori r1,r1,0x0984 /* 64k */
752 mtdcr ISRAM1_SB0CR,r1
753#endif
Feng Kan7d307932008-07-08 22:47:31 -0700754#elif defined(CONFIG_460SX)
755 lis r1,0x0000 /* BAS = 0000_0000 */
756 ori r1,r1,0x0B84 /* first 128k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600757 mtdcr ISRAM0_SB0CR,r1
Feng Kan7d307932008-07-08 22:47:31 -0700758 lis r1,0x0001
759 ori r1,r1,0x0B84 /* second 128k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600760 mtdcr ISRAM0_SB1CR,r1
Feng Kan7d307932008-07-08 22:47:31 -0700761 lis r1, 0x0002
762 ori r1,r1, 0x0B84 /* third 128k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600763 mtdcr ISRAM0_SB2CR,r1
Feng Kan7d307932008-07-08 22:47:31 -0700764 lis r1, 0x0003
765 ori r1,r1, 0x0B84 /* fourth 128k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600766 mtdcr ISRAM0_SB3CR,r1
Stefan Roese887e2ec2006-09-07 11:51:23 +0200767#elif defined(CONFIG_440GP)
wdenk0442ed82002-11-03 10:24:00 +0000768 ori r1,r1,0x0380 /* 8k rw */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600769 mtdcr ISRAM0_SB0CR,r1
770 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
wdenkba56f622004-02-06 23:19:44 +0000771#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200772#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
wdenk0442ed82002-11-03 10:24:00 +0000773
774 /*----------------------------------------------------------------*/
775 /* Setup the stack in internal SRAM */
776 /*----------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200777 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
778 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
wdenk0442ed82002-11-03 10:24:00 +0000779 li r0,0
780 stwu r0,-4(r1)
781 stwu r0,-4(r1) /* Terminate call chain */
782
783 stwu r1,-8(r1) /* Save back chain and move SP */
784 lis r0,RESET_VECTOR@h /* Address of reset vector */
785 ori r0,r0, RESET_VECTOR@l
786 stwu r1,-8(r1) /* Save back chain and move SP */
787 stw r0,+12(r1) /* Save return addr (underflow vect) */
788
Stefan Roese887e2ec2006-09-07 11:51:23 +0200789#ifdef CONFIG_NAND_SPL
Stefan Roese64852d02008-06-02 14:35:44 +0200790 bl nand_boot_common /* will not return */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200791#else
wdenk0442ed82002-11-03 10:24:00 +0000792 GET_GOT
Stefan Roese5568e612005-11-22 13:20:42 +0100793
794 bl cpu_init_f /* run low-level CPU init code (from Flash) */
wdenk0442ed82002-11-03 10:24:00 +0000795 bl board_init_f
Stefan Roese887e2ec2006-09-07 11:51:23 +0200796#endif
wdenk0442ed82002-11-03 10:24:00 +0000797
798#endif /* CONFIG_440 */
799
800/*****************************************************************************/
801#ifdef CONFIG_IOP480
802 /*----------------------------------------------------------------------- */
803 /* Set up some machine state registers. */
804 /*----------------------------------------------------------------------- */
805 addi r0,r0,0x0000 /* initialize r0 to zero */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200806 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
wdenk0442ed82002-11-03 10:24:00 +0000807 mttcr r0 /* timer control register */
808 mtexier r0 /* disable all interrupts */
wdenk0442ed82002-11-03 10:24:00 +0000809 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
810 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
811 mtdbsr r4 /* clear/reset the dbsr */
812 mtexisr r4 /* clear all pending interrupts */
813 addis r4,r0,0x8000
814 mtexier r4 /* enable critical exceptions */
815 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
816 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
817 mtiocr r4 /* since bit not used) & DRC to latch */
818 /* data bus on rising edge of CAS */
819 /*----------------------------------------------------------------------- */
820 /* Clear XER. */
821 /*----------------------------------------------------------------------- */
822 mtxer r0
823 /*----------------------------------------------------------------------- */
824 /* Invalidate i-cache and d-cache TAG arrays. */
825 /*----------------------------------------------------------------------- */
826 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
827 addi r4,0,1024 /* 1/4 of I-cache */
828..cloop:
829 iccci 0,r3
830 iccci r4,r3
831 dccci 0,r3
832 addic. r3,r3,-16 /* move back one cache line */
833 bne ..cloop /* loop back to do rest until r3 = 0 */
834
835 /* */
836 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
837 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
838 /* */
839
840 /* first copy IOP480 register base address into r3 */
841 addis r3,0,0x5000 /* IOP480 register base address hi */
842/* ori r3,r3,0x0000 / IOP480 register base address lo */
843
844#ifdef CONFIG_ADCIOP
845 /* use r4 as the working variable */
846 /* turn on CS3 (LOCCTL.7) */
847 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
848 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
849 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
850#endif
851
852#ifdef CONFIG_DASA_SIM
853 /* use r4 as the working variable */
854 /* turn on MA17 (LOCCTL.7) */
855 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
856 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
857 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
858#endif
859
860 /* turn on MA16..13 (LCS0BRD.12 = 0) */
861 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
862 andi. r4,r4,0xefff /* make bit 12 = 0 */
863 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
864
865 /* make sure above stores all comlete before going on */
866 sync
867
868 /* last thing, set local init status done bit (DEVINIT.31) */
869 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
870 oris r4,r4,0x8000 /* make bit 31 = 1 */
871 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
872
873 /* clear all pending interrupts and disable all interrupts */
874 li r4,-1 /* set p1 to 0xffffffff */
875 stw r4,0x1b0(r3) /* clear all pending interrupts */
876 stw r4,0x1b8(r3) /* clear all pending interrupts */
877 li r4,0 /* set r4 to 0 */
878 stw r4,0x1b4(r3) /* disable all interrupts */
879 stw r4,0x1bc(r3) /* disable all interrupts */
880
881 /* make sure above stores all comlete before going on */
882 sync
883
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700884 /* Set-up icache cacheability. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200885 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
886 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700887 mticcr r1
888 isync
wdenk0442ed82002-11-03 10:24:00 +0000889
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700890 /* Set-up dcache cacheability. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200891 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
892 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700893 mtdccr r1
wdenk0442ed82002-11-03 10:24:00 +0000894
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200895 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
896 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
wdenk0442ed82002-11-03 10:24:00 +0000897 li r0, 0 /* Make room for stack frame header and */
898 stwu r0, -4(r1) /* clear final stack frame so that */
899 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
900
901 GET_GOT /* initialize GOT access */
902
903 bl board_init_f /* run first part of init code (from Flash) */
904
905#endif /* CONFIG_IOP480 */
906
907/*****************************************************************************/
Stefan Roesee01bd212007-03-21 13:38:59 +0100908#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
909 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200910 defined(CONFIG_405EX) || defined(CONFIG_405)
wdenk0442ed82002-11-03 10:24:00 +0000911 /*----------------------------------------------------------------------- */
912 /* Clear and set up some registers. */
913 /*----------------------------------------------------------------------- */
914 addi r4,r0,0x0000
Stefan Roesedbbd1252007-10-05 17:10:59 +0200915#if !defined(CONFIG_405EX)
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200916 mtspr SPRN_SGR,r4
Stefan Roesedbbd1252007-10-05 17:10:59 +0200917#else
918 /*
919 * On 405EX, completely clearing the SGR leads to PPC hangup
920 * upon PCIe configuration access. The PCIe memory regions
921 * need to be guarded!
922 */
923 lis r3,0x0000
924 ori r3,r3,0x7FFC
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200925 mtspr SPRN_SGR,r3
Stefan Roesedbbd1252007-10-05 17:10:59 +0200926#endif
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200927 mtspr SPRN_DCWR,r4
wdenk0442ed82002-11-03 10:24:00 +0000928 mtesr r4 /* clear Exception Syndrome Reg */
929 mttcr r4 /* clear Timer Control Reg */
930 mtxer r4 /* clear Fixed-Point Exception Reg */
931 mtevpr r4 /* clear Exception Vector Prefix Reg */
wdenk0442ed82002-11-03 10:24:00 +0000932 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
933 /* dbsr is cleared by setting bits to 1) */
934 mtdbsr r4 /* clear/reset the dbsr */
935
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700936 /* Invalidate the i- and d-caches. */
wdenk0442ed82002-11-03 10:24:00 +0000937 bl invalidate_icache
938 bl invalidate_dcache
939
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700940 /* Set-up icache cacheability. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200941 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
942 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700943 mticcr r4
wdenk0442ed82002-11-03 10:24:00 +0000944 isync
945
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700946 /* Set-up dcache cacheability. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200947 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
948 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700949 mtdccr r4
wdenk0442ed82002-11-03 10:24:00 +0000950
Ricardo Ribalda Delgado1f4d5322008-10-21 18:29:46 +0200951#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
952 && !defined (CONFIG_XILINX_405)
wdenk0442ed82002-11-03 10:24:00 +0000953 /*----------------------------------------------------------------------- */
954 /* Tune the speed and size for flash CS0 */
955 /*----------------------------------------------------------------------- */
956 bl ext_bus_cntlr_init
957#endif
Stefan Roese64852d02008-06-02 14:35:44 +0200958
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200959#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
Stefan Roesedbbd1252007-10-05 17:10:59 +0200960 /*
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700961 * For boards that don't have OCM and can't use the data cache
962 * for their primordial stack, setup stack here directly after the
963 * SDRAM is initialized in ext_bus_cntlr_init.
Stefan Roesedbbd1252007-10-05 17:10:59 +0200964 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200965 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
966 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200967
968 li r0, 0 /* Make room for stack frame header and */
969 stwu r0, -4(r1) /* clear final stack frame so that */
970 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
971 /*
972 * Set up a dummy frame to store reset vector as return address.
973 * this causes stack underflow to reset board.
974 */
975 stwu r1, -8(r1) /* Save back chain and move SP */
976 lis r0, RESET_VECTOR@h /* Address of reset vector */
977 ori r0, r0, RESET_VECTOR@l
978 stwu r1, -8(r1) /* Save back chain and move SP */
979 stw r0, +12(r1) /* Save return addr (underflow vect) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200980#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
wdenk0442ed82002-11-03 10:24:00 +0000981
stroeseb867d702003-05-23 11:18:02 +0000982#if defined(CONFIG_405EP)
983 /*----------------------------------------------------------------------- */
984 /* DMA Status, clear to come up clean */
985 /*----------------------------------------------------------------------- */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200986 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200987 ori r3,r3, 0xFFFF
Stefan Roesed1c3b272009-09-09 16:25:29 +0200988 mtdcr DMASR, r3
stroeseb867d702003-05-23 11:18:02 +0000989
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200990 bl ppc405ep_init /* do ppc405ep specific init */
stroeseb867d702003-05-23 11:18:02 +0000991#endif /* CONFIG_405EP */
992
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200993#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
Stefan Roesee01bd212007-03-21 13:38:59 +0100994#if defined(CONFIG_405EZ)
995 /********************************************************************
996 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
997 *******************************************************************/
998 /*
999 * We can map the OCM on the PLB3, so map it at
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001000 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
Stefan Roesee01bd212007-03-21 13:38:59 +01001001 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001002 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1003 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
Stefan Roesedf8a24c2007-06-19 16:42:31 +02001004 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001005 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
Stefan Roesee01bd212007-03-21 13:38:59 +01001006 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001007 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
Stefan Roesee01bd212007-03-21 13:38:59 +01001008 isync
1009
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001010 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1011 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001012 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001013 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1014 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
Stefan Roesee01bd212007-03-21 13:38:59 +01001015 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001016 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1017 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001018 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001019 mtdcr OCM0_DISDPC,r3
Stefan Roesee01bd212007-03-21 13:38:59 +01001020
1021 isync
Stefan Roese3cb86f32007-03-24 15:45:34 +01001022#else /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +00001023 /********************************************************************
1024 * Setup OCM - On Chip Memory
1025 *******************************************************************/
1026 /* Setup OCM */
wdenk8bde7f72003-06-27 21:31:46 +00001027 lis r0, 0x7FFF
1028 ori r0, r0, 0xFFFF
Stefan Roesed1c3b272009-09-09 16:25:29 +02001029 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1030 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
Stefan Roese3cb86f32007-03-24 15:45:34 +01001031 and r3, r3, r0 /* disable data-side IRAM */
1032 and r4, r4, r0 /* disable data-side IRAM */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001033 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1034 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
wdenk8bde7f72003-06-27 21:31:46 +00001035 isync
wdenk0442ed82002-11-03 10:24:00 +00001036
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001037 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1038 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001039 mtdcr OCM0_DSARC, r3
wdenk0442ed82002-11-03 10:24:00 +00001040 addis r4, 0, 0xC000 /* OCM data area enabled */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001041 mtdcr OCM0_DSCNTL, r4
wdenk8bde7f72003-06-27 21:31:46 +00001042 isync
Stefan Roesee01bd212007-03-21 13:38:59 +01001043#endif /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +00001044#endif
1045
1046 /*----------------------------------------------------------------------- */
1047 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1048 /*----------------------------------------------------------------------- */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001049#ifdef CONFIG_SYS_INIT_DCACHE_CS
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001050 li r4, PBxAP
Stefan Roesed1c3b272009-09-09 16:25:29 +02001051 mtdcr EBC0_CFGADDR, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001052 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1053 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001054 mtdcr EBC0_CFGDATA, r4
wdenk0442ed82002-11-03 10:24:00 +00001055
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001056 addi r4, 0, PBxCR
Stefan Roesed1c3b272009-09-09 16:25:29 +02001057 mtdcr EBC0_CFGADDR, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001058 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1059 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001060 mtdcr EBC0_CFGDATA, r4
wdenk0442ed82002-11-03 10:24:00 +00001061
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001062 /*
1063 * Enable the data cache for the 128MB storage access control region
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001064 * at CONFIG_SYS_INIT_RAM_ADDR.
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001065 */
1066 mfdccr r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001067 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1068 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
wdenk0442ed82002-11-03 10:24:00 +00001069 mtdccr r4
1070
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001071 /*
1072 * Preallocate data cache lines to be used to avoid a subsequent
1073 * cache miss and an ensuing machine check exception when exceptions
1074 * are enabled.
1075 */
1076 li r0, 0
wdenk0442ed82002-11-03 10:24:00 +00001077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001078 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1079 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
wdenk0442ed82002-11-03 10:24:00 +00001080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001081 lis r4, CONFIG_SYS_INIT_RAM_END@h
1082 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001083
1084 /*
1085 * Convert the size, in bytes, to the number of cache lines/blocks
1086 * to preallocate.
1087 */
1088 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1089 srwi r5, r4, L1_CACHE_SHIFT
1090 beq ..load_counter
1091 addi r5, r5, 0x0001
1092..load_counter:
1093 mtctr r5
1094
1095 /* Preallocate the computed number of cache blocks. */
1096..alloc_dcache_block:
1097 dcba r0, r3
1098 addi r3, r3, L1_CACHE_BYTES
1099 bdnz ..alloc_dcache_block
1100 sync
1101
1102 /*
1103 * Load the initial stack pointer and data area and convert the size,
1104 * in bytes, to the number of words to initialize to a known value.
1105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001106 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1107 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001109 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1110 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
wdenk0442ed82002-11-03 10:24:00 +00001111 mtctr r4
1112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001113 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1114 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
wdenk0442ed82002-11-03 10:24:00 +00001115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001116 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1117 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
wdenk0442ed82002-11-03 10:24:00 +00001118
1119..stackloop:
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001120 stwu r4, -4(r2)
wdenk0442ed82002-11-03 10:24:00 +00001121 bdnz ..stackloop
1122
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001123 /*
1124 * Make room for stack frame header and clear final stack frame so
1125 * that stack backtraces terminate cleanly.
1126 */
1127 stwu r0, -4(r1)
1128 stwu r0, -4(r1)
1129
wdenk0442ed82002-11-03 10:24:00 +00001130 /*
1131 * Set up a dummy frame to store reset vector as return address.
1132 * this causes stack underflow to reset board.
1133 */
1134 stwu r1, -8(r1) /* Save back chain and move SP */
1135 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1136 ori r0, r0, RESET_VECTOR@l
1137 stwu r1, -8(r1) /* Save back chain and move SP */
1138 stw r0, +12(r1) /* Save return addr (underflow vect) */
1139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001140#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1141 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
wdenk0442ed82002-11-03 10:24:00 +00001142 /*
1143 * Stack in OCM.
1144 */
1145
1146 /* Set up Stack at top of OCM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001147 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1148 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
wdenk0442ed82002-11-03 10:24:00 +00001149
1150 /* Set up a zeroized stack frame so that backtrace works right */
1151 li r0, 0
1152 stwu r0, -4(r1)
1153 stwu r0, -4(r1)
1154
1155 /*
1156 * Set up a dummy frame to store reset vector as return address.
1157 * this causes stack underflow to reset board.
1158 */
1159 stwu r1, -8(r1) /* Save back chain and move SP */
1160 lis r0, RESET_VECTOR@h /* Address of reset vector */
1161 ori r0, r0, RESET_VECTOR@l
1162 stwu r1, -8(r1) /* Save back chain and move SP */
1163 stw r0, +12(r1) /* Save return addr (underflow vect) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001164#endif /* CONFIG_SYS_INIT_DCACHE_CS */
wdenk0442ed82002-11-03 10:24:00 +00001165
Stefan Roesec440bfe2007-06-06 11:42:13 +02001166#ifdef CONFIG_NAND_SPL
Stefan Roese64852d02008-06-02 14:35:44 +02001167 bl nand_boot_common /* will not return */
Stefan Roesec440bfe2007-06-06 11:42:13 +02001168#else
wdenk0442ed82002-11-03 10:24:00 +00001169 GET_GOT /* initialize GOT access */
1170
Wolfgang Denkf901a832005-08-06 01:42:58 +02001171 bl cpu_init_f /* run low-level CPU init code (from Flash) */
wdenk0442ed82002-11-03 10:24:00 +00001172
1173 /* NEVER RETURNS! */
1174 bl board_init_f /* run first part of init code (from Flash) */
Stefan Roesec440bfe2007-06-06 11:42:13 +02001175#endif /* CONFIG_NAND_SPL */
wdenk0442ed82002-11-03 10:24:00 +00001176
wdenk12f34242003-09-02 22:48:03 +00001177#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1178 /*----------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001179
1180
Stefan Roese887e2ec2006-09-07 11:51:23 +02001181#ifndef CONFIG_NAND_SPL
wdenk0442ed82002-11-03 10:24:00 +00001182/*
1183 * This code finishes saving the registers to the exception frame
1184 * and jumps to the appropriate handler for the exception.
1185 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1186 */
1187 .globl transfer_to_handler
1188transfer_to_handler:
1189 stw r22,_NIP(r21)
1190 lis r22,MSR_POW@h
1191 andc r23,r23,r22
1192 stw r23,_MSR(r21)
1193 SAVE_GPR(7, r21)
1194 SAVE_4GPRS(8, r21)
1195 SAVE_8GPRS(12, r21)
1196 SAVE_8GPRS(24, r21)
wdenk0442ed82002-11-03 10:24:00 +00001197 mflr r23
1198 andi. r24,r23,0x3f00 /* get vector offset */
1199 stw r24,TRAP(r21)
1200 li r22,0
1201 stw r22,RESULT(r21)
1202 mtspr SPRG2,r22 /* r1 is now kernel sp */
wdenk0442ed82002-11-03 10:24:00 +00001203 lwz r24,0(r23) /* virtual address of handler */
1204 lwz r23,4(r23) /* where to go when done */
1205 mtspr SRR0,r24
1206 mtspr SRR1,r20
1207 mtlr r23
1208 SYNC
1209 rfi /* jump to handler, enable MMU */
1210
1211int_return:
1212 mfmsr r28 /* Disable interrupts */
1213 li r4,0
1214 ori r4,r4,MSR_EE
1215 andc r28,r28,r4
1216 SYNC /* Some chip revs need this... */
1217 mtmsr r28
1218 SYNC
1219 lwz r2,_CTR(r1)
1220 lwz r0,_LINK(r1)
1221 mtctr r2
1222 mtlr r0
1223 lwz r2,_XER(r1)
1224 lwz r0,_CCR(r1)
1225 mtspr XER,r2
1226 mtcrf 0xFF,r0
1227 REST_10GPRS(3, r1)
1228 REST_10GPRS(13, r1)
1229 REST_8GPRS(23, r1)
1230 REST_GPR(31, r1)
1231 lwz r2,_NIP(r1) /* Restore environment */
1232 lwz r0,_MSR(r1)
1233 mtspr SRR0,r2
1234 mtspr SRR1,r0
1235 lwz r0,GPR0(r1)
1236 lwz r2,GPR2(r1)
1237 lwz r1,GPR1(r1)
1238 SYNC
1239 rfi
1240
1241crit_return:
1242 mfmsr r28 /* Disable interrupts */
1243 li r4,0
1244 ori r4,r4,MSR_EE
1245 andc r28,r28,r4
1246 SYNC /* Some chip revs need this... */
1247 mtmsr r28
1248 SYNC
1249 lwz r2,_CTR(r1)
1250 lwz r0,_LINK(r1)
1251 mtctr r2
1252 mtlr r0
1253 lwz r2,_XER(r1)
1254 lwz r0,_CCR(r1)
1255 mtspr XER,r2
1256 mtcrf 0xFF,r0
1257 REST_10GPRS(3, r1)
1258 REST_10GPRS(13, r1)
1259 REST_8GPRS(23, r1)
1260 REST_GPR(31, r1)
1261 lwz r2,_NIP(r1) /* Restore environment */
1262 lwz r0,_MSR(r1)
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001263 mtspr SPRN_CSRR0,r2
1264 mtspr SPRN_CSRR1,r0
wdenk0442ed82002-11-03 10:24:00 +00001265 lwz r0,GPR0(r1)
1266 lwz r2,GPR2(r1)
1267 lwz r1,GPR1(r1)
1268 SYNC
1269 rfci
1270
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001271#ifdef CONFIG_440
1272mck_return:
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001273 mfmsr r28 /* Disable interrupts */
1274 li r4,0
1275 ori r4,r4,MSR_EE
1276 andc r28,r28,r4
1277 SYNC /* Some chip revs need this... */
1278 mtmsr r28
1279 SYNC
1280 lwz r2,_CTR(r1)
1281 lwz r0,_LINK(r1)
1282 mtctr r2
1283 mtlr r0
1284 lwz r2,_XER(r1)
1285 lwz r0,_CCR(r1)
1286 mtspr XER,r2
1287 mtcrf 0xFF,r0
1288 REST_10GPRS(3, r1)
1289 REST_10GPRS(13, r1)
1290 REST_8GPRS(23, r1)
1291 REST_GPR(31, r1)
1292 lwz r2,_NIP(r1) /* Restore environment */
1293 lwz r0,_MSR(r1)
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001294 mtspr SPRN_MCSRR0,r2
1295 mtspr SPRN_MCSRR1,r0
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001296 lwz r0,GPR0(r1)
1297 lwz r2,GPR2(r1)
1298 lwz r1,GPR1(r1)
1299 SYNC
1300 rfmci
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001301#endif /* CONFIG_440 */
1302
1303
wdenk0442ed82002-11-03 10:24:00 +00001304 .globl get_pvr
1305get_pvr:
1306 mfspr r3, PVR
1307 blr
1308
wdenk0442ed82002-11-03 10:24:00 +00001309/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001310/* Function: out16 */
1311/* Description: Output 16 bits */
1312/*------------------------------------------------------------------------------- */
1313 .globl out16
1314out16:
1315 sth r4,0x0000(r3)
1316 blr
1317
1318/*------------------------------------------------------------------------------- */
1319/* Function: out16r */
1320/* Description: Byte reverse and output 16 bits */
1321/*------------------------------------------------------------------------------- */
1322 .globl out16r
1323out16r:
1324 sthbrx r4,r0,r3
1325 blr
1326
1327/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001328/* Function: out32r */
1329/* Description: Byte reverse and output 32 bits */
1330/*------------------------------------------------------------------------------- */
1331 .globl out32r
1332out32r:
1333 stwbrx r4,r0,r3
1334 blr
1335
1336/*------------------------------------------------------------------------------- */
1337/* Function: in16 */
1338/* Description: Input 16 bits */
1339/*------------------------------------------------------------------------------- */
1340 .globl in16
1341in16:
1342 lhz r3,0x0000(r3)
1343 blr
1344
1345/*------------------------------------------------------------------------------- */
1346/* Function: in16r */
1347/* Description: Input 16 bits and byte reverse */
1348/*------------------------------------------------------------------------------- */
1349 .globl in16r
1350in16r:
1351 lhbrx r3,r0,r3
1352 blr
1353
1354/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001355/* Function: in32r */
1356/* Description: Input 32 bits and byte reverse */
1357/*------------------------------------------------------------------------------- */
1358 .globl in32r
1359in32r:
1360 lwbrx r3,r0,r3
1361 blr
1362
wdenk0442ed82002-11-03 10:24:00 +00001363/*
1364 * void relocate_code (addr_sp, gd, addr_moni)
1365 *
1366 * This "function" does not return, instead it continues in RAM
1367 * after relocating the monitor code.
1368 *
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001369 * r3 = Relocated stack pointer
1370 * r4 = Relocated global data pointer
1371 * r5 = Relocated text pointer
wdenk0442ed82002-11-03 10:24:00 +00001372 */
1373 .globl relocate_code
1374relocate_code:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001375#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
Stefan Roese9b94ac62007-10-31 17:55:58 +01001376 /*
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001377 * We need to flush the initial global data (gd_t) before the dcache
1378 * will be invalidated.
Stefan Roese9b94ac62007-10-31 17:55:58 +01001379 */
1380
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001381 /* Save registers */
1382 mr r9, r3
1383 mr r10, r4
1384 mr r11, r5
Stefan Roese9b94ac62007-10-31 17:55:58 +01001385
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001386 /* Flush initial global data range */
1387 mr r3, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001388 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
Stefan Roese9b94ac62007-10-31 17:55:58 +01001389 bl flush_dcache_range
1390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001391#if defined(CONFIG_SYS_INIT_DCACHE_CS)
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001392 /*
1393 * Undo the earlier data cache set-up for the primordial stack and
1394 * data area. First, invalidate the data cache and then disable data
1395 * cacheability for that area. Finally, restore the EBC values, if
1396 * any.
1397 */
1398
1399 /* Invalidate the primordial stack and data area in cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001400 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1401 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001403 lis r4, CONFIG_SYS_INIT_RAM_END@h
1404 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001405 add r4, r4, r3
1406
1407 bl invalidate_dcache_range
1408
1409 /* Disable cacheability for the region */
1410 mfdccr r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001411 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1412 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001413 and r3, r3, r4
1414 mtdccr r3
1415
1416 /* Restore the EBC parameters */
1417 li r3, PBxAP
Stefan Roesed1c3b272009-09-09 16:25:29 +02001418 mtdcr EBC0_CFGADDR, r3
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001419 lis r3, PBxAP_VAL@h
1420 ori r3, r3, PBxAP_VAL@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001421 mtdcr EBC0_CFGDATA, r3
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001422
1423 li r3, PBxCR
Stefan Roesed1c3b272009-09-09 16:25:29 +02001424 mtdcr EBC0_CFGADDR, r3
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001425 lis r3, PBxCR_VAL@h
1426 ori r3, r3, PBxCR_VAL@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001427 mtdcr EBC0_CFGDATA, r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001428#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001429
1430 /* Restore registers */
1431 mr r3, r9
1432 mr r4, r10
1433 mr r5, r11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001434#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
Stefan Roesee02c5212008-01-09 10:23:16 +01001435
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001436#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Stefan Roesee02c5212008-01-09 10:23:16 +01001437 /*
1438 * Unlock the previously locked d-cache
1439 */
1440 msync
1441 isync
1442 /* set TFLOOR/NFLOOR to 0 again */
1443 lis r6,0x0001
1444 ori r6,r6,0xf800
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001445 mtspr SPRN_DVLIM,r6
Stefan Roesee02c5212008-01-09 10:23:16 +01001446 lis r6,0x0000
1447 ori r6,r6,0x0000
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001448 mtspr SPRN_DNV0,r6
1449 mtspr SPRN_DNV1,r6
1450 mtspr SPRN_DNV2,r6
1451 mtspr SPRN_DNV3,r6
1452 mtspr SPRN_DTV0,r6
1453 mtspr SPRN_DTV1,r6
1454 mtspr SPRN_DTV2,r6
1455 mtspr SPRN_DTV3,r6
Stefan Roesee02c5212008-01-09 10:23:16 +01001456 msync
1457 isync
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001458#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
Stefan Roesee02c5212008-01-09 10:23:16 +01001459
Stefan Roese887e2ec2006-09-07 11:51:23 +02001460#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1461 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese2801b2d2008-03-11 15:05:50 +01001462 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Feng Kan7d307932008-07-08 22:47:31 -07001463 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1464 defined(CONFIG_460SX)
Stefan Roesea4c8d132006-06-02 16:18:04 +02001465 /*
1466 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1467 * to speed up the boot process. Now this cache needs to be disabled.
1468 */
1469 iccci 0,0 /* Invalidate inst cache */
1470 dccci 0,0 /* Invalidate data cache, now no longer our stack */
Stefan Roesec157d8e2005-08-01 16:41:48 +02001471 sync
Stefan Roesea4c8d132006-06-02 16:18:04 +02001472 isync
Stefan Roese25fb4ea2008-11-20 11:46:20 +01001473
1474 /* Clear all potential pending exceptions */
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001475 mfspr r1,SPRN_MCSR
1476 mtspr SPRN_MCSR,r1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001477#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
1478 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
Niklaus Giger85dc2a72007-11-30 18:35:11 +01001479#else
1480 addi r1,r0,0x0000 /* Default TLB entry is #0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001481#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
Stefan Roesec157d8e2005-08-01 16:41:48 +02001482 tlbre r0,r1,0x0002 /* Read contents */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001483 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001484 tlbwe r0,r1,0x0002 /* Save it out */
Stefan Roesea4c8d132006-06-02 16:18:04 +02001485 sync
Stefan Roesec157d8e2005-08-01 16:41:48 +02001486 isync
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001487#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
wdenk0442ed82002-11-03 10:24:00 +00001488 mr r1, r3 /* Set new stack pointer */
1489 mr r9, r4 /* Save copy of Init Data pointer */
1490 mr r10, r5 /* Save copy of Destination Address */
1491
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001492 GET_GOT
wdenk0442ed82002-11-03 10:24:00 +00001493 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001494 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1495 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +00001496 lwz r5, GOT(__init_end)
1497 sub r5, r5, r4
Stefan Roese9b94ac62007-10-31 17:55:58 +01001498 li r6, L1_CACHE_BYTES /* Cache Line Size */
wdenk0442ed82002-11-03 10:24:00 +00001499
1500 /*
1501 * Fix GOT pointer:
1502 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001503 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenk0442ed82002-11-03 10:24:00 +00001504 *
1505 * Offset:
1506 */
1507 sub r15, r10, r4
1508
1509 /* First our own GOT */
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001510 add r12, r12, r15
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001511 /* then the one used by the C code */
wdenk0442ed82002-11-03 10:24:00 +00001512 add r30, r30, r15
1513
1514 /*
1515 * Now relocate code
1516 */
1517
1518 cmplw cr1,r3,r4
1519 addi r0,r5,3
1520 srwi. r0,r0,2
1521 beq cr1,4f /* In place copy is not necessary */
1522 beq 7f /* Protect against 0 count */
1523 mtctr r0
1524 bge cr1,2f
1525
1526 la r8,-4(r4)
1527 la r7,-4(r3)
15281: lwzu r0,4(r8)
1529 stwu r0,4(r7)
1530 bdnz 1b
1531 b 4f
1532
15332: slwi r0,r0,2
1534 add r8,r4,r0
1535 add r7,r3,r0
15363: lwzu r0,-4(r8)
1537 stwu r0,-4(r7)
1538 bdnz 3b
1539
1540/*
1541 * Now flush the cache: note that we must start from a cache aligned
1542 * address. Otherwise we might miss one cache line.
1543 */
15444: cmpwi r6,0
1545 add r5,r3,r5
1546 beq 7f /* Always flush prefetch queue in any case */
1547 subi r0,r6,1
1548 andc r3,r3,r0
1549 mr r4,r3
15505: dcbst 0,r4
1551 add r4,r4,r6
1552 cmplw r4,r5
1553 blt 5b
1554 sync /* Wait for all dcbst to complete on bus */
1555 mr r4,r3
15566: icbi 0,r4
1557 add r4,r4,r6
1558 cmplw r4,r5
1559 blt 6b
15607: sync /* Wait for all icbi to complete on bus */
1561 isync
1562
1563/*
1564 * We are done. Do not return, instead branch to second part of board
1565 * initialization, now running from RAM.
1566 */
1567
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001568 addi r0, r10, in_ram - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001569 mtlr r0
1570 blr /* NEVER RETURNS! */
1571
1572in_ram:
1573
1574 /*
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001575 * Relocation Function, r12 point to got2+0x8000
wdenk0442ed82002-11-03 10:24:00 +00001576 *
1577 * Adjust got2 pointers, no need to check for 0, this code
1578 * already puts a few entries in the table.
1579 */
1580 li r0,__got2_entries@sectoff@l
1581 la r3,GOT(_GOT2_TABLE_)
1582 lwz r11,GOT(_GOT2_TABLE_)
1583 mtctr r0
1584 sub r11,r3,r11
1585 addi r3,r3,-4
15861: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02001587 cmpwi r0,0
1588 beq- 2f
wdenk0442ed82002-11-03 10:24:00 +00001589 add r0,r0,r11
1590 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +020015912: bdnz 1b
wdenk0442ed82002-11-03 10:24:00 +00001592
1593 /*
1594 * Now adjust the fixups and the pointers to the fixups
1595 * in case we need to move ourselves again.
1596 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02001597 li r0,__fixup_entries@sectoff@l
wdenk0442ed82002-11-03 10:24:00 +00001598 lwz r3,GOT(_FIXUP_TABLE_)
1599 cmpwi r0,0
1600 mtctr r0
1601 addi r3,r3,-4
1602 beq 4f
16033: lwzu r4,4(r3)
1604 lwzux r0,r4,r11
1605 add r0,r0,r11
1606 stw r10,0(r3)
1607 stw r0,0(r4)
1608 bdnz 3b
16094:
1610clear_bss:
1611 /*
1612 * Now clear BSS segment
1613 */
wdenk5d232d02003-05-22 22:52:13 +00001614 lwz r3,GOT(__bss_start)
wdenk0442ed82002-11-03 10:24:00 +00001615 lwz r4,GOT(_end)
1616
1617 cmplw 0, r3, r4
Anatolij Gustschin42ed33f2007-12-05 17:43:20 +01001618 beq 7f
wdenk0442ed82002-11-03 10:24:00 +00001619
1620 li r0, 0
Anatolij Gustschin42ed33f2007-12-05 17:43:20 +01001621
1622 andi. r5, r4, 3
1623 beq 6f
1624 sub r4, r4, r5
1625 mtctr r5
1626 mr r5, r4
16275: stb r0, 0(r5)
1628 addi r5, r5, 1
1629 bdnz 5b
16306:
wdenk0442ed82002-11-03 10:24:00 +00001631 stw r0, 0(r3)
1632 addi r3, r3, 4
1633 cmplw 0, r3, r4
Anatolij Gustschin42ed33f2007-12-05 17:43:20 +01001634 bne 6b
wdenk0442ed82002-11-03 10:24:00 +00001635
Anatolij Gustschin42ed33f2007-12-05 17:43:20 +010016367:
wdenk0442ed82002-11-03 10:24:00 +00001637 mr r3, r9 /* Init Data pointer */
1638 mr r4, r10 /* Destination Address */
1639 bl board_init_r
1640
wdenk0442ed82002-11-03 10:24:00 +00001641 /*
1642 * Copy exception vector code to low memory
1643 *
1644 * r3: dest_addr
1645 * r7: source address, r8: end address, r9: target address
1646 */
1647 .globl trap_init
1648trap_init:
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001649 mflr r4 /* save link register */
1650 GET_GOT
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001651 lwz r7, GOT(_start_of_vectors)
wdenk0442ed82002-11-03 10:24:00 +00001652 lwz r8, GOT(_end_of_vectors)
1653
wdenk682011f2003-06-03 23:54:09 +00001654 li r9, 0x100 /* reset vector always at 0x100 */
wdenk0442ed82002-11-03 10:24:00 +00001655
1656 cmplw 0, r7, r8
1657 bgelr /* return if r7>=r8 - just in case */
wdenk0442ed82002-11-03 10:24:00 +000016581:
1659 lwz r0, 0(r7)
1660 stw r0, 0(r9)
1661 addi r7, r7, 4
1662 addi r9, r9, 4
1663 cmplw 0, r7, r8
1664 bne 1b
1665
1666 /*
1667 * relocate `hdlr' and `int_return' entries
1668 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001669 li r7, .L_MachineCheck - _start + _START_OFFSET
1670 li r8, Alignment - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +000016712:
1672 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001673 addi r7, r7, 0x100 /* next exception vector */
wdenk0442ed82002-11-03 10:24:00 +00001674 cmplw 0, r7, r8
1675 blt 2b
1676
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001677 li r7, .L_Alignment - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001678 bl trap_reloc
1679
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001680 li r7, .L_ProgramCheck - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001681 bl trap_reloc
1682
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001683#ifdef CONFIG_440
1684 li r7, .L_FPUnavailable - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001685 bl trap_reloc
wdenk0442ed82002-11-03 10:24:00 +00001686
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001687 li r7, .L_Decrementer - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001688 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001689
1690 li r7, .L_APU - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001691 bl trap_reloc
Stefan Roesedf8a24c2007-06-19 16:42:31 +02001692
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001693 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1694 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001695
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001696 li r7, .L_DataTLBError - _start + _START_OFFSET
1697 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001698#else /* CONFIG_440 */
1699 li r7, .L_PIT - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001700 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001701
1702 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001703 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001704
1705 li r7, .L_DataTLBMiss - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001706 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001707#endif /* CONFIG_440 */
1708
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001709 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1710 bl trap_reloc
wdenk0442ed82002-11-03 10:24:00 +00001711
Stefan Roese887e2ec2006-09-07 11:51:23 +02001712#if !defined(CONFIG_440)
Stefan Roese9a7b4082006-03-13 09:42:28 +01001713 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1714 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1715 mtmsr r7 /* change MSR */
1716#else
Stefan Roese887e2ec2006-09-07 11:51:23 +02001717 bl __440_msr_set
1718 b __440_msr_continue
Stefan Roese9a7b4082006-03-13 09:42:28 +01001719
Stefan Roese887e2ec2006-09-07 11:51:23 +02001720__440_msr_set:
Stefan Roese9a7b4082006-03-13 09:42:28 +01001721 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1722 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001723 mtspr SPRN_SRR1,r7
Stefan Roese9a7b4082006-03-13 09:42:28 +01001724 mflr r7
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001725 mtspr SPRN_SRR0,r7
Stefan Roese9a7b4082006-03-13 09:42:28 +01001726 rfi
Stefan Roese887e2ec2006-09-07 11:51:23 +02001727__440_msr_continue:
Stefan Roese9a7b4082006-03-13 09:42:28 +01001728#endif
1729
wdenk0442ed82002-11-03 10:24:00 +00001730 mtlr r4 /* restore link register */
1731 blr
1732
Stefan Roesecf959c72007-06-01 15:27:11 +02001733#if defined(CONFIG_440)
1734/*----------------------------------------------------------------------------+
1735| dcbz_area.
1736+----------------------------------------------------------------------------*/
1737 function_prolog(dcbz_area)
1738 rlwinm. r5,r4,0,27,31
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001739 rlwinm r5,r4,27,5,31
1740 beq ..d_ra2
1741 addi r5,r5,0x0001
1742..d_ra2:mtctr r5
1743..d_ag2:dcbz r0,r3
1744 addi r3,r3,32
1745 bdnz ..d_ag2
Stefan Roesecf959c72007-06-01 15:27:11 +02001746 sync
1747 blr
1748 function_epilog(dcbz_area)
Stefan Roesecf959c72007-06-01 15:27:11 +02001749#endif /* CONFIG_440 */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001750#endif /* CONFIG_NAND_SPL */
stroeseb867d702003-05-23 11:18:02 +00001751
Stefan Roesecf959c72007-06-01 15:27:11 +02001752/*------------------------------------------------------------------------------- */
1753/* Function: in8 */
1754/* Description: Input 8 bits */
1755/*------------------------------------------------------------------------------- */
1756 .globl in8
1757in8:
1758 lbz r3,0x0000(r3)
1759 blr
1760
1761/*------------------------------------------------------------------------------- */
1762/* Function: out8 */
1763/* Description: Output 8 bits */
1764/*------------------------------------------------------------------------------- */
1765 .globl out8
1766out8:
1767 stb r4,0x0000(r3)
1768 blr
1769
1770/*------------------------------------------------------------------------------- */
1771/* Function: out32 */
1772/* Description: Output 32 bits */
1773/*------------------------------------------------------------------------------- */
1774 .globl out32
1775out32:
1776 stw r4,0x0000(r3)
1777 blr
1778
1779/*------------------------------------------------------------------------------- */
1780/* Function: in32 */
1781/* Description: Input 32 bits */
1782/*------------------------------------------------------------------------------- */
1783 .globl in32
1784in32:
1785 lwz 3,0x0000(3)
1786 blr
stroeseb867d702003-05-23 11:18:02 +00001787
1788/**************************************************************************/
Wolfgang Denkf901a832005-08-06 01:42:58 +02001789/* PPC405EP specific stuff */
stroeseb867d702003-05-23 11:18:02 +00001790/**************************************************************************/
1791#ifdef CONFIG_405EP
1792ppc405ep_init:
stroeseb828dda2003-12-09 14:54:43 +00001793
Stefan Roesec157d8e2005-08-01 16:41:48 +02001794#ifdef CONFIG_BUBINGA
stroeseb828dda2003-12-09 14:54:43 +00001795 /*
1796 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1797 * function) to support FPGA and NVRAM accesses below.
1798 */
1799
1800 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1801 ori r3,r3,GPIO0_OSRH@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001802 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1803 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
stroeseb828dda2003-12-09 14:54:43 +00001804 stw r4,0(r3)
1805 lis r3,GPIO0_OSRL@h
1806 ori r3,r3,GPIO0_OSRL@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001807 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1808 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
stroeseb828dda2003-12-09 14:54:43 +00001809 stw r4,0(r3)
1810
1811 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1812 ori r3,r3,GPIO0_ISR1H@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001813 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1814 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
stroeseb828dda2003-12-09 14:54:43 +00001815 stw r4,0(r3)
1816 lis r3,GPIO0_ISR1L@h
1817 ori r3,r3,GPIO0_ISR1L@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001818 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1819 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
stroeseb828dda2003-12-09 14:54:43 +00001820 stw r4,0(r3)
1821
1822 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1823 ori r3,r3,GPIO0_TSRH@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001824 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1825 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
stroeseb828dda2003-12-09 14:54:43 +00001826 stw r4,0(r3)
1827 lis r3,GPIO0_TSRL@h
1828 ori r3,r3,GPIO0_TSRL@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001829 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1830 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
stroeseb828dda2003-12-09 14:54:43 +00001831 stw r4,0(r3)
1832
1833 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1834 ori r3,r3,GPIO0_TCR@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001835 lis r4,CONFIG_SYS_GPIO0_TCR@h
1836 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
stroeseb828dda2003-12-09 14:54:43 +00001837 stw r4,0(r3)
1838
Stefan Roesed1c3b272009-09-09 16:25:29 +02001839 li r3,PB1AP /* program EBC bank 1 for RTC access */
1840 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001841 lis r3,CONFIG_SYS_EBC_PB1AP@h
1842 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001843 mtdcr EBC0_CFGDATA,r3
1844 li r3,PB1CR
1845 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001846 lis r3,CONFIG_SYS_EBC_PB1CR@h
1847 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001848 mtdcr EBC0_CFGDATA,r3
stroeseb828dda2003-12-09 14:54:43 +00001849
Stefan Roesed1c3b272009-09-09 16:25:29 +02001850 li r3,PB1AP /* program EBC bank 1 for RTC access */
1851 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001852 lis r3,CONFIG_SYS_EBC_PB1AP@h
1853 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001854 mtdcr EBC0_CFGDATA,r3
1855 li r3,PB1CR
1856 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001857 lis r3,CONFIG_SYS_EBC_PB1CR@h
1858 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001859 mtdcr EBC0_CFGDATA,r3
stroeseb828dda2003-12-09 14:54:43 +00001860
Stefan Roesed1c3b272009-09-09 16:25:29 +02001861 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1862 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001863 lis r3,CONFIG_SYS_EBC_PB4AP@h
1864 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001865 mtdcr EBC0_CFGDATA,r3
1866 li r3,PB4CR
1867 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001868 lis r3,CONFIG_SYS_EBC_PB4CR@h
1869 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001870 mtdcr EBC0_CFGDATA,r3
stroeseb828dda2003-12-09 14:54:43 +00001871#endif
1872
wdenk8bde7f72003-06-27 21:31:46 +00001873 /*
1874 !-----------------------------------------------------------------------
1875 ! Check to see if chip is in bypass mode.
1876 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1877 ! CPU reset Otherwise, skip this step and keep going.
Wolfgang Denkf901a832005-08-06 01:42:58 +02001878 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1879 ! will not be fast enough for the SDRAM (min 66MHz)
wdenk8bde7f72003-06-27 21:31:46 +00001880 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001881 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001882 mfdcr r5, CPC0_PLLMR1
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001883 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001884 cmpi cr0,0,r4,0x1
stroeseb867d702003-05-23 11:18:02 +00001885
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001886 beq pll_done /* if SSCS =b'1' then PLL has */
1887 /* already been set */
1888 /* and CPU has been reset */
1889 /* so skip to next section */
stroeseb867d702003-05-23 11:18:02 +00001890
Stefan Roesec157d8e2005-08-01 16:41:48 +02001891#ifdef CONFIG_BUBINGA
stroeseb867d702003-05-23 11:18:02 +00001892 /*
wdenk8bde7f72003-06-27 21:31:46 +00001893 !-----------------------------------------------------------------------
1894 ! Read NVRAM to get value to write in PLLMR.
1895 ! If value has not been correctly saved, write default value
1896 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1897 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1898 !
1899 ! WARNING: This code assumes the first three words in the nvram_t
Wolfgang Denkf901a832005-08-06 01:42:58 +02001900 ! structure in openbios.h. Changing the beginning of
1901 ! the structure will break this code.
wdenk8bde7f72003-06-27 21:31:46 +00001902 !
1903 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001904 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001905 addis r3,0,NVRAM_BASE@h
1906 addi r3,r3,NVRAM_BASE@l
stroeseb867d702003-05-23 11:18:02 +00001907
Wolfgang Denkf901a832005-08-06 01:42:58 +02001908 lwz r4, 0(r3)
1909 addis r5,0,NVRVFY1@h
1910 addi r5,r5,NVRVFY1@l
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001911 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
Wolfgang Denkf901a832005-08-06 01:42:58 +02001912 bne ..no_pllset
1913 addi r3,r3,4
1914 lwz r4, 0(r3)
1915 addis r5,0,NVRVFY2@h
1916 addi r5,r5,NVRVFY2@l
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001917 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001918 bne ..no_pllset
1919 addi r3,r3,8 /* Skip over conf_size */
1920 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1921 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1922 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1923 cmpi cr0,0,r5,1 /* See if PLL is locked */
1924 beq pll_write
stroeseb867d702003-05-23 11:18:02 +00001925..no_pllset:
Stefan Roesec157d8e2005-08-01 16:41:48 +02001926#endif /* CONFIG_BUBINGA */
stroeseb867d702003-05-23 11:18:02 +00001927
John Otkend4024bb2007-07-26 17:49:11 +02001928#ifdef CONFIG_TAIHU
1929 mfdcr r4, CPC0_BOOT
1930 andi. r5, r4, CPC0_BOOT_SEP@l
1931 bne strap_1 /* serial eeprom present */
1932 addis r5,0,CPLD_REG0_ADDR@h
1933 ori r5,r5,CPLD_REG0_ADDR@l
1934 andi. r5, r5, 0x10
1935 bne _pci_66mhz
1936#endif /* CONFIG_TAIHU */
1937
Stefan Roese779e9752007-08-14 14:44:41 +02001938#if defined(CONFIG_ZEUS)
1939 mfdcr r4, CPC0_BOOT
1940 andi. r5, r4, CPC0_BOOT_SEP@l
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001941 bne strap_1 /* serial eeprom present */
Stefan Roese779e9752007-08-14 14:44:41 +02001942 lis r3,0x0000
1943 addi r3,r3,0x3030
1944 lis r4,0x8042
1945 addi r4,r4,0x223e
1946 b 1f
1947strap_1:
1948 mfdcr r3, CPC0_PLLMR0
1949 mfdcr r4, CPC0_PLLMR1
1950 b 1f
1951#endif
1952
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001953 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1954 ori r3,r3,PLLMR0_DEFAULT@l /* */
1955 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1956 ori r4,r4,PLLMR1_DEFAULT@l /* */
stroeseb867d702003-05-23 11:18:02 +00001957
John Otkend4024bb2007-07-26 17:49:11 +02001958#ifdef CONFIG_TAIHU
1959 b 1f
1960_pci_66mhz:
1961 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1962 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1963 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1964 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1965 b 1f
1966strap_1:
1967 mfdcr r3, CPC0_PLLMR0
1968 mfdcr r4, CPC0_PLLMR1
John Otkend4024bb2007-07-26 17:49:11 +02001969#endif /* CONFIG_TAIHU */
1970
Stefan Roese779e9752007-08-14 14:44:41 +020019711:
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001972 b pll_write /* Write the CPC0_PLLMR with new value */
stroeseb867d702003-05-23 11:18:02 +00001973
1974pll_done:
wdenk8bde7f72003-06-27 21:31:46 +00001975 /*
1976 !-----------------------------------------------------------------------
1977 ! Clear Soft Reset Register
1978 ! This is needed to enable PCI if not booting from serial EPROM
1979 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001980 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001981 addi r3, 0, 0x0
1982 mtdcr CPC0_SRR, r3
stroeseb867d702003-05-23 11:18:02 +00001983
Wolfgang Denkf901a832005-08-06 01:42:58 +02001984 addis r3,0,0x0010
1985 mtctr r3
stroeseb867d702003-05-23 11:18:02 +00001986pci_wait:
Wolfgang Denkf901a832005-08-06 01:42:58 +02001987 bdnz pci_wait
stroeseb867d702003-05-23 11:18:02 +00001988
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001989 blr /* return to main code */
stroeseb867d702003-05-23 11:18:02 +00001990
1991/*
1992!-----------------------------------------------------------------------------
Wolfgang Denkf901a832005-08-06 01:42:58 +02001993! Function: pll_write
1994! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1995! That is:
1996! 1. Pll is first disabled (de-activated by putting in bypass mode)
1997! 2. PLL is reset
1998! 3. Clock dividers are set while PLL is held in reset and bypassed
1999! 4. PLL Reset is cleared
2000! 5. Wait 100us for PLL to lock
2001! 6. A core reset is performed
stroeseb867d702003-05-23 11:18:02 +00002002! Input: r3 = Value to write to CPC0_PLLMR0
2003! Input: r4 = Value to write to CPC0_PLLMR1
2004! Output r3 = none
2005!-----------------------------------------------------------------------------
2006*/
Matthias Fuchs0580e482009-07-06 16:27:33 +02002007 .globl pll_write
stroeseb867d702003-05-23 11:18:02 +00002008pll_write:
wdenk8bde7f72003-06-27 21:31:46 +00002009 mfdcr r5, CPC0_UCR
2010 andis. r5,r5,0xFFFF
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002011 ori r5,r5,0x0101 /* Stop the UART clocks */
2012 mtdcr CPC0_UCR,r5 /* Before changing PLL */
stroeseb867d702003-05-23 11:18:02 +00002013
wdenk8bde7f72003-06-27 21:31:46 +00002014 mfdcr r5, CPC0_PLLMR1
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002015 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002016 mtdcr CPC0_PLLMR1,r5
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002017 oris r5,r5,0x4000 /* Set PLL Reset */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002018 mtdcr CPC0_PLLMR1,r5
stroeseb867d702003-05-23 11:18:02 +00002019
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002020 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2021 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2022 oris r5,r5,0x4000 /* Set PLL Reset */
2023 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2024 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002025 mtdcr CPC0_PLLMR1,r5
stroeseb867d702003-05-23 11:18:02 +00002026
2027 /*
wdenk8bde7f72003-06-27 21:31:46 +00002028 ! Wait min of 100us for PLL to lock.
2029 ! See CMOS 27E databook for more info.
2030 ! At 200MHz, that means waiting 20,000 instructions
stroeseb867d702003-05-23 11:18:02 +00002031 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002032 addi r3,0,20000 /* 2000 = 0x4e20 */
2033 mtctr r3
stroeseb867d702003-05-23 11:18:02 +00002034pll_wait:
Wolfgang Denkf901a832005-08-06 01:42:58 +02002035 bdnz pll_wait
stroeseb867d702003-05-23 11:18:02 +00002036
Wolfgang Denkf901a832005-08-06 01:42:58 +02002037 oris r5,r5,0x8000 /* Enable PLL */
2038 mtdcr CPC0_PLLMR1,r5 /* Engage */
stroeseb867d702003-05-23 11:18:02 +00002039
wdenk8bde7f72003-06-27 21:31:46 +00002040 /*
2041 * Reset CPU to guarantee timings are OK
2042 * Not sure if this is needed...
2043 */
2044 addis r3,0,0x1000
Matthias Fuchs58ea1422009-07-22 17:27:56 +02002045 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002046 /* execution will continue from the poweron */
2047 /* vector of 0xfffffffc */
stroeseb867d702003-05-23 11:18:02 +00002048#endif /* CONFIG_405EP */
Stefan Roese4745aca2007-02-20 10:57:08 +01002049
2050#if defined(CONFIG_440)
Stefan Roese4745aca2007-02-20 10:57:08 +01002051/*----------------------------------------------------------------------------+
2052| mttlb3.
2053+----------------------------------------------------------------------------*/
2054 function_prolog(mttlb3)
2055 TLBWE(4,3,2)
2056 blr
2057 function_epilog(mttlb3)
2058
2059/*----------------------------------------------------------------------------+
2060| mftlb3.
2061+----------------------------------------------------------------------------*/
2062 function_prolog(mftlb3)
Wolfgang Denk74357112007-02-27 14:26:04 +01002063 TLBRE(3,3,2)
Stefan Roese4745aca2007-02-20 10:57:08 +01002064 blr
2065 function_epilog(mftlb3)
2066
2067/*----------------------------------------------------------------------------+
2068| mttlb2.
2069+----------------------------------------------------------------------------*/
2070 function_prolog(mttlb2)
2071 TLBWE(4,3,1)
2072 blr
2073 function_epilog(mttlb2)
2074
2075/*----------------------------------------------------------------------------+
2076| mftlb2.
2077+----------------------------------------------------------------------------*/
2078 function_prolog(mftlb2)
Wolfgang Denk74357112007-02-27 14:26:04 +01002079 TLBRE(3,3,1)
Stefan Roese4745aca2007-02-20 10:57:08 +01002080 blr
2081 function_epilog(mftlb2)
2082
2083/*----------------------------------------------------------------------------+
2084| mttlb1.
2085+----------------------------------------------------------------------------*/
2086 function_prolog(mttlb1)
2087 TLBWE(4,3,0)
2088 blr
2089 function_epilog(mttlb1)
2090
2091/*----------------------------------------------------------------------------+
2092| mftlb1.
2093+----------------------------------------------------------------------------*/
2094 function_prolog(mftlb1)
Wolfgang Denk74357112007-02-27 14:26:04 +01002095 TLBRE(3,3,0)
Stefan Roese4745aca2007-02-20 10:57:08 +01002096 blr
2097 function_epilog(mftlb1)
2098#endif /* CONFIG_440 */
Stefan Roese64852d02008-06-02 14:35:44 +02002099
2100#if defined(CONFIG_NAND_SPL)
2101/*
2102 * void nand_boot_relocate(dst, src, bytes)
2103 *
2104 * r3 = Destination address to copy code to (in SDRAM)
2105 * r4 = Source address to copy code from
2106 * r5 = size to copy in bytes
2107 */
2108nand_boot_relocate:
2109 mr r6,r3
2110 mr r7,r4
2111 mflr r8
2112
2113 /*
2114 * Copy SPL from icache into SDRAM
2115 */
2116 subi r3,r3,4
2117 subi r4,r4,4
2118 srwi r5,r5,2
2119 mtctr r5
2120..spl_loop:
2121 lwzu r0,4(r4)
2122 stwu r0,4(r3)
2123 bdnz ..spl_loop
2124
2125 /*
2126 * Calculate "corrected" link register, so that we "continue"
2127 * in execution in destination range
2128 */
2129 sub r3,r7,r6 /* r3 = src - dst */
2130 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2131 mtlr r8
2132 blr
2133
2134nand_boot_common:
2135 /*
2136 * First initialize SDRAM. It has to be available *before* calling
2137 * nand_boot().
2138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02002139 lis r3,CONFIG_SYS_SDRAM_BASE@h
2140 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
Stefan Roese64852d02008-06-02 14:35:44 +02002141 bl initdram
2142
2143 /*
2144 * Now copy the 4k SPL code into SDRAM and continue execution
2145 * from there.
2146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02002147 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2148 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2149 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2150 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2151 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2152 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
Stefan Roese64852d02008-06-02 14:35:44 +02002153 bl nand_boot_relocate
2154
2155 /*
2156 * We're running from SDRAM now!!!
2157 *
2158 * It is necessary for 4xx systems to relocate from running at
2159 * the original location (0xfffffxxx) to somewhere else (SDRAM
2160 * preferably). This is because CS0 needs to be reconfigured for
2161 * NAND access. And we can't reconfigure this CS when currently
2162 * "running" from it.
2163 */
2164
2165 /*
2166 * Finally call nand_boot() to load main NAND U-Boot image from
2167 * NAND and jump to it.
2168 */
2169 bl nand_boot /* will not return */
2170#endif /* CONFIG_NAND_SPL */