blob: 6a4f0cb9bc06ec4ed41e6ca6be404c8b05fa8e8a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk5b845b62002-08-21 21:57:24 +00002/*
wdenk5da627a2003-10-09 20:09:04 +00003 * (C) Copyright 2003
4 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
5 *
wdenk5b845b62002-08-21 21:57:24 +00006 * (C) Copyright 2002
7 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk5b845b62002-08-21 21:57:24 +00008 */
9
Alexander Dahl6c62e8f2022-10-07 14:19:58 +020010#define LOG_CATEGORY UCLASS_FPGA
11
wdenk5b845b62002-08-21 21:57:24 +000012/*
wdenk5b845b62002-08-21 21:57:24 +000013 * Altera FPGA support
14 */
15#include <common.h>
Marek Vasutfda915a2014-09-16 20:33:54 +020016#include <errno.h>
wdenk5da627a2003-10-09 20:09:04 +000017#include <ACEX1K.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060018#include <log.h>
eran liberty3c735e72008-03-27 00:50:49 +010019#include <stratixII.h>
wdenk5b845b62002-08-21 21:57:24 +000020
Marek Vasut2012f232014-09-16 21:17:51 +020021static const struct altera_fpga {
22 enum altera_family family;
23 const char *name;
24 int (*load)(Altera_desc *, const void *, size_t);
25 int (*dump)(Altera_desc *, const void *, size_t);
26 int (*info)(Altera_desc *);
27} altera_fpga[] = {
28#if defined(CONFIG_FPGA_ACEX1K)
29 { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
30 { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
31#elif defined(CONFIG_FPGA_CYCLON2)
32 { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
33 { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
34#endif
35#if defined(CONFIG_FPGA_STRATIX_II)
36 { Altera_StratixII, "StratixII", StratixII_load,
37 StratixII_dump, StratixII_info },
38#endif
Stefan Roeseff9c4c52016-02-12 13:48:02 +010039#if defined(CONFIG_FPGA_STRATIX_V)
40 { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
41#endif
Pavel Machek230fe9b2014-09-08 14:08:45 +020042#if defined(CONFIG_FPGA_SOCFPGA)
43 { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
44#endif
Chee Hong Angd2170162020-08-07 11:50:03 +080045#if defined(CONFIG_FPGA_INTEL_SDM_MAILBOX)
46 { Intel_FPGA_SDM_Mailbox, "Intel SDM Mailbox", intel_sdm_mb_load, NULL,
47 NULL },
48#endif
Marek Vasut2012f232014-09-16 21:17:51 +020049};
50
Marek Vasut54c96b12014-09-16 20:32:51 +020051static int altera_validate(Altera_desc *desc, const char *fn)
52{
53 if (!desc) {
54 printf("%s: NULL descriptor!\n", fn);
Marek Vasutfda915a2014-09-16 20:33:54 +020055 return -EINVAL;
Marek Vasut54c96b12014-09-16 20:32:51 +020056 }
57
58 if ((desc->family < min_altera_type) ||
59 (desc->family > max_altera_type)) {
60 printf("%s: Invalid family type, %d\n", fn, desc->family);
Marek Vasutfda915a2014-09-16 20:33:54 +020061 return -EINVAL;
Marek Vasut54c96b12014-09-16 20:32:51 +020062 }
63
64 if ((desc->iface < min_altera_iface_type) ||
65 (desc->iface > max_altera_iface_type)) {
66 printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
Marek Vasutfda915a2014-09-16 20:33:54 +020067 return -EINVAL;
Marek Vasut54c96b12014-09-16 20:32:51 +020068 }
69
70 if (!desc->size) {
71 printf("%s: NULL part size\n", fn);
Marek Vasutfda915a2014-09-16 20:33:54 +020072 return -EINVAL;
Marek Vasut54c96b12014-09-16 20:32:51 +020073 }
74
Marek Vasutfda915a2014-09-16 20:33:54 +020075 return 0;
Marek Vasut54c96b12014-09-16 20:32:51 +020076}
wdenk5da627a2003-10-09 20:09:04 +000077
Marek Vasut2012f232014-09-16 21:17:51 +020078static const struct altera_fpga *
79altera_desc_to_fpga(Altera_desc *desc, const char *fn)
80{
81 int i;
82
83 if (altera_validate(desc, fn)) {
84 printf("%s: Invalid device descriptor\n", fn);
85 return NULL;
86 }
87
88 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
89 if (desc->family == altera_fpga[i].family)
90 break;
91 }
92
93 if (i == ARRAY_SIZE(altera_fpga)) {
94 printf("%s: Unsupported family type, %d\n", fn, desc->family);
95 return NULL;
96 }
97
98 return &altera_fpga[i];
99}
100
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000101int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
wdenk5b845b62002-08-21 21:57:24 +0000102{
Marek Vasut2012f232014-09-16 21:17:51 +0200103 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk5da627a2003-10-09 20:09:04 +0000104
Marek Vasut2012f232014-09-16 21:17:51 +0200105 if (!fpga)
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200106 return FPGA_FAIL;
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200107
Alexander Dahl6c62e8f2022-10-07 14:19:58 +0200108 log_debug("Launching the %s Loader...\n", fpga->name);
Marek Vasut2012f232014-09-16 21:17:51 +0200109 if (fpga->load)
110 return fpga->load(desc, buf, bsize);
111 return 0;
wdenk5b845b62002-08-21 21:57:24 +0000112}
113
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000114int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
wdenk5b845b62002-08-21 21:57:24 +0000115{
Marek Vasut2012f232014-09-16 21:17:51 +0200116 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk5da627a2003-10-09 20:09:04 +0000117
Marek Vasut2012f232014-09-16 21:17:51 +0200118 if (!fpga)
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200119 return FPGA_FAIL;
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200120
Alexander Dahl6c62e8f2022-10-07 14:19:58 +0200121 log_debug("Launching the %s Reader...\n", fpga->name);
Marek Vasut2012f232014-09-16 21:17:51 +0200122 if (fpga->dump)
123 return fpga->dump(desc, buf, bsize);
124 return 0;
wdenk5b845b62002-08-21 21:57:24 +0000125}
126
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200127int altera_info(Altera_desc *desc)
wdenk5b845b62002-08-21 21:57:24 +0000128{
Marek Vasut2012f232014-09-16 21:17:51 +0200129 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk5da627a2003-10-09 20:09:04 +0000130
Marek Vasut2012f232014-09-16 21:17:51 +0200131 if (!fpga)
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200132 return FPGA_FAIL;
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200133
Marek Vasut2012f232014-09-16 21:17:51 +0200134 printf("Family: \t%s\n", fpga->name);
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200135
136 printf("Interface type:\t");
137 switch (desc->iface) {
138 case passive_serial:
139 printf("Passive Serial (PS)\n");
140 break;
141 case passive_parallel_synchronous:
142 printf("Passive Parallel Synchronous (PPS)\n");
143 break;
144 case passive_parallel_asynchronous:
145 printf("Passive Parallel Asynchronous (PPA)\n");
146 break;
147 case passive_serial_asynchronous:
148 printf("Passive Serial Asynchronous (PSA)\n");
149 break;
150 case altera_jtag_mode: /* Not used */
151 printf("JTAG Mode\n");
152 break;
153 case fast_passive_parallel:
154 printf("Fast Passive Parallel (FPP)\n");
155 break;
156 case fast_passive_parallel_security:
157 printf("Fast Passive Parallel with Security (FPPS)\n");
158 break;
Ang, Chee Hong877ec6e2018-12-19 18:35:15 -0800159 case secure_device_manager_mailbox:
160 puts("Secure Device Manager (SDM) Mailbox\n");
161 break;
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200162 /* Add new interface types here */
163 default:
164 printf("Unsupported interface type, %d\n", desc->iface);
165 }
166
167 printf("Device Size: \t%zd bytes\n"
168 "Cookie: \t0x%x (%d)\n",
169 desc->size, desc->cookie, desc->cookie);
170
171 if (desc->iface_fns) {
172 printf("Device Function Table @ 0x%p\n", desc->iface_fns);
Marek Vasut2012f232014-09-16 21:17:51 +0200173 if (fpga->info)
174 fpga->info(desc);
wdenk5da627a2003-10-09 20:09:04 +0000175 } else {
Marek Vasut4a4c0a52014-09-16 20:29:24 +0200176 printf("No Device Function Table.\n");
wdenk5da627a2003-10-09 20:09:04 +0000177 }
178
Marek Vasut2012f232014-09-16 21:17:51 +0200179 return FPGA_SUCCESS;
wdenk5da627a2003-10-09 20:09:04 +0000180}