| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Arun Bharadwaj | fe5d488 | 2015-04-28 16:55:29 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Maintainer : Steve Sakoman <steve@sakoman.com> |
| 4 | * |
| 5 | * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by |
| 6 | * Richard Woodruff <r-woodruff2@ti.com> |
| 7 | * Syed Mohammed Khasim <khasim@ti.com> |
| 8 | * Sunil Kumar <sunilsaini05@gmail.com> |
| 9 | * Shashi Ranjan <shashiranjanmca05@gmail.com> |
| 10 | * |
| 11 | * (C) Copyright 2004-2008 |
| 12 | * Texas Instruments, <www.ti.com> |
| Arun Bharadwaj | fe5d488 | 2015-04-28 16:55:29 -0700 | [diff] [blame] | 13 | */ |
| Simon Glass | c3dc39a | 2020-05-10 11:39:55 -0600 | [diff] [blame] | 14 | |
| 15 | #include <common.h> |
| Arun Bharadwaj | fe5d488 | 2015-04-28 16:55:29 -0700 | [diff] [blame] | 16 | #include <asm/io.h> |
| 17 | #include <asm/arch/mem.h> |
| 18 | #include <asm/arch/sys_proto.h> |
| 19 | #include "overo.h" |
| 20 | |
| 21 | /* |
| 22 | * Routine: get_board_mem_timings |
| 23 | * Description: If we use SPL then there is no x-loader nor config header |
| 24 | * so we have to setup the DDR timings ourself on both banks. |
| 25 | */ |
| 26 | void get_board_mem_timings(struct board_sdrc_timings *timings) |
| 27 | { |
| 28 | timings->mr = MICRON_V_MR_165; |
| 29 | switch (get_board_revision()) { |
| 30 | case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ |
| 31 | timings->mcfg = MICRON_V_MCFG_165(256 << 20); |
| 32 | timings->ctrla = MICRON_V_ACTIMA_165; |
| 33 | timings->ctrlb = MICRON_V_ACTIMB_165; |
| 34 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
| 35 | break; |
| 36 | case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ |
| 37 | case REVISION_4: |
| 38 | timings->mcfg = MICRON_V_MCFG_200(256 << 20); |
| 39 | timings->ctrla = MICRON_V_ACTIMA_200; |
| 40 | timings->ctrlb = MICRON_V_ACTIMB_200; |
| 41 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
| 42 | break; |
| 43 | case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ |
| 44 | timings->mcfg = HYNIX_V_MCFG_200(256 << 20); |
| 45 | timings->ctrla = HYNIX_V_ACTIMA_200; |
| 46 | timings->ctrlb = HYNIX_V_ACTIMB_200; |
| 47 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
| 48 | break; |
| 49 | case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ |
| 50 | timings->mcfg = MCFG(512 << 20, 15); |
| 51 | timings->ctrla = MICRON_V_ACTIMA_200; |
| 52 | timings->ctrlb = MICRON_V_ACTIMB_200; |
| 53 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
| 54 | break; |
| 55 | default: |
| 56 | timings->mcfg = MICRON_V_MCFG_165(128 << 20); |
| 57 | timings->ctrla = MICRON_V_ACTIMA_165; |
| 58 | timings->ctrlb = MICRON_V_ACTIMB_165; |
| 59 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
| 60 | } |
| 61 | } |