arch/arm/dts/zynqmp-zcu102-revA.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP ZCU102 RevA
 *
 * (C) Copyright 2015 - 2020, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */

/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/ {
	model = "ZynqMP ZCU102 RevA";
	compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem3;
		gpio0 = &gpio;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		mmc0 = &sdhci1;
		rtc0 = &rtc;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &dcc;
		spi0 = &qspi;
		usb0 = &usb0;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
		xlnx,eeprom = &eeprom;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		sw19 {
			label = "sw19";
			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_DOWN>;
			wakeup-source;
			autorepeat;
		};
	};

	leds {
		compatible = "gpio-leds";
		heartbeat-led {
			label = "heartbeat";
			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	ina226-u76 {
		compatible = "iio-hwmon";
		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
	};
	ina226-u77 {
		compatible = "iio-hwmon";
		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
	};
	ina226-u78 {
		compatible = "iio-hwmon";
		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
	};
	ina226-u87 {
		compatible = "iio-hwmon";
		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
	};
	ina226-u85 {
		compatible = "iio-hwmon";
		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
	};
	ina226-u86 {
		compatible = "iio-hwmon";
		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
	};
	ina226-u93 {
		compatible = "iio-hwmon";
		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
	};
	ina226-u88 {
		compatible = "iio-hwmon";
		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
	};
	ina226-u15 {
		compatible = "iio-hwmon";
		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
	};
	ina226-u92 {
		compatible = "iio-hwmon";
		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
	};
	ina226-u79 {
		compatible = "iio-hwmon";
		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
	};
	ina226-u81 {
		compatible = "iio-hwmon";
		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
	};
	ina226-u80 {
		compatible = "iio-hwmon";
		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
	};
	ina226-u84 {
		compatible = "iio-hwmon";
		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
	};
	ina226-u16 {
		compatible = "iio-hwmon";
		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
	};
	ina226-u65 {
		compatible = "iio-hwmon";
		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
	};
	ina226-u74 {
		compatible = "iio-hwmon";
		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
	};
	ina226-u75 {
		compatible = "iio-hwmon";
		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
	};

	/* 48MHz reference crystal */
	ref48: ref48M {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <48000000>;
	};

	refhdmi: refhdmi {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <114285000>;
	};
};

&can1 {
	status = "okay";
};

&dcc {
	status = "okay";
};

&fpd_dma_chan1 {
	status = "okay";
};

&fpd_dma_chan2 {
	status = "okay";
};

&fpd_dma_chan3 {
	status = "okay";
};

&fpd_dma_chan4 {
	status = "okay";
};

&fpd_dma_chan5 {
	status = "okay";
};

&fpd_dma_chan6 {
	status = "okay";
};

&fpd_dma_chan7 {
	status = "okay";
};

&fpd_dma_chan8 {
	status = "okay";
};

&gem3 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	phy0: ethernet-phy@21 {
		reg = <21>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
		ti,dp83867-rxctrl-strap-quirk;
		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
	};
};

&gpio {
	status = "okay";
};

&gpu {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <400000>;

	tca6416_u97: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller; /* IRQ not connected */
		#gpio-cells = <2>;
		gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
				"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
				"", "", "", "", "", "", "", "", "";
		gtr-sel0-hog {
			gpio-hog;
			gpios = <0 0>;
			output-low; /* PCIE = 0, DP = 1 */
			line-name = "sel0";
		};
		gtr-sel1-hog {
			gpio-hog;
			gpios = <1 0>;
			output-high; /* PCIE = 0, DP = 1 */
			line-name = "sel1";
		};
		gtr-sel2-hog {
			gpio-hog;
			gpios = <2 0>;
			output-high; /* PCIE = 0, USB0 = 1 */
			line-name = "sel2";
		};
		gtr-sel3-hog {
			gpio-hog;
			gpios = <3 0>;
			output-high; /* PCIE = 0, SATA = 1 */
			line-name = "sel3";
		};
	};

	tca6416_u61: gpio@21 {
		compatible = "ti,tca6416";
		reg = <0x21>;
		gpio-controller; /* IRQ not connected */
		#gpio-cells = <2>;
		gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
				"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
				"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
				"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
	};

	i2c-mux@75 { /* u60 */
		compatible = "nxp,pca9544";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x75>;
		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* PS_PMBUS */
			u76: ina226@40 { /* u76 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u76";
				reg = <0x40>;
				shunt-resistor = <5000>;
			};
			u77: ina226@41 { /* u77 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u77";
				reg = <0x41>;
				shunt-resistor = <5000>;
			};
			u78: ina226@42 { /* u78 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u78";
				reg = <0x42>;
				shunt-resistor = <5000>;
			};
			u87: ina226@43 { /* u87 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u87";
				reg = <0x43>;
				shunt-resistor = <5000>;
			};
			u85: ina226@44 { /* u85 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u85";
				reg = <0x44>;
				shunt-resistor = <5000>;
			};
			u86: ina226@45 { /* u86 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u86";
				reg = <0x45>;
				shunt-resistor = <5000>;
			};
			u93: ina226@46 { /* u93 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u93";
				reg = <0x46>;
				shunt-resistor = <5000>;
			};
			u88: ina226@47 { /* u88 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u88";
				reg = <0x47>;
				shunt-resistor = <5000>;
			};
			u15: ina226@4a { /* u15 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u15";
				reg = <0x4a>;
				shunt-resistor = <5000>;
			};
			u92: ina226@4b { /* u92 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u92";
				reg = <0x4b>;
				shunt-resistor = <5000>;
			};
		};
		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* PL_PMBUS */
			u79: ina226@40 { /* u79 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u79";
				reg = <0x40>;
				shunt-resistor = <2000>;
			};
			u81: ina226@41 { /* u81 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u81";
				reg = <0x41>;
				shunt-resistor = <5000>;
			};
			u80: ina226@42 { /* u80 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u80";
				reg = <0x42>;
				shunt-resistor = <5000>;
			};
			u84: ina226@43 { /* u84 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u84";
				reg = <0x43>;
				shunt-resistor = <5000>;
			};
			u16: ina226@44 { /* u16 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u16";
				reg = <0x44>;
				shunt-resistor = <5000>;
			};
			u65: ina226@45 { /* u65 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u65";
				reg = <0x45>;
				shunt-resistor = <5000>;
			};
			u74: ina226@46 { /* u74 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u74";
				reg = <0x46>;
				shunt-resistor = <5000>;
			};
			u75: ina226@47 { /* u75 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u75";
				reg = <0x47>;
				shunt-resistor = <5000>;
			};
		};
		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			/* MAXIM_PMBUS - 00 */
			max15301@a { /* u46 */
				compatible = "maxim,max15301";
				reg = <0xa>;
			};
			max15303@b { /* u4 */
				compatible = "maxim,max15303";
				reg = <0xb>;
			};
			max15303@10 { /* u13 */
				compatible = "maxim,max15303";
				reg = <0x10>;
			};
			max15301@13 { /* u47 */
				compatible = "maxim,max15301";
				reg = <0x13>;
			};
			max15303@14 { /* u7 */
				compatible = "maxim,max15303";
				reg = <0x14>;
			};
			max15303@15 { /* u6 */
				compatible = "maxim,max15303";
				reg = <0x15>;
			};
			max15303@16 { /* u10 */
				compatible = "maxim,max15303";
				reg = <0x16>;
			};
			max15303@17 { /* u9 */
				compatible = "maxim,max15303";
				reg = <0x17>;
			};
			max15301@18 { /* u63 */
				compatible = "maxim,max15301";
				reg = <0x18>;
			};
			max15303@1a { /* u49 */
				compatible = "maxim,max15303";
				reg = <0x1a>;
			};
			max15303@1d { /* u18 */
				compatible = "maxim,max15303";
				reg = <0x1d>;
			};
			max15303@20 { /* u8 */
				compatible = "maxim,max15303";
				status = "disabled"; /* unreachable */
				reg = <0x20>;
			};
			max20751@72 { /* u95 */
				compatible = "maxim,max20751";
				reg = <0x72>;
			};
			max20751@73 { /* u96 */
				compatible = "maxim,max20751";
				reg = <0x73>;
			};
		};
		/* Bus 3 is not connected */
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	/* PL i2c via PCA9306 - u45 */
	i2c-mux@74 { /* u34 */
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/*
			 * IIC_EEPROM 1kB memory which uses 256B blocks
			 * where every block has different address.
			 *    0 - 256B address 0x54
			 * 256B - 512B address 0x55
			 * 512B - 768B address 0x56
			 * 768B - 1024B address 0x57
			 */
			eeprom: eeprom@54 { /* u23 */
				compatible = "atmel,24c08";
				reg = <0x54>;
			};
		};
		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			si5341: clock-generator@36 { /* SI5341 - u69 */
				compatible = "silabs,si5341";
				reg = <0x36>;
				#clock-cells = <2>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&ref48>;
				clock-names = "xtal";
				clock-output-names = "si5341";

				si5341_0: out@0 {
					/* refclk0 for PS-GT, used for DP */
					reg = <0>;
					always-on;
				};
				si5341_2: out@2 {
					/* refclk2 for PS-GT, used for USB3 */
					reg = <2>;
					always-on;
				};
				si5341_3: out@3 {
					/* refclk3 for PS-GT, used for SATA */
					reg = <3>;
					always-on;
				};
				si5341_4: out@4 {
					/* refclk4 for PS-GT, used for PCIE slot */
					reg = <4>;
					always-on;
				};
				si5341_5: out@5 {
					/* refclk5 for PS-GT, used for PCIE */
					reg = <5>;
					always-on;
				};
				si5341_6: out@6 {
					/* refclk6 PL CLK125 */
					reg = <6>;
					always-on;
				};
				si5341_7: out@7 {
					/* refclk7 PL CLK74 */
					reg = <7>;
					always-on;
				};
				si5341_9: out@9 {
					/* refclk9 used for PS_REF_CLK 33.3 MHz */
					reg = <9>;
					always-on;
				};
			};
		};
		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			si570_1: clock-generator@5d { /* USER SI570 - u42 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>;
				temperature-stability = <50>;
				factory-fout = <300000000>;
				clock-frequency = <300000000>;
				clock-output-names = "si570_user";
			};
		};
		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>;
				temperature-stability = <50>; /* copy from zc702 */
				factory-fout = <156250000>;
				clock-frequency = <148500000>;
				clock-output-names = "si570_mgt";
			};
		};
		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			si5328: clock-generator@69 {/* SI5328 - u20 */
				compatible = "silabs,si5328";
				reg = <0x69>;
				/*
				 * Chip has interrupt present connected to PL
				 * interrupt-parent = <&>;
				 * interrupts = <>;
				 */
			};
		};
		/* 5 - 7 unconnected */
	};

	i2c-mux@75 {
		compatible = "nxp,pca9548"; /* u135 */
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x75>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* HPC0_IIC */
		};
		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* HPC1_IIC */
		};
		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			/* SYSMON */
		};
		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			/* DDR4 SODIMM */
		};
		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			/* SEP 3 */
		};
		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
			/* SEP 2 */
		};
		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
			/* SEP 1 */
		};
		i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;
			/* SEP 0 */
		};
	};
};

&pcie {
	status = "okay";
};

&psgtr {
	status = "okay";
	/* pcie, sata, usb3, dp */
	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
	clock-names = "ref0", "ref1", "ref2", "ref3";
};

&qspi {
	status = "okay";
	is-dual = <1>;
	flash@0 {
		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
		spi-max-frequency = <108000000>; /* Based on DC1 spec */
		partition@0 { /* for testing purpose */
			label = "qspi-fsbl-uboot";
			reg = <0x0 0x100000>;
		};
		partition@100000 { /* for testing purpose */
			label = "qspi-linux";
			reg = <0x100000 0x500000>;
		};
		partition@600000 { /* for testing purpose */
			label = "qspi-device-tree";
			reg = <0x600000 0x20000>;
		};
		partition@620000 { /* for testing purpose */
			label = "qspi-rootfs";
			reg = <0x620000 0x5E0000>;
		};
	};
};

&rtc {
	status = "okay";
};

&sata {
	status = "okay";
	/* SATA OOB timing settings */
	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	phy-names = "sata-phy";
	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};

/* SD1 with level shifter */
&sdhci1 {
	status = "okay";
	/*
	 * 1.0 revision has level shifter and this property should be
	 * removed for supporting UHS mode
	 */
	no-1-8-v;
	xlnx,mio-bank = <1>;
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

/* ULPI SMSC USB3320 */
&usb0 {
	status = "okay";
};

&dwc3_0 {
	status = "okay";
	dr_mode = "host";
	snps,usb3_lpm_capable;
	maximum-speed = "super-speed";
};

&watchdog0 {
	status = "okay";
};

&xilinx_ams {
	status = "okay";
};

&ams_ps {
	status = "okay";
};

&ams_pl {
	status = "okay";
};

&zynqmp_dpdma {
	status = "okay";
};

&zynqmp_dpsub {
	status = "okay";
	phy-names = "dp-phy0";
	phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
};