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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * FPGA support
27 */
28#include <common.h>
29#include <command.h>
Jon Loeligerbaa26db2007-07-08 17:51:39 -050030#if defined(CONFIG_CMD_NET)
wdenk4a9cbbe2002-08-27 09:48:53 +000031#include <net.h>
32#endif
wdenk8bde7f72003-06-27 21:31:46 +000033#include <fpga.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000034#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000035
36#if 0
37#define FPGA_DEBUG
38#endif
39
40#ifdef FPGA_DEBUG
41#define PRINTF(fmt,args...) printf (fmt ,##args)
42#else
43#define PRINTF(fmt,args...)
44#endif
45
wdenk4a9cbbe2002-08-27 09:48:53 +000046/* Local functions */
wdenkd4ca31c2004-01-02 14:00:00 +000047static int fpga_get_op (char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000048
49/* Local defines */
50#define FPGA_NONE -1
51#define FPGA_INFO 0
52#define FPGA_LOAD 1
wdenk30ce5ab2005-01-09 18:12:51 +000053#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000054#define FPGA_DUMP 3
Stefan Roesef0ff4692006-08-15 14:15:51 +020055#define FPGA_LOADMK 4
wdenk4a9cbbe2002-08-27 09:48:53 +000056
wdenk30ce5ab2005-01-09 18:12:51 +000057/* Convert bitstream data and load into the fpga */
58int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
59{
Matthias Fuchs01335022007-12-27 17:12:34 +010060#if defined(CONFIG_FPGA_XILINX)
Wolfgang Denk8b019da2005-08-08 00:14:41 +020061 unsigned int length;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020062 unsigned int swapsize;
wdenk30ce5ab2005-01-09 18:12:51 +000063 char buffer[80];
Wolfgang Denk8b019da2005-08-08 00:14:41 +020064 unsigned char *dataptr;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020065 unsigned int i;
wdenk30ce5ab2005-01-09 18:12:51 +000066 int rc;
67
Wolfgang Denk77ddac92005-10-13 16:45:02 +020068 dataptr = (unsigned char *)fpgadata;
wdenk30ce5ab2005-01-09 18:12:51 +000069
Wolfgang Denk8b019da2005-08-08 00:14:41 +020070 /* skip the first bytes of the bitsteam, their meaning is unknown */
71 length = (*dataptr << 8) + *(dataptr+1);
72 dataptr+=2;
73 dataptr+=length;
wdenk30ce5ab2005-01-09 18:12:51 +000074
75 /* get design name (identifier, length, string) */
Wolfgang Denk8b019da2005-08-08 00:14:41 +020076 length = (*dataptr << 8) + *(dataptr+1);
77 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +000078 if (*dataptr++ != 0x61) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020079 PRINTF ("%s: Design name identifier not recognized in bitstream\n",
80 __FUNCTION__ );
wdenk30ce5ab2005-01-09 18:12:51 +000081 return FPGA_FAIL;
82 }
83
wdenka562e1b2005-01-09 18:21:42 +000084 length = (*dataptr << 8) + *(dataptr+1);
wdenk30ce5ab2005-01-09 18:12:51 +000085 dataptr+=2;
86 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +020087 buffer[i] = *dataptr++;
wdenka562e1b2005-01-09 18:21:42 +000088
Wolfgang Denk8b019da2005-08-08 00:14:41 +020089 printf(" design filename = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +000090
91 /* get part number (identifier, length, string) */
92 if (*dataptr++ != 0x62) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020093 printf("%s: Part number identifier not recognized in bitstream\n",
94 __FUNCTION__ );
wdenk30ce5ab2005-01-09 18:12:51 +000095 return FPGA_FAIL;
96 }
wdenka562e1b2005-01-09 18:21:42 +000097
Wolfgang Denk8b019da2005-08-08 00:14:41 +020098 length = (*dataptr << 8) + *(dataptr+1);
99 dataptr+=2;
wdenka562e1b2005-01-09 18:21:42 +0000100 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200101 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200102 printf(" part number = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000103
wdenk30ce5ab2005-01-09 18:12:51 +0000104 /* get date (identifier, length, string) */
105 if (*dataptr++ != 0x63) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200106 printf("%s: Date identifier not recognized in bitstream\n",
107 __FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000108 return FPGA_FAIL;
109 }
wdenka562e1b2005-01-09 18:21:42 +0000110
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200111 length = (*dataptr << 8) + *(dataptr+1);
112 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000113 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200114 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200115 printf(" date = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +0000116
117 /* get time (identifier, length, string) */
118 if (*dataptr++ != 0x64) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200119 printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000120 return FPGA_FAIL;
121 }
wdenka562e1b2005-01-09 18:21:42 +0000122
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200123 length = (*dataptr << 8) + *(dataptr+1);
124 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000125 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200126 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200127 printf(" time = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000128
wdenk30ce5ab2005-01-09 18:12:51 +0000129 /* get fpga data length (identifier, length) */
130 if (*dataptr++ != 0x65) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200131 printf("%s: Data length identifier not recognized in bitstream\n",
132 __FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000133 return FPGA_FAIL;
134 }
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200135 swapsize = ((unsigned int) *dataptr <<24) +
136 ((unsigned int) *(dataptr+1) <<16) +
137 ((unsigned int) *(dataptr+2) <<8 ) +
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200138 ((unsigned int) *(dataptr+3) ) ;
wdenk30ce5ab2005-01-09 18:12:51 +0000139 dataptr+=4;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200140 printf(" bytes in bitstream = %d\n", swapsize);
wdenka562e1b2005-01-09 18:21:42 +0000141
Matthias Fuchsc26acc12007-12-27 17:13:11 +0100142 rc = fpga_load(dev, dataptr, swapsize);
wdenk30ce5ab2005-01-09 18:12:51 +0000143 return rc;
144#else
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200145 printf("Bitstream support only for Xilinx devices\n");
wdenk30ce5ab2005-01-09 18:12:51 +0000146 return FPGA_FAIL;
147#endif
148}
149
wdenk4a9cbbe2002-08-27 09:48:53 +0000150/* ------------------------------------------------------------------------- */
151/* command form:
152 * fpga <op> <device number> <data addr> <datasize>
153 * where op is 'load', 'dump', or 'info'
154 * If there is no device number field, the fpga environment variable is used.
155 * If there is no data addr field, the fpgadata environment variable is used.
156 * The info command requires no data address field.
157 */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200158int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000159{
wdenkd4ca31c2004-01-02 14:00:00 +0000160 int op, dev = FPGA_INVALID_DEVICE;
161 size_t data_size = 0;
162 void *fpga_data = NULL;
163 char *devstr = getenv ("fpga");
164 char *datastr = getenv ("fpgadata");
165 int rc = FPGA_FAIL;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100166#if defined (CONFIG_FIT)
167 const char *fit_uname = NULL;
168 ulong fit_addr;
169#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000170
wdenkd4ca31c2004-01-02 14:00:00 +0000171 if (devstr)
172 dev = (int) simple_strtoul (devstr, NULL, 16);
173 if (datastr)
174 fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000175
wdenkd4ca31c2004-01-02 14:00:00 +0000176 switch (argc) {
177 case 5: /* fpga <op> <dev> <data> <datasize> */
178 data_size = simple_strtoul (argv[4], NULL, 16);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100179
wdenkd4ca31c2004-01-02 14:00:00 +0000180 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100181#if defined(CONFIG_FIT)
182 if (fit_parse_subimage (argv[3], (ulong)fpga_data,
183 &fit_addr, &fit_uname)) {
184 fpga_data = (void *)fit_addr;
185 debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
186 fit_uname, fit_addr);
187 } else
188#endif
189 {
190 fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
191 debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
192 }
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200193 PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100194
wdenkd4ca31c2004-01-02 14:00:00 +0000195 case 3: /* fpga <op> <dev | data addr> */
196 dev = (int) simple_strtoul (argv[2], NULL, 16);
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200197 PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000198 /* FIXME - this is a really weak test */
199 if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200200 PRINTF ("%s: Assuming buffer pointer in arg 3\n",
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200201 __FUNCTION__);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100202
203#if defined(CONFIG_FIT)
204 if (fit_parse_subimage (argv[2], (ulong)fpga_data,
205 &fit_addr, &fit_uname)) {
206 fpga_data = (void *)fit_addr;
207 debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
208 fit_uname, fit_addr);
209 } else
210#endif
211 {
212 fpga_data = (void *) dev;
213 debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
214 }
215
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200216 PRINTF ("%s: fpga_data = 0x%x\n",
217 __FUNCTION__, (uint) fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000218 dev = FPGA_INVALID_DEVICE; /* reset device num */
219 }
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100220
wdenkd4ca31c2004-01-02 14:00:00 +0000221 case 2: /* fpga <op> */
222 op = (int) fpga_get_op (argv[1]);
223 break;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100224
wdenkd4ca31c2004-01-02 14:00:00 +0000225 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200226 PRINTF ("%s: Too many or too few args (%d)\n",
227 __FUNCTION__, argc);
wdenkd4ca31c2004-01-02 14:00:00 +0000228 op = FPGA_NONE; /* force usage display */
229 break;
230 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000231
wdenkd4ca31c2004-01-02 14:00:00 +0000232 switch (op) {
233 case FPGA_NONE:
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200234 return cmd_usage(cmdtp);
wdenk4a9cbbe2002-08-27 09:48:53 +0000235
wdenkd4ca31c2004-01-02 14:00:00 +0000236 case FPGA_INFO:
237 rc = fpga_info (dev);
238 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000239
wdenkd4ca31c2004-01-02 14:00:00 +0000240 case FPGA_LOAD:
241 rc = fpga_load (dev, fpga_data, data_size);
242 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000243
wdenk30ce5ab2005-01-09 18:12:51 +0000244 case FPGA_LOADB:
245 rc = fpga_loadbitstream(dev, fpga_data, data_size);
246 break;
247
Stefan Roesef0ff4692006-08-15 14:15:51 +0200248 case FPGA_LOADMK:
Marian Balakowicz9a4daad2008-02-29 14:58:34 +0100249 switch (genimg_get_format (fpga_data)) {
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100250 case IMAGE_FORMAT_LEGACY:
251 {
252 image_header_t *hdr = (image_header_t *)fpga_data;
253 ulong data;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200254
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100255 data = (ulong)image_get_data (hdr);
256 data_size = image_get_data_size (hdr);
257 rc = fpga_load (dev, (void *)data, data_size);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200258 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100259 break;
260#if defined(CONFIG_FIT)
261 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100262 {
263 const void *fit_hdr = (const void *)fpga_data;
264 int noffset;
265 void *fit_data;
266
267 if (fit_uname == NULL) {
268 puts ("No FIT subimage unit name\n");
269 return 1;
270 }
271
272 if (!fit_check_format (fit_hdr)) {
273 puts ("Bad FIT image format\n");
274 return 1;
275 }
276
277 /* get fpga component image node offset */
278 noffset = fit_image_get_node (fit_hdr, fit_uname);
279 if (noffset < 0) {
280 printf ("Can't find '%s' FIT subimage\n", fit_uname);
281 return 1;
282 }
283
284 /* verify integrity */
285 if (!fit_image_check_hashes (fit_hdr, noffset)) {
286 puts ("Bad Data Hash\n");
287 return 1;
288 }
289
290 /* get fpga subimage data address and length */
291 if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
292 puts ("Could not find fpga subimage data\n");
293 return 1;
294 }
295
296 rc = fpga_load (dev, fit_data, data_size);
297 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100298 break;
299#endif
300 default:
301 puts ("** Unknown image type\n");
302 rc = FPGA_FAIL;
303 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200304 }
305 break;
306
wdenkd4ca31c2004-01-02 14:00:00 +0000307 case FPGA_DUMP:
308 rc = fpga_dump (dev, fpga_data, data_size);
309 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000310
wdenkd4ca31c2004-01-02 14:00:00 +0000311 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200312 printf ("Unknown operation\n");
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200313 return cmd_usage(cmdtp);
wdenkd4ca31c2004-01-02 14:00:00 +0000314 }
315 return (rc);
wdenk4a9cbbe2002-08-27 09:48:53 +0000316}
317
wdenk4a9cbbe2002-08-27 09:48:53 +0000318/*
319 * Map op to supported operations. We don't use a table since we
320 * would just have to relocate it from flash anyway.
321 */
wdenkd4ca31c2004-01-02 14:00:00 +0000322static int fpga_get_op (char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000323{
324 int op = FPGA_NONE;
325
326 if (!strcmp ("info", opstr)) {
327 op = FPGA_INFO;
wdenk30ce5ab2005-01-09 18:12:51 +0000328 } else if (!strcmp ("loadb", opstr)) {
329 op = FPGA_LOADB;
wdenkd4ca31c2004-01-02 14:00:00 +0000330 } else if (!strcmp ("load", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000331 op = FPGA_LOAD;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200332 } else if (!strcmp ("loadmk", opstr)) {
333 op = FPGA_LOADMK;
wdenkd4ca31c2004-01-02 14:00:00 +0000334 } else if (!strcmp ("dump", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000335 op = FPGA_DUMP;
336 }
337
wdenkd4ca31c2004-01-02 14:00:00 +0000338 if (op == FPGA_NONE) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000339 printf ("Unknown fpga operation \"%s\"\n", opstr);
340 }
341 return op;
342}
343
wdenkd4ca31c2004-01-02 14:00:00 +0000344U_BOOT_CMD (fpga, 6, 1, do_fpga,
Peter Tyser2fb26042009-01-27 18:03:12 -0600345 "loadable FPGA image support",
wdenkd4ca31c2004-01-02 14:00:00 +0000346 "fpga [operation type] [device number] [image address] [image size]\n"
347 "fpga operations:\n"
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200348 "\tinfo\tlist known device information\n"
349 "\tload\tLoad device from memory buffer\n"
350 "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
Stefan Roesef0ff4692006-08-15 14:15:51 +0200351 "\tloadmk\tLoad device generated with mkimage\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200352 "\tdump\tLoad device to memory buffer"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100353#if defined(CONFIG_FIT)
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200354 "\n"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100355 "\tFor loadmk operating on FIT format uImage address must include\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200356 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100357#endif
358);