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wdenkacea76a2002-09-20 09:17:33 +00001/*
2 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
3 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenkacea76a2002-09-20 09:17:33 +00005 */
6
7/************************************************************************
Wolfgang Denk0c8721a2005-09-23 11:05:55 +02008 * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
wdenkacea76a2002-09-20 09:17:33 +00009 ***********************************************************************/
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
17#define CONFIG_EBONY 1 /* Board is ebony */
Stefan Roese4a3cd9e2005-09-07 16:21:12 +020018#define CONFIG_440GP 1 /* Specifc GP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020019#define CONFIG_440 1 /* ... PPC440 family */
wdenkacea76a2002-09-20 09:17:33 +000020#define CONFIG_4xx 1 /* ... PPC4xx family */
wdenkc837dcb2004-01-20 23:12:12 +000021#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenkacea76a2002-09-20 09:17:33 +000022#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
25
Stefan Roese8a316c92005-08-01 16:49:12 +020026/*
Stefan Roese490f2042008-06-06 15:55:03 +020027 * Include common defines/options for all AMCC eval boards
28 */
29#define CONFIG_HOSTNAME ebony
30#include "amcc-common.h"
31
32/*
Stefan Roese8a316c92005-08-01 16:49:12 +020033 * Define here the location of the environment variables (FLASH or NVRAM).
34 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
35 * supported for backward compatibility.
36 */
37#if 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020038#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +020039#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020040#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +020041#endif
42
wdenkacea76a2002-09-20 09:17:33 +000043/*-----------------------------------------------------------------------
44 * Base addresses -- Note these are effective addresses where the
45 * actual resources get mapped (not physical addresses)
46 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
48#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
49#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
51#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
wdenkacea76a2002-09-20 09:17:33 +000052
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
54#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
wdenkacea76a2002-09-20 09:17:33 +000055
56/*-----------------------------------------------------------------------
57 * Initial RAM & stack pointer (placed in internal SRAM)
58 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +020060#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
wdenkacea76a2002-09-20 09:17:33 +000061
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020062#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkacea76a2002-09-20 09:17:33 +000064
wdenkacea76a2002-09-20 09:17:33 +000065/*-----------------------------------------------------------------------
66 * Serial Port
67 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020068#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
wdenkacea76a2002-09-20 09:17:33 +000070
71/*-----------------------------------------------------------------------
72 * NVRAM/RTC
73 *
74 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
75 * The DS1743 code assumes this condition (i.e. -- it assumes the base
76 * address for the RTC registers is:
77 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
wdenkacea76a2002-09-20 09:17:33 +000079 *
80 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
wdenkacea76a2002-09-20 09:17:33 +000082#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
83
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020084#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020085#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
86#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020088#endif /* CONFIG_ENV_IS_IN_NVRAM */
Stefan Roese8a316c92005-08-01 16:49:12 +020089
wdenkacea76a2002-09-20 09:17:33 +000090/*-----------------------------------------------------------------------
91 * FLASH related
92 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
94#define CONFIG_SYS_MAX_FLASH_SECT 32 /* sectors per device */
wdenkacea76a2002-09-20 09:17:33 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
97#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkacea76a2002-09-20 09:17:33 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese8a316c92005-08-01 16:49:12 +0200100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_ADDR0 0x5555
102#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
103#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese8a316c92005-08-01 16:49:12 +0200104
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200105#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200106#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200108#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200109
110/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200111#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
112#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200113#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese8a316c92005-08-01 16:49:12 +0200114
wdenkacea76a2002-09-20 09:17:33 +0000115/*-----------------------------------------------------------------------
116 * DDR SDRAM
117 *----------------------------------------------------------------------*/
Stefan Roese8423e5e2007-03-16 21:11:42 +0100118#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
119#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
120#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
wdenkacea76a2002-09-20 09:17:33 +0000121
122/*-----------------------------------------------------------------------
123 * I2C
124 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000125#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese4f92ed52006-08-07 14:33:32 +0200126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_I2C_MULTI_EEPROMS
128#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
129#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
130#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
131#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenkacea76a2002-09-20 09:17:33 +0000132
Stefan Roese490f2042008-06-06 15:55:03 +0200133/*
134 * Default environment variables
135 */
Stefan Roese8a316c92005-08-01 16:49:12 +0200136#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200137 CONFIG_AMCC_DEF_ENV \
138 CONFIG_AMCC_DEF_ENV_POWERPC \
139 CONFIG_AMCC_DEF_ENV_PPC_OLD \
140 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese8a316c92005-08-01 16:49:12 +0200141 "kernel_addr=ff800000\0" \
142 "ramdisk_addr=ff810000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200143 ""
wdenkacea76a2002-09-20 09:17:33 +0000144
wdenkacea76a2002-09-20 09:17:33 +0000145#define CONFIG_PHY_ADDR 8 /* PHY address */
Stefan Roesea00eccf2008-05-08 11:05:15 +0200146#define CONFIG_HAS_ETH0
Stefan Roese4a3cd9e2005-09-07 16:21:12 +0200147#define CONFIG_HAS_ETH1
148#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
wdenkacea76a2002-09-20 09:17:33 +0000149
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500150/*
Stefan Roese490f2042008-06-06 15:55:03 +0200151 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500152 */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500153#define CONFIG_CMD_DATE
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500154#define CONFIG_CMD_PCI
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500155#define CONFIG_CMD_SDRAM
156#define CONFIG_CMD_SNTP
157
wdenkacea76a2002-09-20 09:17:33 +0000158/*-----------------------------------------------------------------------
159 * PCI stuff
160 *-----------------------------------------------------------------------
161 */
162/* General PCI */
163#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000164#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkacea76a2002-09-20 09:17:33 +0000165#define CONFIG_PCI_PNP /* do pci plug-and-play */
166#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
wdenkacea76a2002-09-20 09:17:33 +0000168
169/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
wdenkacea76a2002-09-20 09:17:33 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
173#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
wdenkacea76a2002-09-20 09:17:33 +0000174
wdenkacea76a2002-09-20 09:17:33 +0000175#endif /* __CONFIG_H */