blob: 06151177735319d4ebca530174eab301698f4e1c [file] [log] [blame]
stefano babic5e5803e2007-08-30 23:01:49 +02001/*
2 * (C) Copyright 2007
3 * Stefano Babic, DENX Gmbh, sbabic@denx.de
4 *
5 * (C) Copyright 2004
6 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
7 *
8 * (C) Copyright 2002
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 *
11 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
14 *
15 * Configuation settings for the LUBBOCK board.
16 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020017 * SPDX-License-Identifier: GPL-2.0+
stefano babic5e5803e2007-08-30 23:01:49 +020018 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 * (easy to change)
26 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010027#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */
stefano babic5e5803e2007-08-30 23:01:49 +020028
stefano babic5e5803e2007-08-30 23:01:49 +020029#define CONFIG_MMC 1
Helmut Raiger9660e442011-10-20 04:19:47 +000030#define CONFIG_BOARD_LATE_INIT
Marek Vasutcc72ac62010-10-20 21:28:14 +020031#define CONFIG_SYS_TEXT_BASE 0x0
stefano babic5e5803e2007-08-30 23:01:49 +020032
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020033/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000034#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020035
stefano babic5e5803e2007-08-30 23:01:49 +020036#define RTC
37
38/*
39 * Size of malloc() pool
40 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
stefano babic5e5803e2007-08-30 23:01:49 +020042
43/*
44 * Hardware drivers
45 */
46
47/*
48 * select serial console configuration
49 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020050#define CONFIG_PXA_SERIAL
stefano babic5e5803e2007-08-30 23:01:49 +020051#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
52#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
53#define CONFIG_STUART 1 /* we use STUART on Conxs */
Marek Vasutce6971c2012-09-12 12:36:25 +020054#define CONFIG_CONS_INDEX 3
stefano babic5e5803e2007-08-30 23:01:49 +020055
56/* allow to overwrite serial and ethaddr */
57#define CONFIG_ENV_OVERWRITE
58
59#define CONFIG_BAUDRATE 38400
60
61#define CONFIG_DOS_PARTITION 1
62
63/*
64 * Command line configuration.
65 */
66#include <config_cmd_default.h>
67
stefano babic5e5803e2007-08-30 23:01:49 +020068#define CONFIG_CMD_FAT
69#define CONFIG_CMD_IMLS
70#define CONFIG_CMD_PING
71#define CONFIG_CMD_USB
72
73/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
74
75#undef CONFIG_SHOW_BOOT_PROGRESS
76
77#define CONFIG_BOOTDELAY 3
78#define CONFIG_SERVERIP 192.168.1.99
79#define CONFIG_BOOTCOMMAND "run boot_flash"
80#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
81 " rw root=/dev/ram initrd=0xa0800000,5m"
82
83#define CONFIG_EXTRA_ENV_SETTINGS \
84 "program_boot_mmc=" \
85 "mw.b 0xa0010000 0xff 0x20000; " \
86 "if mmcinit && " \
87 "fatload mmc 0 0xa0010000 u-boot.bin; " \
88 "then " \
89 "protect off 0x0 0x1ffff; " \
90 "erase 0x0 0x1ffff; " \
91 "cp.b 0xa0010000 0x0 0x20000; " \
92 "fi\0" \
93 "program_uzImage_mmc=" \
94 "mw.b 0xa0010000 0xff 0x180000; " \
95 "if mmcinit && " \
96 "fatload mmc 0 0xa0010000 uzImage; " \
97 "then " \
98 "protect off 0x40000 0x1bffff; " \
99 "erase 0x40000 0x1bffff; " \
100 "cp.b 0xa0010000 0x40000 0x180000; " \
101 "fi\0" \
102 "program_ramdisk_mmc=" \
103 "mw.b 0xa0010000 0xff 0x500000; " \
104 "if mmcinit && " \
105 "fatload mmc 0 0xa0010000 ramdisk.gz; " \
106 "then " \
107 "protect off 0x1c0000 0x6bffff; " \
108 "erase 0x1c0000 0x6bffff; " \
109 "cp.b 0xa0010000 0x1c0000 0x500000; " \
110 "fi\0" \
111 "boot_mmc=" \
112 "if mmcinit && " \
113 "fatload mmc 0 0xa0030000 uzImage && " \
114 "fatload mmc 0 0xa0800000 ramdisk.gz; " \
115 "then " \
116 "bootm 0xa0030000; " \
117 "fi\0" \
118 "boot_flash=" \
119 "cp.b 0x1c0000 0xa0800000 0x500000; " \
120 "bootm 0x40000\0" \
121
122#define CONFIG_SETUP_MEMORY_TAGS 1
123#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
124/* #define CONFIG_INITRD_TAG 1 */
125
Jean-Christophe PLAGNIOL-VILLARD1b769882008-01-25 07:54:47 +0100126#if defined(CONFIG_CMD_KGDB)
stefano babic5e5803e2007-08-30 23:01:49 +0200127#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
128#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
129#endif
130
131/*
132 * Miscellaneous configurable options
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_HUSH_PARSER 1
stefano babic5e5803e2007-08-30 23:01:49 +0200135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LONGHELP /* undef to save memory */
137#ifdef CONFIG_SYS_HUSH_PARSER
138#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
stefano babic5e5803e2007-08-30 23:01:49 +0200139#else
stefano babic5e5803e2007-08-30 23:01:49 +0200140#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
142#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
143#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
144#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
145#define CONFIG_SYS_DEVICE_NULLDEV 1
stefano babic5e5803e2007-08-30 23:01:49 +0200146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
148#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
stefano babic5e5803e2007-08-30 23:01:49 +0200149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
stefano babic5e5803e2007-08-30 23:01:49 +0200151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
stefano babic5e5803e2007-08-30 23:01:49 +0200153
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100154#ifdef CONFIG_MMC
Marek Vasut831f8492012-09-30 10:09:49 +0000155#define CONFIG_GENERIC_MMC
156#define CONFIG_PXA_MMC_GENERIC
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100157#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100159#endif
stefano babic5e5803e2007-08-30 23:01:49 +0200160
161/*
stefano babic5e5803e2007-08-30 23:01:49 +0200162 * Physical Memory Map
163 */
164#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
165#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
166#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
167#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
168#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
169#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
170#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
171#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
172#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
173
174#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_DRAM_BASE 0xa0000000
177#define CONFIG_SYS_DRAM_SIZE 0x04000000
stefano babic5e5803e2007-08-30 23:01:49 +0200178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
stefano babic5e5803e2007-08-30 23:01:49 +0200180
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200181#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200182#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200183
stefano babic5e5803e2007-08-30 23:01:49 +0200184/*
185 * GPIO settings
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_GPSR0_VAL 0x00018000
188#define CONFIG_SYS_GPSR1_VAL 0x00000000
189#define CONFIG_SYS_GPSR2_VAL 0x400dc000
190#define CONFIG_SYS_GPSR3_VAL 0x00000000
191#define CONFIG_SYS_GPCR0_VAL 0x00000000
192#define CONFIG_SYS_GPCR1_VAL 0x00000000
193#define CONFIG_SYS_GPCR2_VAL 0x00000000
194#define CONFIG_SYS_GPCR3_VAL 0x00000000
195#define CONFIG_SYS_GPDR0_VAL 0x00018000
196#define CONFIG_SYS_GPDR1_VAL 0x00028801
197#define CONFIG_SYS_GPDR2_VAL 0x520dc000
198#define CONFIG_SYS_GPDR3_VAL 0x0001E000
199#define CONFIG_SYS_GAFR0_L_VAL 0x801c0000
200#define CONFIG_SYS_GAFR0_U_VAL 0x00000013
201#define CONFIG_SYS_GAFR1_L_VAL 0x6990100A
202#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
203#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
204#define CONFIG_SYS_GAFR2_U_VAL 0x010900F2
205#define CONFIG_SYS_GAFR3_L_VAL 0x54000003
206#define CONFIG_SYS_GAFR3_U_VAL 0x00002401
207#define CONFIG_SYS_GRER0_VAL 0x00000000
208#define CONFIG_SYS_GRER1_VAL 0x00000000
209#define CONFIG_SYS_GRER2_VAL 0x00000000
210#define CONFIG_SYS_GRER3_VAL 0x00000000
Stefano Babic040f8f62009-07-01 20:40:41 +0200211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_GFER1_VAL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_GFER3_VAL 0x00000020
stefano babic5e5803e2007-08-30 23:01:49 +0200214
Stefano Babic040f8f62009-07-01 20:40:41 +0200215#if CONFIG_POLARIS
216#define CONFIG_SYS_GFER0_VAL 0x00000001
217#define CONFIG_SYS_GFER2_VAL 0x00200000
218#else
219#define CONFIG_SYS_GFER0_VAL 0x00000000
220#define CONFIG_SYS_GFER2_VAL 0x00000000
221#endif
stefano babic5e5803e2007-08-30 23:01:49 +0200222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
stefano babic5e5803e2007-08-30 23:01:49 +0200224
225/*
226 * Clock settings
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */
229#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
stefano babic5e5803e2007-08-30 23:01:49 +0200230
231/*
232 * Memory settings
233 */
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_MSC0_VAL 0x4df84df0
236#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
Stefano Babic040f8f62009-07-01 20:40:41 +0200237#if CONFIG_POLARIS
238#define CONFIG_SYS_MSC2_VAL 0xa2697ff8
239#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MSC2_VAL 0xa26936d4
Stefano Babic040f8f62009-07-01 20:40:41 +0200241#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_MDCNFG_VAL 0x880009C9
243#define CONFIG_SYS_MDREFR_VAL 0x20ca201e
244#define CONFIG_SYS_MDMRS_VAL 0x00220022
stefano babic5e5803e2007-08-30 23:01:49 +0200245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
247#define CONFIG_SYS_SXCNFG_VAL 0x40044004
stefano babic5e5803e2007-08-30 23:01:49 +0200248
249/*
250 * PCMCIA and CF Interfaces
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_MECR_VAL 0x00000001
253#define CONFIG_SYS_MCMEM0_VAL 0x00004204
254#define CONFIG_SYS_MCMEM1_VAL 0x00010204
255#define CONFIG_SYS_MCATT0_VAL 0x00010504
256#define CONFIG_SYS_MCATT1_VAL 0x00010504
257#define CONFIG_SYS_MCIO0_VAL 0x00008407
258#define CONFIG_SYS_MCIO1_VAL 0x0000c108
stefano babic5e5803e2007-08-30 23:01:49 +0200259
260#define CONFIG_DRIVER_DM9000 1
Stefano Babic040f8f62009-07-01 20:40:41 +0200261
262#if CONFIG_POLARIS
263#define CONFIG_DM9000_BASE 0x0C800000
264#else
265#define CONFIG_DM9000_BASE 0x08000000
266#endif
267
stefano babic5e5803e2007-08-30 23:01:49 +0200268#define DM9000_IO CONFIG_DM9000_BASE
269#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
stefano babic5e5803e2007-08-30 23:01:49 +0200270
271#define CONFIG_USB_OHCI_NEW 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
273#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
274#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
275#define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv"
stefano babic5e5803e2007-08-30 23:01:49 +0200276#define CONFIG_USB_STORAGE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
stefano babic5e5803e2007-08-30 23:01:49 +0200278
279/*
280 * FLASH and environment organization
281 */
282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200284#define CONFIG_FLASH_CFI_DRIVER 1
stefano babic5e5803e2007-08-30 23:01:49 +0200285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_MONITOR_BASE 0
287#define CONFIG_SYS_MONITOR_LEN 0x40000
stefano babic5e5803e2007-08-30 23:01:49 +0200288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
290#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
stefano babic5e5803e2007-08-30 23:01:49 +0200291
292/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
294#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
stefano babic5e5803e2007-08-30 23:01:49 +0200295
296/* write flash less slowly */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
stefano babic5e5803e2007-08-30 23:01:49 +0200298
Stefano Babic040f8f62009-07-01 20:40:41 +0200299/* Unlock to be used with Intel chips */
300#define CONFIG_SYS_FLASH_PROTECTION 1
301
stefano babic5e5803e2007-08-30 23:01:49 +0200302/* Flash environment locations */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200303#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200305#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */
306#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
stefano babic5e5803e2007-08-30 23:01:49 +0200307
308/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200309#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
310#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
stefano babic5e5803e2007-08-30 23:01:49 +0200311
312#endif /* __CONFIG_H */