blob: 2e9f1f917c5f74bd8eb5af3fc0871025942936ad [file] [log] [blame]
Gong Qianyu630532f2015-11-11 17:58:38 +08001/*
2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
3 *
4 * Copyright (C) 2015, Freescale Semiconductor
5 *
6 * Mingkai Hu <Mingkai.hu@freescale.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
Gong Qianyu630532f2015-11-11 17:58:38 +080013/include/ "fsl-ls1043a.dtsi"
14
15/ {
16 model = "LS1043A QDS Board";
Qianyu Gong73a5de42016-02-01 13:09:16 +080017 aliases {
18 spi0 = &qspi;
19 spi1 = &dspi0;
20 };
21};
22
23&dspi0 {
24 bus-num = <0>;
25 status = "okay";
26
27 dflash0: n25q128a {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "spi-flash";
Qianyu Gong73a5de42016-02-01 13:09:16 +080031 spi-max-frequency = <1000000>; /* input clock */
Qianyu Gong2ef846e2016-03-23 19:11:36 +080032 spi-cpol;
33 spi-cpha;
34 reg = <0>;
Qianyu Gong73a5de42016-02-01 13:09:16 +080035 };
36
37 dflash1: sst25wf040b {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "spi-flash";
41 spi-max-frequency = <3500000>;
Qianyu Gong2ef846e2016-03-23 19:11:36 +080042 spi-cpol;
43 spi-cpha;
Qianyu Gong73a5de42016-02-01 13:09:16 +080044 reg = <1>;
45 };
46
47 dflash2: en25s64 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "spi-flash";
51 spi-max-frequency = <3500000>;
Qianyu Gong2ef846e2016-03-23 19:11:36 +080052 spi-cpol;
53 spi-cpha;
Qianyu Gong73a5de42016-02-01 13:09:16 +080054 reg = <2>;
55 };
56};
57
58&qspi {
59 bus-num = <0>;
60 status = "okay";
61
62 qflash0: s25fl128s@0 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "spi-flash";
66 spi-max-frequency = <20000000>;
67 reg = <0>;
68 };
Gong Qianyu630532f2015-11-11 17:58:38 +080069};
70
71&i2c0 {
72 status = "okay";
73 pca9547@77 {
74 compatible = "philips,pca9547";
75 reg = <0x77>;
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 i2c@0 {
80 #address-cells = <1>;
81 #size-cells = <0>;
82 reg = <0x0>;
83
84 rtc@68 {
85 compatible = "dallas,ds3232";
86 reg = <0x68>;
87 /* IRQ10_B */
88 interrupts = <0 150 0x4>;
89 };
90 };
91
92 i2c@2 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 reg = <0x2>;
96
97 ina220@40 {
98 compatible = "ti,ina220";
99 reg = <0x40>;
100 shunt-resistor = <1000>;
101 };
102
103 ina220@41 {
104 compatible = "ti,ina220";
105 reg = <0x41>;
106 shunt-resistor = <1000>;
107 };
108 };
109
110 i2c@3 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 reg = <0x3>;
114
115 eeprom@56 {
116 compatible = "at24,24c512";
117 reg = <0x56>;
118 };
119
120 eeprom@57 {
121 compatible = "at24,24c512";
122 reg = <0x57>;
123 };
124
125 adt7461a@4c {
126 compatible = "adt7461a";
127 reg = <0x4c>;
128 };
129 };
130 };
131};
132
133&ifc {
134 #address-cells = <2>;
135 #size-cells = <1>;
136 /* NOR, NAND Flashes and FPGA on board */
137 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
138 0x2 0x0 0x0 0x7e800000 0x00010000
139 0x3 0x0 0x0 0x7fb00000 0x00000100>;
140 status = "okay";
141
142 nor@0,0 {
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "cfi-flash";
146 reg = <0x0 0x0 0x8000000>;
147 bank-width = <2>;
148 device-width = <1>;
149 };
150
151 nand@2,0 {
152 compatible = "fsl,ifc-nand";
153 #address-cells = <1>;
154 #size-cells = <1>;
155 reg = <0x1 0x0 0x10000>;
156 };
157
158 fpga: board-control@3,0 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "simple-bus";
162 reg = <0x3 0x0 0x0000100>;
163 bank-width = <1>;
164 device-width = <1>;
165 ranges = <0 3 0 0x100>;
166 };
167};
168
169&duart0 {
170 status = "okay";
171};
172
173&duart1 {
174 status = "okay";
175};
Wenbin Song2970e142016-01-21 17:14:55 +0800176
177&lpuart0 {
178 status = "okay";
179};