| Joseph Chen | 2a950e3 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * (C) Copyright 2021 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_RK3568_COMMON_H |
| 7 | #define __CONFIG_RK3568_COMMON_H |
| 8 | |
| 9 | #include "rockchip-common.h" |
| 10 | |
| Joseph Chen | 2a950e3 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 11 | #define CONFIG_IRAM_BASE 0xfdcc0000 |
| 12 | |
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 13 | #define CFG_SYS_SDRAM_BASE 0 |
| Joseph Chen | 2a950e3 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 14 | #define SDRAM_MAX_SIZE 0xf0000000 |
| 15 | |
| Joseph Chen | 2a950e3 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 16 | #define ENV_MEM_LAYOUT_SETTINGS \ |
| 17 | "scriptaddr=0x00c00000\0" \ |
| 18 | "pxefile_addr_r=0x00e00000\0" \ |
| 19 | "fdt_addr_r=0x0a100000\0" \ |
| 20 | "kernel_addr_r=0x02080000\0" \ |
| 21 | "ramdisk_addr_r=0x0a200000\0" |
| 22 | |
| 23 | #include <config_distro_bootcmd.h> |
| 24 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 25 | ENV_MEM_LAYOUT_SETTINGS \ |
| 26 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
| 27 | "partitions=" PARTS_DEFAULT \ |
| 28 | ROCKCHIP_DEVICE_SETTINGS \ |
| 29 | BOOTENV |
| Joseph Chen | 2a950e3 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 30 | |
| 31 | #endif |