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Michael Trimarchi6b924872008-11-28 13:22:09 +01001/*
Rajesh Bhagatba699a52016-07-01 18:51:46 +05302 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
Vivek Mahajan4ef01012009-05-25 17:23:16 +05303 *
Michael Trimarchi6b924872008-11-28 13:22:09 +01004 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
5 *
6 * Author: Tor Krill tor@excito.com
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Michael Trimarchi6b924872008-11-28 13:22:09 +01009 */
10
11#include <common.h>
12#include <pci.h>
13#include <usb.h>
Michael Trimarchi6b924872008-11-28 13:22:09 +010014#include <asm/io.h>
Mateusz Kulikowskie162c6b2016-03-31 23:12:23 +020015#include <usb/ehci-ci.h>
Ramneek Mehresh1b719e62011-03-23 15:20:43 +053016#include <hwconfig.h>
Nikhil Badolac26c80a2014-09-30 11:22:43 +053017#include <fsl_usb.h>
Nikhil Badolaa1c04e22014-10-20 16:50:49 +053018#include <fdt_support.h>
Rajesh Bhagatba699a52016-07-01 18:51:46 +053019#include <dm.h>
Michael Trimarchi6b924872008-11-28 13:22:09 +010020
Jean-Christophe PLAGNIOL-VILLARD2731b9a2009-04-03 12:46:58 +020021#include "ehci.h"
Michael Trimarchi6b924872008-11-28 13:22:09 +010022
Rajesh Bhagatba699a52016-07-01 18:51:46 +053023DECLARE_GLOBAL_DATA_PTR;
24
Nikhil Badolaa1c04e22014-10-20 16:50:49 +053025#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
26#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
27#endif
28
Rajesh Bhagatba699a52016-07-01 18:51:46 +053029#ifdef CONFIG_DM_USB
30struct ehci_fsl_priv {
31 struct ehci_ctrl ehci;
32 fdt_addr_t hcd_base;
33 char *phy_type;
34};
35#endif
36
Nikhil Badola896720c2014-04-07 08:46:14 +053037static void set_txfifothresh(struct usb_ehci *, u32);
Rajesh Bhagatba699a52016-07-01 18:51:46 +053038#ifdef CONFIG_DM_USB
39static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
40 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
41#else
Rajesh Bhagat1e61ce92016-07-01 18:51:45 +053042static int ehci_fsl_init(int index, struct usb_ehci *ehci,
43 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
Rajesh Bhagatba699a52016-07-01 18:51:46 +053044#endif
Nikhil Badola896720c2014-04-07 08:46:14 +053045
Shengzhou Liu047cea32012-10-22 13:18:24 +080046/* Check USB PHY clock valid */
47static int usb_phy_clk_valid(struct usb_ehci *ehci)
48{
49 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
50 in_be32(&ehci->prictrl))) {
51 printf("USB PHY clock invalid!\n");
52 return 0;
53 } else {
54 return 1;
55 }
56}
57
Rajesh Bhagatba699a52016-07-01 18:51:46 +053058#ifdef CONFIG_DM_USB
59static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
60{
61 struct ehci_fsl_priv *priv = dev_get_priv(dev);
62 const void *prop;
63
Simon Glasse160f7d2017-01-17 16:52:55 -070064 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
Rajesh Bhagatba699a52016-07-01 18:51:46 +053065 NULL);
66 if (prop) {
67 priv->phy_type = (char *)prop;
68 debug("phy_type %s\n", priv->phy_type);
69 }
70
71 return 0;
72}
73
74static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
75{
76 struct usb_ehci *ehci = NULL;
77 struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
78 ehci);
79
80 ehci = (struct usb_ehci *)priv->hcd_base;
81 if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
82 return -ENXIO;
83
84 return 0;
85}
86
87static const struct ehci_ops fsl_ehci_ops = {
88 .init_after_reset = ehci_fsl_init_after_reset,
89};
90
91static int ehci_fsl_probe(struct udevice *dev)
92{
93 struct ehci_fsl_priv *priv = dev_get_priv(dev);
94 struct usb_ehci *ehci = NULL;
95 struct ehci_hccr *hccr;
96 struct ehci_hcor *hcor;
97
98 /*
99 * Get the base address for EHCI controller from the device node
100 */
Simon Glassa821c4a2017-05-17 17:18:05 -0600101 priv->hcd_base = devfdt_get_addr(dev);
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530102 if (priv->hcd_base == FDT_ADDR_T_NONE) {
103 debug("Can't get the EHCI register base address\n");
104 return -ENXIO;
105 }
106 ehci = (struct usb_ehci *)priv->hcd_base;
107 hccr = (struct ehci_hccr *)(&ehci->caplength);
108 hcor = (struct ehci_hcor *)
109 ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
110
111 if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
112 return -ENXIO;
113
114 debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
115 (u32)hccr, (u32)hcor,
116 (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
117
118 return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
119}
120
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530121static const struct udevice_id ehci_usb_ids[] = {
122 { .compatible = "fsl-usb2-mph", },
123 { .compatible = "fsl-usb2-dr", },
124 { }
125};
126
127U_BOOT_DRIVER(ehci_fsl) = {
128 .name = "ehci_fsl",
129 .id = UCLASS_USB,
130 .of_match = ehci_usb_ids,
131 .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
132 .probe = ehci_fsl_probe,
Masahiro Yamada40527342016-09-06 22:17:34 +0900133 .remove = ehci_deregister,
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530134 .ops = &ehci_usb_ops,
135 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
136 .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
137 .flags = DM_FLAG_ALLOC_PRIV_DMA,
138};
139#else
Michael Trimarchi6b924872008-11-28 13:22:09 +0100140/*
141 * Create the appropriate control structures to manage
142 * a new EHCI host controller.
143 *
144 * Excerpts from linux ehci fsl driver.
145 */
Troy Kisky127efc42013-10-10 15:27:57 -0700146int ehci_hcd_init(int index, enum usb_init_type init,
147 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Michael Trimarchi6b924872008-11-28 13:22:09 +0100148{
ramneek mehresh77354e92013-09-12 16:35:49 +0530149 struct usb_ehci *ehci = NULL;
Rajesh Bhagat1e61ce92016-07-01 18:51:45 +0530150
151 switch (index) {
152 case 0:
153 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
154 break;
155 case 1:
156 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
157 break;
158 default:
159 printf("ERROR: wrong controller index!!\n");
160 return -EINVAL;
161 };
162
163 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
164 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
165 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
166
167 return ehci_fsl_init(index, ehci, *hccr, *hcor);
168}
169
170/*
171 * Destroy the appropriate control structures corresponding
172 * the the EHCI host controller.
173 */
174int ehci_hcd_stop(int index)
175{
176 return 0;
177}
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530178#endif
Rajesh Bhagat1e61ce92016-07-01 18:51:45 +0530179
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530180#ifdef CONFIG_DM_USB
181static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
182 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
183#else
Rajesh Bhagat1e61ce92016-07-01 18:51:45 +0530184static int ehci_fsl_init(int index, struct usb_ehci *ehci,
185 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530186#endif
Rajesh Bhagat1e61ce92016-07-01 18:51:45 +0530187{
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530188 const char *phy_type = NULL;
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530189#ifndef CONFIG_DM_USB
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530190 size_t len;
Nikhil Badola0ecb15c2013-12-19 11:08:46 +0530191 char current_usb_controller[5];
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530192#endif
Kumar Galadd22f7c2011-11-09 10:04:15 -0600193#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
194 char usb_phy[5];
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530195
196 usb_phy[0] = '\0';
Kumar Galadd22f7c2011-11-09 10:04:15 -0600197#endif
Nikhil Badola11856912014-02-26 17:43:15 +0530198 if (has_erratum_a007075()) {
199 /*
200 * A 5ms delay is needed after applying soft-reset to the
201 * controller to let external ULPI phy come out of reset.
202 * This delay needs to be added before re-initializing
203 * the controller after soft-resetting completes
204 */
205 mdelay(5);
206 }
Michael Trimarchi6b924872008-11-28 13:22:09 +0100207
Michael Trimarchi6b924872008-11-28 13:22:09 +0100208 /* Set to Host mode */
Vivek Mahajan08066152009-06-19 17:56:00 +0530209 setbits_le32(&ehci->usbmode, CM_HOST);
Michael Trimarchi6b924872008-11-28 13:22:09 +0100210
Vivek Mahajan08066152009-06-19 17:56:00 +0530211 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
212 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
Michael Trimarchi6b924872008-11-28 13:22:09 +0100213
214 /* Init phy */
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530215#ifdef CONFIG_DM_USB
216 if (priv->phy_type)
217 phy_type = priv->phy_type;
218#else
219 memset(current_usb_controller, '\0', 5);
220 snprintf(current_usb_controller, sizeof(current_usb_controller),
221 "usb%d", index+1);
222
Nikhil Badola0ecb15c2013-12-19 11:08:46 +0530223 if (hwconfig_sub(current_usb_controller, "phy_type"))
224 phy_type = hwconfig_subarg(current_usb_controller,
225 "phy_type", &len);
Rajesh Bhagatba699a52016-07-01 18:51:46 +0530226#endif
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530227 else
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530228 phy_type = getenv("usb_phy_type");
229
230 if (!phy_type) {
231#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
232 /* if none specified assume internal UTMI */
233 strcpy(usb_phy, "utmi");
234 phy_type = usb_phy;
235#else
236 printf("WARNING: USB phy type not defined !!\n");
237 return -1;
238#endif
239 }
240
Nikhil Badola91d77462014-02-17 16:58:36 +0530241 if (!strncmp(phy_type, "utmi", 4)) {
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530242#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
Nikhil Badola15231f62014-05-08 17:05:26 +0530243 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
244 PHY_CLK_SEL_UTMI);
245 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
246 UTMI_PHY_EN);
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530247 udelay(1000); /* delay required for PHY Clk to appear */
248#endif
Rajesh Bhagat1e61ce92016-07-01 18:51:45 +0530249 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
Nikhil Badola15231f62014-05-08 17:05:26 +0530250 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
251 USB_EN);
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530252 } else {
Nikhil Badola15231f62014-05-08 17:05:26 +0530253 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
254 PHY_CLK_SEL_ULPI);
255 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
256 CONTROL_REGISTER_W1C_MASK, USB_EN);
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530257 udelay(1000); /* delay required for PHY Clk to appear */
Shengzhou Liu047cea32012-10-22 13:18:24 +0800258 if (!usb_phy_clk_valid(ehci))
259 return -EINVAL;
Rajesh Bhagat1e61ce92016-07-01 18:51:45 +0530260 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530261 }
Michael Trimarchi6b924872008-11-28 13:22:09 +0100262
Vivek Mahajan08066152009-06-19 17:56:00 +0530263 out_be32(&ehci->prictrl, 0x0000000c);
264 out_be32(&ehci->age_cnt_limit, 0x00000040);
265 out_be32(&ehci->sictrl, 0x00000001);
Michael Trimarchi6b924872008-11-28 13:22:09 +0100266
Vivek Mahajan08066152009-06-19 17:56:00 +0530267 in_le32(&ehci->usbmode);
Michael Trimarchi6b924872008-11-28 13:22:09 +0100268
Nikhil Badolaf3dff692014-10-17 09:12:07 +0530269 if (has_erratum_a007798())
Nikhil Badola896720c2014-04-07 08:46:14 +0530270 set_txfifothresh(ehci, TXFIFOTHRESH);
271
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530272 if (has_erratum_a004477()) {
273 /*
274 * When reset is issued while any ULPI transaction is ongoing
275 * then it may result to corruption of ULPI Function Control
276 * Register which eventually causes phy clock to enter low
277 * power mode which stops the clock. Thus delay is required
278 * before reset to let ongoing ULPI transaction complete.
279 */
280 udelay(1);
281 }
Michael Trimarchi6b924872008-11-28 13:22:09 +0100282 return 0;
283}
284
285/*
Nikhil Badola896720c2014-04-07 08:46:14 +0530286 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
287 * to counter DDR latencies in writing data into Tx buffer.
288 * This prevents Tx buffer from getting underrun
289 */
290static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
291{
292 u32 cmd;
293 cmd = ehci_readl(&ehci->txfilltuning);
294 cmd &= ~TXFIFO_THRESH_MASK;
295 cmd |= TXFIFO_THRESH(txfifo_thresh);
296 ehci_writel(&ehci->txfilltuning, cmd);
297}