blob: d48460b9f5c129b06857df00e3ef0e5e5eb6453b [file] [log] [blame]
wdenk0f8c9762002-08-19 11:57:05 +00001 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
17 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
18 */
19
20/* ------------------------------------------------------------------------- */
21
22/*
23 * board/config.h - configuration options, board specific
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
wdenk0f8c9762002-08-19 11:57:05 +000033#define CONFIG_MPC850 1
34#define CONFIG_MPC850SAR 1
35#define CONFIG_FADS 1
36
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_SYS_TEXT_BASE 0xFE000000
38
wdenk0f8c9762002-08-19 11:57:05 +000039#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 9600
43
44#if 0
45#define MPC8XX_FACT 10 /* Multiply by 10 */
46#define MPC8XX_XIN 50000000 /* 50 MHz in */
47#else
48#define MPC8XX_FACT 12 /* Multiply by 12 */
49#define MPC8XX_XIN 4000000 /* 4 MHz in */
50#endif
51#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
52
53#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
54
55#if 1
56#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57#else
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59#endif
60
61#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */
62#define CONFIG_BOOTARGS " "
63
64#undef CONFIG_WATCHDOG /* watchdog disabled */
65
Jon Loeliger60a08762007-07-07 21:04:26 -050066
67/*
Jon Loeliger11799432007-07-10 09:02:57 -050068 * BOOTP options
69 */
70#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74
75
76/*
Jon Loeliger60a08762007-07-07 21:04:26 -050077 * Command line configuration.
78 */
79#include <config_cmd_default.h>
80
wdenk0f8c9762002-08-19 11:57:05 +000081
82/*
83 * Miscellaneous configurable options
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_LONGHELP /* undef to save memory */
86#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */
Jon Loeliger60a08762007-07-07 21:04:26 -050087#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000089#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000091#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
93#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
94#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
97#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000100
wdenk0f8c9762002-08-19 11:57:05 +0000101/*
102 * Low Level Configuration Settings
103 * (address mappings, register initial values, etc.)
104 * You should know what you are doing if you make changes here.
105 */
106/*-----------------------------------------------------------------------
107 * Internal Memory Mapped Register
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_IMMR 0xFF000000
110#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
wdenk0f8c9762002-08-19 11:57:05 +0000111
112/*-----------------------------------------------------------------------
113 * Definitions for initial stack pointer and data area (in DPRAM)
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200116#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200117#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000119
120/*-----------------------------------------------------------------------
121 * Start addresses for the final memory configuration
122 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000124 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_SDRAM_BASE 0x00000000
127#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
128#define CONFIG_SYS_FLASH_BASE 0x02800000
129#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
wdenk0f8c9762002-08-19 11:57:05 +0000130#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000132#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000134#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
136#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
wdenk0f8c9762002-08-19 11:57:05 +0000137
138/*
139 * For booting Linux, the board info and command line data
140 * have to be in the first 8 MB of memory, since this is
141 * the maximum mapped by the Linux kernel during initialization.
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000144/*-----------------------------------------------------------------------
145 * FLASH organization
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
148#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
151#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000152
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200153#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200154#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
155#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk0f8c9762002-08-19 11:57:05 +0000157
158/*-----------------------------------------------------------------------
159 * Cache Configuration
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500162#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk0f8c9762002-08-19 11:57:05 +0000164#endif
165
166/*-----------------------------------------------------------------------
167 * SYPCR - System Protection Control 11-9
168 * SYPCR can only be written once after reset!
169 *-----------------------------------------------------------------------
170 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
171 */
172#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk0f8c9762002-08-19 11:57:05 +0000174 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
175#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000177#endif
178
179/*-----------------------------------------------------------------------
180 * SIUMCR - SIU Module Configuration 11-6
181 *-----------------------------------------------------------------------
182 * PCMCIA config., multi-function pin tri-state
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk0f8c9762002-08-19 11:57:05 +0000185
186/*-----------------------------------------------------------------------
187 * TBSCR - Time Base Status and Control 11-26
188 *-----------------------------------------------------------------------
189 * Clear Reference Interrupt Status, Timebase freezing enabled
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
wdenk0f8c9762002-08-19 11:57:05 +0000192
193/*-----------------------------------------------------------------------
194 * PISCR - Periodic Interrupt Status and Control 11-31
195 *-----------------------------------------------------------------------
196 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk0f8c9762002-08-19 11:57:05 +0000199
200/*-----------------------------------------------------------------------
201 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
202 *-----------------------------------------------------------------------
203 * Reset PLL lock status sticky bit, timer expired status bit and timer *
204 * interrupt status bit - leave PLL multiplication factor unchanged !
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << 20) | \
wdenk0f8c9762002-08-19 11:57:05 +0000207 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
208
209/*-----------------------------------------------------------------------
210 * SCCR - System Clock and reset Control Register 15-27
211 *-----------------------------------------------------------------------
212 * Set clock output, timebase and RTC source and divider,
213 * power management and some other internal clocks
214 */
215#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk0f8c9762002-08-19 11:57:05 +0000217 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
218 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
219 SCCR_DFALCD00)
220
221 /*-----------------------------------------------------------------------
222 *
223 *-----------------------------------------------------------------------
224 *
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_DER 0
wdenk0f8c9762002-08-19 11:57:05 +0000227
228/* Because of the way the 860 starts up and assigns CS0 the
229* entire address space, we have to set the memory controller
230* differently. Normally, you write the option register
231* first, and then enable the chip select by writing the
232* base register. For CS0, you must write the base register
233* first, followed by the option register.
234*/
235
236/*
237 * Init Memory Controller:
238 *
239 * BR0/1 and OR0/1 (FLASH)
240 */
241/* the other CS:s are determined by looking at parameters in BCSRx */
242
243
244#define BCSR_ADDR ((uint) 0x02100000)
245#define BCSR_SIZE ((uint)(64 * 1024))
246
247#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
248#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
251#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
wdenk0f8c9762002-08-19 11:57:05 +0000252
253/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
wdenk0f8c9762002-08-19 11:57:05 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
257#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
258#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000259
260/* BCSRx - Board Control and Status Registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
262#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
263#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000264
265
266/*
267 * Memory Periodic Timer Prescaler
268 */
269
270/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk0f8c9762002-08-19 11:57:05 +0000272
273/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
275#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000276
277/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
279#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000280
281/*
282 * MAMR settings for SDRAM
283 */
284
285/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk0f8c9762002-08-19 11:57:05 +0000287 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
288 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
289/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk0f8c9762002-08-19 11:57:05 +0000291 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
292 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_MAMR 0x13a01114
wdenk0f8c9762002-08-19 11:57:05 +0000295
296/* values according to the manual */
297
298
299#define PCMCIA_MEM_ADDR ((uint)0xff020000)
300#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
301
302#define BCSR0 ((uint) (BCSR_ADDR + 00))
303#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
304#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
305#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
306#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
307
308/* FADS bitvalues by Helmut Buchsbaum
309 * see MPC8xxADS User's Manual for a proper description
310 * of the following structures
311 */
312
313#define BCSR0_ERB ((uint)0x80000000)
314#define BCSR0_IP ((uint)0x40000000)
315#define BCSR0_BDIS ((uint)0x10000000)
316#define BCSR0_BPS_MASK ((uint)0x0C000000)
317#define BCSR0_ISB_MASK ((uint)0x01800000)
318#define BCSR0_DBGC_MASK ((uint)0x00600000)
319#define BCSR0_DBPC_MASK ((uint)0x00180000)
320#define BCSR0_EBDF_MASK ((uint)0x00060000)
321
322#define BCSR1_FLASH_EN ((uint)0x80000000)
323#define BCSR1_DRAM_EN ((uint)0x40000000)
324#define BCSR1_ETHEN ((uint)0x20000000)
325#define BCSR1_IRDEN ((uint)0x10000000)
326#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
327#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
328#define BCSR1_BCSR_EN ((uint)0x02000000)
329#define BCSR1_RS232EN_1 ((uint)0x01000000)
330#define BCSR1_PCCEN ((uint)0x00800000)
331#define BCSR1_PCCVCC0 ((uint)0x00400000)
332#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
333#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
334#define BCSR1_RS232EN_2 ((uint)0x00040000)
335#define BCSR1_SDRAM_EN ((uint)0x00020000)
336#define BCSR1_PCCVCC1 ((uint)0x00010000)
337
338#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenkb54d32b2004-06-10 21:34:36 +0000339#define BCSR2_FLASH_PD_SHIFT 28
wdenk0f8c9762002-08-19 11:57:05 +0000340#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
wdenkb54d32b2004-06-10 21:34:36 +0000341#define BCSR2_DRAM_PD_SHIFT 23
wdenk0f8c9762002-08-19 11:57:05 +0000342#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
343#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
344
345#define BCSR3_DBID_MASK ((ushort)0x3800)
346#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
347#define BCSR3_BREVNR0 ((ushort)0x0080)
348#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
349#define BCSR3_BREVN1 ((ushort)0x0008)
350#define BCSR3_BREVN2_MASK ((ushort)0x0003)
351
352#define BCSR4_ETHLOOP ((uint)0x80000000)
353#define BCSR4_TFPLDL ((uint)0x40000000)
354#define BCSR4_TPSQEL ((uint)0x20000000)
355#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
356#ifdef CONFIG_MPC823
357#define BCSR4_USB_EN ((uint)0x08000000)
358#endif /* CONFIG_MPC823 */
359#ifdef CONFIG_MPC860SAR
360#define BCSR4_UTOPIA_EN ((uint)0x08000000)
361#endif /* CONFIG_MPC860SAR */
362#ifdef CONFIG_MPC860T
363#define BCSR4_FETH_EN ((uint)0x08000000)
364#endif /* CONFIG_MPC860T */
365#ifdef CONFIG_MPC823
366#define BCSR4_USB_SPEED ((uint)0x04000000)
367#endif /* CONFIG_MPC823 */
368#ifdef CONFIG_MPC860T
369#define BCSR4_FETHCFG0 ((uint)0x04000000)
370#endif /* CONFIG_MPC860T */
371#ifdef CONFIG_MPC823
372#define BCSR4_VCCO ((uint)0x02000000)
373#endif /* CONFIG_MPC823 */
374#ifdef CONFIG_MPC860T
375#define BCSR4_FETHFDE ((uint)0x02000000)
376#endif /* CONFIG_MPC860T */
377#ifdef CONFIG_MPC823
378#define BCSR4_VIDEO_ON ((uint)0x00800000)
379#endif /* CONFIG_MPC823 */
380#ifdef CONFIG_MPC823
381#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
382#endif /* CONFIG_MPC823 */
383#ifdef CONFIG_MPC860T
384#define BCSR4_FETHCFG1 ((uint)0x00400000)
385#endif /* CONFIG_MPC860T */
386#ifdef CONFIG_MPC823
387#define BCSR4_VIDEO_RST ((uint)0x00200000)
388#endif /* CONFIG_MPC823 */
389#ifdef CONFIG_MPC860T
390#define BCSR4_FETHRST ((uint)0x00200000)
391#endif /* CONFIG_MPC860T */
392#define BCSR4_MODEM_EN ((uint)0x00100000)
393#define BCSR4_DATA_VOICE ((uint)0x00080000)
394
395#define CONFIG_DRAM_50MHZ 1
396#define CONFIG_SDRAM_50MHZ
397
wdenk0f8c9762002-08-19 11:57:05 +0000398/* We don't use the 8259.
399*/
400#define NR_8259_INTS 0
401
wdenk0f8c9762002-08-19 11:57:05 +0000402#define CONFIG_DISK_SPINUP_TIME 1000000
403
404
405/* PCMCIA configuration */
406
407#define PCMCIA_MAX_SLOTS 2
408
409#ifdef CONFIG_MPC860
410#define PCMCIA_SLOT_A 1
411#endif
412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_DAUGHTERBOARD
wdenk180d3f72004-01-04 16:28:35 +0000414
wdenk0f8c9762002-08-19 11:57:05 +0000415#endif /* __CONFIG_H */