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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
Stefan Roesedbbd1252007-10-05 17:10:59 +02002 * (C) Copyright 2000-2007
wdenk4a9cbbe2002-08-27 09:48:53 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
Stefan Roesed6c61aa2005-08-16 18:18:00 +020026#include <ppc4xx_enet.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000027#include <asm/processor.h>
Stefan Roese0d974d52007-03-24 15:57:09 +010028#include <asm/gpio.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000029#include <ppc4xx.h>
30
Wolfgang Denkd87080b2006-03-31 18:32:53 +020031#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
32DECLARE_GLOBAL_DATA_PTR;
33#endif
34
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#ifndef CONFIG_SYS_PLL_RECONFIG
36#define CONFIG_SYS_PLL_RECONFIG 0
Mike Nussf66e2c82008-02-20 11:54:20 -050037#endif
38
39void reconfigure_pll(u32 new_cpu_freq)
40{
41#if defined(CONFIG_440EPX)
42 int reset_needed = 0;
43 u32 reg, temp;
44 u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
45 fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
46 fbdv, target_fbdv, lfbdv, target_lfbdv,
47 perdv0, target_perdv0, /* CLK_PERD */
48 spcid0, target_spcid0; /* CLK_SPCID */
49
50 /* Reconfigure clocks if necessary.
51 * See PPC440EPx User's Manual, sections 8.2 and 14 */
52 if (new_cpu_freq == 667) {
53 target_prbdv0 = 2;
54 target_fwdva = 2;
55 target_fwdvb = 4;
56 target_fbdv = 20;
57 target_lfbdv = 1;
58 target_perdv0 = 4;
59 target_spcid0 = 4;
60
61 mfcpr(clk_primbd, reg);
62 temp = (reg & PRBDV_MASK) >> 24;
63 prbdv0 = temp ? temp : 8;
64 if (prbdv0 != target_prbdv0) {
65 reg &= ~PRBDV_MASK;
66 reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
67 mtcpr(clk_primbd, reg);
68 reset_needed = 1;
69 }
70
71 mfcpr(clk_plld, reg);
72
73 temp = (reg & PLLD_FWDVA_MASK) >> 16;
74 fwdva = temp ? temp : 16;
75
76 temp = (reg & PLLD_FWDVB_MASK) >> 8;
77 fwdvb = temp ? temp : 8;
78
79 temp = (reg & PLLD_FBDV_MASK) >> 24;
80 fbdv = temp ? temp : 32;
81
82 temp = (reg & PLLD_LFBDV_MASK);
83 lfbdv = temp ? temp : 64;
84
85 if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
86 reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
87 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
88 reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
89 ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
90 ((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
91 (target_lfbdv == 64 ? 0 : target_lfbdv);
92 mtcpr(clk_plld, reg);
93 reset_needed = 1;
94 }
95
96 mfcpr(clk_perd, reg);
97 perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
98 if (perdv0 != target_perdv0) {
99 reg &= ~CPR0_PERD_PERDV0_MASK;
100 reg |= (target_perdv0 << 24);
101 mtcpr(clk_perd, reg);
102 reset_needed = 1;
103 }
104
105 mfcpr(clk_spcid, reg);
106 temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
107 spcid0 = temp ? temp : 4;
108 if (spcid0 != target_spcid0) {
109 reg &= ~CPR0_SPCID_SPCIDV0_MASK;
110 reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
111 mtcpr(clk_spcid, reg);
112 reset_needed = 1;
113 }
114
115 /* Set reload inhibit so configuration will persist across
116 * processor resets */
117 mfcpr(clk_icfg, reg);
118 reg &= ~CPR0_ICFG_RLI_MASK;
119 reg |= 1 << 31;
120 mtcpr(clk_icfg, reg);
121 }
122
123 /* Reset processor if configuration changed */
124 if (reset_needed) {
125 __asm__ __volatile__ ("sync; isync");
126 mtspr(dbcr0, 0x20000000);
127 }
128#endif
129}
130
wdenk4a9cbbe2002-08-27 09:48:53 +0000131/*
132 * Breath some life into the CPU...
133 *
Mike Nussf66e2c82008-02-20 11:54:20 -0500134 * Reconfigure PLL if necessary,
135 * set up the memory map,
wdenk4a9cbbe2002-08-27 09:48:53 +0000136 * initialize a bunch of registers
137 */
138void
139cpu_init_f (void)
140{
Stefan Roesef5564832008-08-21 11:05:03 +0200141#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
Stefan Roese745d8a02008-06-28 14:56:17 +0200142 u32 val;
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100143#endif
Stefan Roese5de85142008-06-26 17:36:39 +0200144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
stroeseb867d702003-05-23 11:18:02 +0000148 /*
149 * GPIO0 setup (select GPIO or alternate function)
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#if defined(CONFIG_SYS_GPIO0_OR)
152 out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */
Stefan Roesee0a46552006-10-12 19:43:29 +0200153#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#if defined(CONFIG_SYS_GPIO0_ODR)
155 out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */
Stefan Roesee0a46552006-10-12 19:43:29 +0200156#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
158 out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
159 out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
160 out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
161 out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
162 out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
163#if defined(CONFIG_SYS_GPIO0_ISR2H)
164 out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
165 out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200166#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#if defined (CONFIG_SYS_GPIO0_TCR)
168 out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200169#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
stroeseb867d702003-05-23 11:18:02 +0000171
Stefan Roesebec92642007-12-28 15:53:46 +0100172#if defined (CONFIG_405EP)
stroeseb867d702003-05-23 11:18:02 +0000173 /*
174 * Set EMAC noise filter bits
175 */
176 mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
Stefan Roesec0556902007-12-28 16:08:08 +0100177
178 /*
179 * Enable the internal PCI arbiter
180 */
181 mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
stroeseb867d702003-05-23 11:18:02 +0000182#endif /* CONFIG_405EP */
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
Stefan Roese0d974d52007-03-24 15:57:09 +0100185 gpio_set_chip_configuration();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200187
wdenk4a9cbbe2002-08-27 09:48:53 +0000188 /*
189 * External Bus Controller (EBC) Setup
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
Stefan Roesea4c8d132006-06-02 16:18:04 +0200192#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
Stefan Roesee01bd212007-03-21 13:38:59 +0100193 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200194 defined(CONFIG_405EX) || defined(CONFIG_405))
wdenk4a9cbbe2002-08-27 09:48:53 +0000195 /*
196 * Move the next instructions into icache, since these modify the flash
197 * we are running from!
198 */
199 asm volatile(" bl 0f" ::: "lr");
200 asm volatile("0: mflr 3" ::: "r3");
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200201 asm volatile(" addi 4, 0, 14" ::: "r4");
wdenk4a9cbbe2002-08-27 09:48:53 +0000202 asm volatile(" mtctr 4" ::: "ctr");
203 asm volatile("1: icbt 0, 3");
204 asm volatile(" addi 3, 3, 32" ::: "r3");
205 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
206 asm volatile(" addis 3, 0, 0x0" ::: "r3");
207 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
208 asm volatile(" mtctr 3" ::: "ctr");
209 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
Stefan Roesea4c8d132006-06-02 16:18:04 +0200210#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
213 mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000214#endif
215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
217 mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP);
218 mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000219#endif
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
222 mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP);
223 mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000224#endif
225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
227 mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP);
228 mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000229#endif
230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
232 mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP);
233 mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000234#endif
235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
237 mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP);
238 mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000239#endif
240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
242 mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP);
243 mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000244#endif
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
247 mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP);
248 mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000249#endif
250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#if defined (CONFIG_SYS_EBC_CFG)
252 mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
Heiko Schocherca43ba12007-01-11 15:44:44 +0100253#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000254
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100255#if defined(CONFIG_WATCHDOG)
wdenk4a9cbbe2002-08-27 09:48:53 +0000256 val = mfspr(tcr);
Stefan Roese846b0dd2005-08-08 12:42:22 +0200257#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200258 val |= 0xb8000000; /* generate system reset after 1.34 seconds */
Igor Lisitsina11e0692007-03-28 19:06:19 +0400259#elif defined(CONFIG_440EPX)
260 val |= 0xb0000000; /* generate system reset after 1.34 seconds */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200261#else
wdenk4a9cbbe2002-08-27 09:48:53 +0000262 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200263#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#if defined(CONFIG_SYS_4xx_RESET_TYPE)
Stefan Roese1c2ce222006-11-27 14:12:17 +0100265 val &= ~0x30000000; /* clear WRC bits */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266 val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100267#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000268 mtspr(tcr, val);
269
270 val = mfspr(tsr);
271 val |= 0x80000000; /* enable watchdog timer */
272 mtspr(tsr, val);
273
274 reset_4xx_watchdog();
275#endif /* CONFIG_WATCHDOG */
Stefan Roese745d8a02008-06-28 14:56:17 +0200276
Stefan Roese5de85142008-06-26 17:36:39 +0200277#if defined(CONFIG_440GX)
278 /* Take the GX out of compatibility mode
279 * Travis Sawyer, 9 Mar 2004
280 * NOTE: 440gx user manual inconsistency here
281 * Compatibility mode and Ethernet Clock select are not
282 * correct in the manual
283 */
284 mfsdr(sdr_mfr, val);
285 val &= ~0x10000000;
286 mtsdr(sdr_mfr,val);
287#endif /* CONFIG_440GX */
288
Stefan Roese745d8a02008-06-28 14:56:17 +0200289#if defined(CONFIG_460EX)
290 /*
291 * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
292 * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
293 * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
294 */
295 mfsdr(SDR0_AHB_CFG, val);
296 val |= 0x80;
297 val &= ~0x40;
298 mtsdr(SDR0_AHB_CFG, val);
299 mfsdr(SDR0_USB2HOST_CFG, val);
300 val &= ~0xf00;
301 val |= 0x400;
302 mtsdr(SDR0_USB2HOST_CFG, val);
303#endif /* CONFIG_460EX */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700304
Stefan Roesef5564832008-08-21 11:05:03 +0200305#if defined(CONFIG_405EX) || \
306 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700307 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesef5564832008-08-21 11:05:03 +0200308 defined(CONFIG_460SX)
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700309 /*
310 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
311 */
Stefan Roesef5564832008-08-21 11:05:03 +0200312 mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) |
313 plb0_acr_rdp_4deep);
314 mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) |
315 plb1_acr_rdp_4deep);
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700316#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
wdenk4a9cbbe2002-08-27 09:48:53 +0000317}
318
319/*
320 * initialize higher level parts of CPU like time base and timers
321 */
322int cpu_init_r (void)
323{
stroeseb867d702003-05-23 11:18:02 +0000324#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
wdenk4a9cbbe2002-08-27 09:48:53 +0000325 bd_t *bd = gd->bd;
326 unsigned long reg;
stroeseb867d702003-05-23 11:18:02 +0000327#if defined(CONFIG_405GP)
stroese38daa272003-03-20 15:21:50 +0000328 uint pvr = get_pvr();
stroeseb867d702003-05-23 11:18:02 +0000329#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000330
331 /*
332 * Write Ethernetaddress into on-chip register
333 */
334 reg = 0x00000000;
335 reg |= bd->bi_enetaddr[0]; /* set high address */
336 reg = reg << 8;
337 reg |= bd->bi_enetaddr[1];
338 out32 (EMAC_IAH, reg);
339
340 reg = 0x00000000;
341 reg |= bd->bi_enetaddr[2]; /* set low address */
342 reg = reg << 8;
343 reg |= bd->bi_enetaddr[3];
344 reg = reg << 8;
345 reg |= bd->bi_enetaddr[4];
346 reg = reg << 8;
347 reg |= bd->bi_enetaddr[5];
348 out32 (EMAC_IAL, reg);
stroese38daa272003-03-20 15:21:50 +0000349
stroeseb867d702003-05-23 11:18:02 +0000350#if defined(CONFIG_405GP)
stroese38daa272003-03-20 15:21:50 +0000351 /*
352 * Set edge conditioning circuitry on PPC405GPr
353 * for compatibility to existing PPC405GP designs.
354 */
stroesebaa3d522003-04-04 16:00:33 +0000355 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
stroese38daa272003-03-20 15:21:50 +0000356 mtdcr(ecr, 0x60606000);
357 }
stroeseb867d702003-05-23 11:18:02 +0000358#endif /* defined(CONFIG_405GP) */
359#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
Stefan Roese2801b2d2008-03-11 15:05:50 +0100360
wdenk4a9cbbe2002-08-27 09:48:53 +0000361 return (0);
362}