blob: 26095a545596f96a48f775b18ebed7bad0084a31 [file] [log] [blame]
Joe Hamman11c45eb2007-12-13 06:45:08 -06001/*
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -04002 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
3 *
Joe Hamman11c45eb2007-12-13 06:45:08 -06004 * Copyright 2007 Embedded Specialties, Inc.
5 *
6 * Copyright 2004, 2007 Freescale Semiconductor.
7 *
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <pci.h>
31#include <asm/processor.h>
32#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050033#include <asm/fsl_pci.h>
Kumar Gala33b90792008-08-26 23:15:28 -050034#include <asm/fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060035#include <asm/fsl_serdes.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060036#include <spd_sdram.h>
Paul Gortmaker94ca0912009-09-18 19:08:44 -040037#include <netdev.h>
38#include <tsec.h>
Joe Hamman11c45eb2007-12-13 06:45:08 -060039#include <miiphy.h>
40#include <libfdt.h>
41#include <fdt_support.h>
42
Joe Hamman11c45eb2007-12-13 06:45:08 -060043DECLARE_GLOBAL_DATA_PTR;
44
Joe Hamman11c45eb2007-12-13 06:45:08 -060045void local_bus_init(void);
Joe Hamman11c45eb2007-12-13 06:45:08 -060046
47int board_early_init_f (void)
48{
49 return 0;
50}
51
52int checkboard (void)
53{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
55 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
Joe Hamman11c45eb2007-12-13 06:45:08 -060056
57 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040058 in_8(rev) >> 4);
Joe Hamman11c45eb2007-12-13 06:45:08 -060059
60 /*
61 * Initialize local bus.
62 */
63 local_bus_init ();
64
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040065 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
66 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
Joe Hamman11c45eb2007-12-13 06:45:08 -060067 return 0;
68}
69
Joe Hamman11c45eb2007-12-13 06:45:08 -060070/*
71 * Initialize Local Bus
72 */
73void
74local_bus_init(void)
75{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -050077 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Joe Hamman11c45eb2007-12-13 06:45:08 -060078
79 uint clkdiv;
Joe Hamman11c45eb2007-12-13 06:45:08 -060080 sys_info_t sysinfo;
81
82 get_sys_info(&sysinfo);
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040083 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
Joe Hamman11c45eb2007-12-13 06:45:08 -060084
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040085 out_be32(&gur->lbiuiplldcr1, 0x00078080);
Joe Hamman11c45eb2007-12-13 06:45:08 -060086 if (clkdiv == 16) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040087 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -060088 } else if (clkdiv == 8) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040089 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -060090 } else if (clkdiv == 4) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040091 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -060092 }
93
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040094 setbits_be32(&lbc->lcrr, 0x00030000);
Joe Hamman11c45eb2007-12-13 06:45:08 -060095
96 asm("sync;isync;msync");
97
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040098 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
99 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600100}
101
102/*
103 * Initialize SDRAM memory on the Local Bus.
104 */
Becky Bruce70961ba2010-12-17 17:17:57 -0600105void lbc_sdram_init(void)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600106{
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400107#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600108
109 uint idx;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500110 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600112 uint lsdmr_common;
113
114 puts(" SDRAM: ");
115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600117
118 /*
119 * Setup SDRAM Base and Option Registers
120 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500121 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
122 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
123 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
124 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400125
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400126 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600127 asm("msync");
128
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400129 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
130 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600131 asm("msync");
132
133 /*
134 * MPC8548 uses "new" 15-16 style addressing.
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500137 lsdmr_common |= LSDMR_BSMA1516;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600138
139 /*
140 * Issue PRECHARGE ALL command.
141 */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400142 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600143 asm("sync;msync");
144 *sdram_addr = 0xff;
145 ppcDcbf((unsigned long) sdram_addr);
146 udelay(100);
147
148 /*
149 * Issue 8 AUTO REFRESH commands.
150 */
151 for (idx = 0; idx < 8; idx++) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400152 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600153 asm("sync;msync");
154 *sdram_addr = 0xff;
155 ppcDcbf((unsigned long) sdram_addr);
156 udelay(100);
157 }
158
159 /*
160 * Issue 8 MODE-set command.
161 */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400162 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600163 asm("sync;msync");
164 *sdram_addr = 0xff;
165 ppcDcbf((unsigned long) sdram_addr);
166 udelay(100);
167
168 /*
169 * Issue NORMAL OP command.
170 */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400171 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600172 asm("sync;msync");
173 *sdram_addr = 0xff;
174 ppcDcbf((unsigned long) sdram_addr);
175 udelay(200); /* Overkill. Must wait > 200 bus cycles */
176
177#endif /* enable SDRAM init */
178}
179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#if defined(CONFIG_SYS_DRAM_TEST)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600181int
182testdram(void)
183{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
185 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600186 uint *p;
187
188 printf("Testing DRAM from 0x%08x to 0x%08x\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 CONFIG_SYS_MEMTEST_START,
190 CONFIG_SYS_MEMTEST_END);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600191
192 printf("DRAM test phase 1:\n");
193 for (p = pstart; p < pend; p++)
194 *p = 0xaaaaaaaa;
195
196 for (p = pstart; p < pend; p++) {
197 if (*p != 0xaaaaaaaa) {
198 printf ("DRAM test fails at: %08x\n", (uint) p);
199 return 1;
200 }
201 }
202
203 printf("DRAM test phase 2:\n");
204 for (p = pstart; p < pend; p++)
205 *p = 0x55555555;
206
207 for (p = pstart; p < pend; p++) {
208 if (*p != 0x55555555) {
209 printf ("DRAM test fails at: %08x\n", (uint) p);
210 return 1;
211 }
212 }
213
214 printf("DRAM test passed.\n");
215 return 0;
216}
217#endif
218
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400219#if !defined(CONFIG_SPD_EEPROM)
220#define CONFIG_SYS_DDR_CONTROL 0xc300c000
Joe Hamman11c45eb2007-12-13 06:45:08 -0600221/*************************************************************************
222 * fixed_sdram init -- doesn't use serial presence detect.
223 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
224 ************************************************************************/
Becky Bruce38dba0c2010-12-17 17:17:56 -0600225phys_size_t fixed_sdram(void)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600226{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600228
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400229 out_be32(&ddr->cs0_bnds, 0x0000007f);
230 out_be32(&ddr->cs1_bnds, 0x008000ff);
231 out_be32(&ddr->cs2_bnds, 0x00000000);
232 out_be32(&ddr->cs3_bnds, 0x00000000);
233 out_be32(&ddr->cs0_config, 0x80010101);
234 out_be32(&ddr->cs1_config, 0x80010101);
235 out_be32(&ddr->cs2_config, 0x00000000);
236 out_be32(&ddr->cs3_config, 0x00000000);
237 out_be32(&ddr->timing_cfg_3, 0x00000000);
238 out_be32(&ddr->timing_cfg_0, 0x00220802);
239 out_be32(&ddr->timing_cfg_1, 0x38377322);
240 out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
241 out_be32(&ddr->sdram_cfg, 0x4300C000);
242 out_be32(&ddr->sdram_cfg_2, 0x24401000);
243 out_be32(&ddr->sdram_mode, 0x23C00542);
244 out_be32(&ddr->sdram_mode_2, 0x00000000);
245 out_be32(&ddr->sdram_interval, 0x05080100);
246 out_be32(&ddr->sdram_md_cntl, 0x00000000);
247 out_be32(&ddr->sdram_data_init, 0x00000000);
248 out_be32(&ddr->sdram_clk_cntl, 0x03800000);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600249 asm("sync;isync;msync");
250 udelay(500);
251
252 #if defined (CONFIG_DDR_ECC)
253 /* Enable ECC checking */
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400254 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600255 #else
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400256 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600257 #endif
258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600260}
261#endif
262
Paul Gortmaker7b1f1392009-09-18 19:08:39 -0400263#ifdef CONFIG_PCI1
264static struct pci_controller pci1_hose;
265#endif /* CONFIG_PCI1 */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600266
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400267#ifdef CONFIG_PCI
Joe Hamman11c45eb2007-12-13 06:45:08 -0600268void
269pci_init_board(void)
270{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400272 int first_free_busno = 0;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600273
274#ifdef CONFIG_PCI1
Kumar Gala2d0a0542010-12-17 10:30:44 -0600275 struct fsl_pci_info pci_info;
276 u32 devdisr = in_be32(&gur->devdisr);
277 u32 pordevsr = in_be32(&gur->pordevsr);
278 u32 porpllsr = in_be32(&gur->porpllsr);
279
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400280 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
281 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
282 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
283 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
284 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600285
Peter Tyser8ca78f22010-10-29 17:59:24 -0500286 printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
Joe Hamman11c45eb2007-12-13 06:45:08 -0600287 (pci_32) ? 32 : 64,
Paul Gortmaker2c40acd2009-09-18 19:08:40 -0400288 (pci_speed == 33000000) ? "33" :
289 (pci_speed == 66000000) ? "66" : "unknown",
Joe Hamman11c45eb2007-12-13 06:45:08 -0600290 pci_clk_sel ? "sync" : "async",
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400291 pci_arb ? "arbiter" : "external-arbiter");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600292
Kumar Gala2d0a0542010-12-17 10:30:44 -0600293 SET_STD_PCI_INFO(pci_info, 1);
294 set_next_law(pci_info.mem_phys,
295 law_size_bits(pci_info.mem_size), pci_info.law);
296 set_next_law(pci_info.io_phys,
297 law_size_bits(pci_info.io_size), pci_info.law);
298
299 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala01471d52009-11-04 01:29:04 -0600300 &pci1_hose, first_free_busno);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600301 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500302 printf("PCI: disabled\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600303 }
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400304
305 puts("\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600306#else
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400307 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600308#endif
309
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400310 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600311
Kumar Gala2d0a0542010-12-17 10:30:44 -0600312 fsl_pcie_init_board(first_free_busno);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600313}
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400314#endif
Joe Hamman11c45eb2007-12-13 06:45:08 -0600315
Paul Gortmaker94ca0912009-09-18 19:08:44 -0400316int board_eth_init(bd_t *bis)
317{
318 tsec_standard_init(bis);
319 pci_eth_init(bis);
320 return 0; /* otherwise cpu_eth_init gets run */
321}
322
Joe Hamman11c45eb2007-12-13 06:45:08 -0600323int last_stage_init(void)
324{
325 return 0;
326}
327
328#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500329void ft_board_setup(void *blob, bd_t *bd)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600330{
331 ft_cpu_setup(blob, bd);
Kumar Gala6525d512010-07-08 22:37:44 -0500332
333#ifdef CONFIG_FSL_PCI_INIT
334 FT_FSL_PCI_SETUP;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600335#endif
336}
337#endif