blob: 35d15f4271f62f14ca01ea2173e9fb9caf4427ae [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk0ac6f8b2004-07-09 23:27:13 +000025/*
26 * mpc8560ads board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000032 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000038#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050041#define CONFIG_CPM2 1 /* has CPM2 */
wdenk0ac6f8b2004-07-09 23:27:13 +000042#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
Kumar Galaf0600542008-06-11 00:44:10 -050043#define CONFIG_MPC8560 1
wdenk42d1f032003-10-15 23:53:47 +000044
Wolfgang Denk2ae18242010-10-06 09:05:45 +020045/*
46 * default CCARBAR is at 0xff700000
47 * assume U-Boot is less than 0.5MB
48 */
49#define CONFIG_SYS_TEXT_BASE 0xfff80000
50
wdenk0ac6f8b2004-07-09 23:27:13 +000051#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050052#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020053#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingccc091a2007-05-08 17:27:43 -050054#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000055#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060056#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Peter Tyser004eca02009-09-16 22:03:08 -050057#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk42d1f032003-10-15 23:53:47 +000058
wdenk0ac6f8b2004-07-09 23:27:13 +000059/*
60 * sysclk for MPC85xx
61 *
62 * Two valid values are:
63 * 33000000
64 * 66000000
65 *
66 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000067 * is likely the desired value here, so that is now the default.
68 * The board, however, can run at 66MHz. In any event, this value
69 * must match the settings of some switches. Details can be found
70 * in the README.mpc85xxads.
wdenk0ac6f8b2004-07-09 23:27:13 +000071 */
72
wdenk9aea9532004-08-01 23:02:45 +000073#ifndef CONFIG_SYS_CLK_FREQ
74#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000075#endif
76
wdenk9aea9532004-08-01 23:02:45 +000077
wdenk0ac6f8b2004-07-09 23:27:13 +000078/*
79 * These can be toggled for performance analysis, otherwise use default.
80 */
81#define CONFIG_L2_CACHE /* toggle L2 cache */
82#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk42d1f032003-10-15 23:53:47 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
87#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000088
Timur Tabie46fedf2011-08-04 18:03:41 -050089#define CONFIG_SYS_CCSRBAR 0xe0000000
90#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000091
Jon Loeliger8b625112008-03-18 11:12:44 -050092/* DDR Setup */
93#define CONFIG_FSL_DDR1
94#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
95#define CONFIG_DDR_SPD
96#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000097
Jon Loeliger8b625112008-03-18 11:12:44 -050098#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
99
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
101#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000102
Jon Loeliger8b625112008-03-18 11:12:44 -0500103#define CONFIG_NUM_DDR_CONTROLLERS 1
104#define CONFIG_DIMM_SLOTS_PER_CTLR 1
105#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +0000106
Jon Loeliger8b625112008-03-18 11:12:44 -0500107/* I2C addresses of SPD EEPROMs */
108#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +0000109
Jon Loeliger8b625112008-03-18 11:12:44 -0500110/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
112#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
113#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
114#define CONFIG_SYS_DDR_TIMING_1 0x37344321
115#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
116#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
117#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
118#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000119
wdenk0ac6f8b2004-07-09 23:27:13 +0000120/*
121 * SDRAM on the Local Bus
122 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
124#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
127#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
130#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
131#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
132#undef CONFIG_SYS_FLASH_CHECKSUM
133#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000135
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200136#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
139#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000140#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000142#endif
143
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200144#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_FLASH_CFI
146#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk0ac6f8b2004-07-09 23:27:13 +0000147
148#undef CONFIG_CLOCKS_IN_MHZ
wdenk42d1f032003-10-15 23:53:47 +0000149
wdenk42d1f032003-10-15 23:53:47 +0000150
wdenk0ac6f8b2004-07-09 23:27:13 +0000151/*
152 * Local Bus Definitions
153 */
154
155/*
156 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000158 *
159 * For BR2, need:
160 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
161 * port-size = 32-bits = BR2[19:20] = 11
162 * no parity checking = BR2[21:22] = 00
163 * SDRAM for MSEL = BR2[24:26] = 011
164 * Valid = BR[31] = 1
165 *
166 * 0 4 8 12 16 20 24 28
167 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
168 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000170 * FIXME: the top 17 bits of BR2.
171 */
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000174
175/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000177 *
178 * For OR2, need:
179 * 64MB mask for AM, OR2[0:7] = 1111 1100
180 * XAM, OR2[17:18] = 11
181 * 9 columns OR2[19-21] = 010
182 * 13 rows OR2[23-25] = 100
183 * EAD set for extra time OR[31] = 1
184 *
185 * 0 4 8 12 16 20 24 28
186 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
187 */
188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
192#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
193#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
194#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000195
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500196#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
197 | LSDMR_RFCR5 \
198 | LSDMR_PRETOACT3 \
199 | LSDMR_ACTTORW3 \
200 | LSDMR_BL8 \
201 | LSDMR_WRC2 \
202 | LSDMR_CL3 \
203 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000204 )
205
206/*
207 * SDRAM Controller configuration sequence.
208 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500209#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
210#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
211#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
212#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
213#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000214
wdenk42d1f032003-10-15 23:53:47 +0000215
wdenk9aea9532004-08-01 23:02:45 +0000216/*
217 * 32KB, 8-bit wide for ADS config reg
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_BR4_PRELIM 0xf8000801
220#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
221#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_INIT_RAM_LOCK 1
224#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200225#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000226
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200227#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
231#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000232
233/* Serial Port */
wdenk0ac6f8b2004-07-09 23:27:13 +0000234#define CONFIG_CONS_ON_SCC /* define if console on SCC */
235#undef CONFIG_CONS_NONE /* define if console on something else */
236#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
wdenk42d1f032003-10-15 23:53:47 +0000237
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200238#define CONFIG_BAUDRATE 115200
wdenk42d1f032003-10-15 23:53:47 +0000239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000241 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
242
243/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_HUSH_PARSER
245#ifdef CONFIG_SYS_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000246#endif
247
Matthew McClintock0e163872006-06-28 10:43:36 -0500248/* pass open firmware flat tree */
Kumar Gala5ce71582007-11-28 22:40:31 -0600249#define CONFIG_OF_LIBFDT 1
250#define CONFIG_OF_BOARD_SETUP 1
251#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500252
Jon Loeliger20476722006-10-20 15:50:15 -0500253/*
254 * I2C
255 */
256#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
257#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk42d1f032003-10-15 23:53:47 +0000258#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
260#define CONFIG_SYS_I2C_SLAVE 0x7F
261#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
262#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk42d1f032003-10-15 23:53:47 +0000263
wdenk0ac6f8b2004-07-09 23:27:13 +0000264/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600265#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600266#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600267#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk42d1f032003-10-15 23:53:47 +0000269
wdenk0ac6f8b2004-07-09 23:27:13 +0000270/*
271 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300272 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000273 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600274#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600275#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600276#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600278#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600279#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
281#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000282
283#if defined(CONFIG_PCI)
284
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200285#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000286
287#undef CONFIG_EEPRO100
wdenk42d1f032003-10-15 23:53:47 +0000288#undef CONFIG_TULIP
wdenk0ac6f8b2004-07-09 23:27:13 +0000289
290#if !defined(CONFIG_PCI_PNP)
291 #define PCI_ENET0_IOADDR 0xe0000000
292 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200293 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000294#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000295
296#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000298
299#endif /* CONFIG_PCI */
300
301
Andy Flemingccc091a2007-05-08 17:27:43 -0500302#ifdef CONFIG_TSEC_ENET
wdenk0ac6f8b2004-07-09 23:27:13 +0000303
Andy Flemingccc091a2007-05-08 17:27:43 -0500304#ifndef CONFIG_MII
wdenk0ac6f8b2004-07-09 23:27:13 +0000305#define CONFIG_MII 1 /* MII PHY management */
Andy Flemingccc091a2007-05-08 17:27:43 -0500306#endif
Kim Phillips255a35772007-05-16 16:52:19 -0500307#define CONFIG_TSEC1 1
308#define CONFIG_TSEC1_NAME "TSEC0"
309#define CONFIG_TSEC2 1
310#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000311#define TSEC1_PHY_ADDR 0
312#define TSEC2_PHY_ADDR 1
313#define TSEC1_PHYIDX 0
314#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500315#define TSEC1_FLAGS TSEC_GIGABIT
316#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500317
318/* Options are: TSEC[0-1] */
319#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000320
Andy Flemingccc091a2007-05-08 17:27:43 -0500321#endif /* CONFIG_TSEC_ENET */
wdenk0ac6f8b2004-07-09 23:27:13 +0000322
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200323#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
Andy Flemingccc091a2007-05-08 17:27:43 -0500324
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200325#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk0ac6f8b2004-07-09 23:27:13 +0000326#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
327
328#if (CONFIG_ETHER_INDEX == 2)
wdenk42d1f032003-10-15 23:53:47 +0000329 /*
330 * - Rx-CLK is CLK13
331 * - Tx-CLK is CLK14
332 * - Select bus for bd/buffers
333 * - Full duplex
334 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000335 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
336 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
338 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk42d1f032003-10-15 23:53:47 +0000339 #define FETH2_RST 0x01
wdenk0ac6f8b2004-07-09 23:27:13 +0000340#elif (CONFIG_ETHER_INDEX == 3)
wdenk42d1f032003-10-15 23:53:47 +0000341 /* need more definitions here for FE3 */
342 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200343#endif /* CONFIG_ETHER_INDEX */
wdenk0ac6f8b2004-07-09 23:27:13 +0000344
Andy Flemingccc091a2007-05-08 17:27:43 -0500345#ifndef CONFIG_MII
346#define CONFIG_MII 1 /* MII PHY management */
347#endif
348
wdenk0ac6f8b2004-07-09 23:27:13 +0000349#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
350
wdenk42d1f032003-10-15 23:53:47 +0000351/*
352 * GPIO pins used for bit-banged MII communications
353 */
354#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200355#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
356 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
357#define MDC_DECLARE MDIO_DECLARE
358
wdenk42d1f032003-10-15 23:53:47 +0000359#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
360#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
361#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
362
363#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
364 else iop->pdat &= ~0x00400000
365
366#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
367 else iop->pdat &= ~0x00200000
368
369#define MIIDELAY udelay(1)
wdenk0ac6f8b2004-07-09 23:27:13 +0000370
wdenk42d1f032003-10-15 23:53:47 +0000371#endif
372
wdenk0ac6f8b2004-07-09 23:27:13 +0000373
374/*
375 * Environment
376 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200378 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200380 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
381 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000382#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200384 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200386 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000387#endif
388
wdenk0ac6f8b2004-07-09 23:27:13 +0000389#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000391
Jon Loeliger2835e512007-06-13 13:22:08 -0500392/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500393 * BOOTP options
394 */
395#define CONFIG_BOOTP_BOOTFILESIZE
396#define CONFIG_BOOTP_BOOTPATH
397#define CONFIG_BOOTP_GATEWAY
398#define CONFIG_BOOTP_HOSTNAME
399
400
401/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500402 * Command line configuration.
403 */
404#include <config_cmd_default.h>
405
406#define CONFIG_CMD_PING
407#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600408#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500409#define CONFIG_CMD_IRQ
410#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500411#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500412
413#if defined(CONFIG_PCI)
414 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000415#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000416
Jon Loeliger2835e512007-06-13 13:22:08 -0500417#if defined(CONFIG_ETHER_ON_FCC)
418 #define CONFIG_CMD_MII
419#endif
420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500422 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500423 #undef CONFIG_CMD_LOADS
424#endif
425
wdenk42d1f032003-10-15 23:53:47 +0000426
wdenk0ac6f8b2004-07-09 23:27:13 +0000427#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000428
429/*
430 * Miscellaneous configurable options
431 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500433#define CONFIG_CMDLINE_EDITING /* Command-line editing */
434#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
436#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk0ac6f8b2004-07-09 23:27:13 +0000437
Jon Loeliger2835e512007-06-13 13:22:08 -0500438#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000440#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000442#endif
443
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
445#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
446#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
447#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk42d1f032003-10-15 23:53:47 +0000448
449/*
450 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500451 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000452 * the maximum mapped by the Linux kernel during initialization.
453 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500454#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
455#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000456
Jon Loeliger2835e512007-06-13 13:22:08 -0500457#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000458#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
459#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
460#endif
461
wdenk9aea9532004-08-01 23:02:45 +0000462
463/*
464 * Environment Configuration
465 */
466
wdenk0ac6f8b2004-07-09 23:27:13 +0000467/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000468#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500469#define CONFIG_HAS_ETH0
wdenk0ac6f8b2004-07-09 23:27:13 +0000470#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000471#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000472#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000473#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000474#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Kumar Gala5ce71582007-11-28 22:40:31 -0600475#define CONFIG_HAS_ETH3
476#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
wdenk42d1f032003-10-15 23:53:47 +0000477#endif
478
wdenk0ac6f8b2004-07-09 23:27:13 +0000479#define CONFIG_IPADDR 192.168.1.253
480
481#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000482#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000483#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000484
485#define CONFIG_SERVERIP 192.168.1.1
486#define CONFIG_GATEWAYIP 192.168.1.1
487#define CONFIG_NETMASK 255.255.255.0
488
489#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
490
wdenk9aea9532004-08-01 23:02:45 +0000491#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
wdenk0ac6f8b2004-07-09 23:27:13 +0000492#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
493
494#define CONFIG_BAUDRATE 115200
495
wdenk9aea9532004-08-01 23:02:45 +0000496#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming6b44a442008-07-14 20:04:40 -0500497 "netdev=eth0\0" \
498 "consoledev=ttyCPM\0" \
499 "ramdiskaddr=1000000\0" \
500 "ramdiskfile=your.ramdisk.u-boot\0" \
501 "fdtaddr=400000\0" \
502 "fdtfile=mpc8560ads.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000503
wdenk9aea9532004-08-01 23:02:45 +0000504#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500505 "setenv bootargs root=/dev/nfs rw " \
506 "nfsroot=$serverip:$rootpath " \
507 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
508 "console=$consoledev,$baudrate $othbootargs;" \
509 "tftp $loadaddr $bootfile;" \
510 "tftp $fdtaddr $fdtfile;" \
511 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000512
513#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500514 "setenv bootargs root=/dev/ram rw " \
515 "console=$consoledev,$baudrate $othbootargs;" \
516 "tftp $ramdiskaddr $ramdiskfile;" \
517 "tftp $loadaddr $bootfile;" \
518 "tftp $fdtaddr $fdtfile;" \
519 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000520
521#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000522
523#endif /* __CONFIG_H */