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wdenkacea76a2002-09-20 09:17:33 +00001/*
2 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/************************************************************************
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020024 * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
wdenkacea76a2002-09-20 09:17:33 +000025 ***********************************************************************/
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
33#define CONFIG_EBONY 1 /* Board is ebony */
Stefan Roese4a3cd9e2005-09-07 16:21:12 +020034#define CONFIG_440GP 1 /* Specifc GP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020035#define CONFIG_440 1 /* ... PPC440 family */
wdenkacea76a2002-09-20 09:17:33 +000036#define CONFIG_4xx 1 /* ... PPC4xx family */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenkacea76a2002-09-20 09:17:33 +000038#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
39
Stefan Roese8a316c92005-08-01 16:49:12 +020040/*
Stefan Roese490f2042008-06-06 15:55:03 +020041 * Include common defines/options for all AMCC eval boards
42 */
43#define CONFIG_HOSTNAME ebony
44#include "amcc-common.h"
45
46/*
Stefan Roese8a316c92005-08-01 16:49:12 +020047 * Define here the location of the environment variables (FLASH or NVRAM).
48 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
49 * supported for backward compatibility.
50 */
51#if 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020052#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +020053#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020054#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +020055#endif
56
wdenkacea76a2002-09-20 09:17:33 +000057/*-----------------------------------------------------------------------
58 * Base addresses -- Note these are effective addresses where the
59 * actual resources get mapped (not physical addresses)
60 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
62#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
63#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
64#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
65#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
66#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
wdenkacea76a2002-09-20 09:17:33 +000067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
69#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
wdenkacea76a2002-09-20 09:17:33 +000070
71/*-----------------------------------------------------------------------
72 * Initial RAM & stack pointer (placed in internal SRAM)
73 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
75#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
76#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
wdenkacea76a2002-09-20 09:17:33 +000077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
79#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkacea76a2002-09-20 09:17:33 +000080
wdenkacea76a2002-09-20 09:17:33 +000081/*-----------------------------------------------------------------------
82 * Serial Port
83 *----------------------------------------------------------------------*/
84#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
wdenkacea76a2002-09-20 09:17:33 +000086
87/*-----------------------------------------------------------------------
88 * NVRAM/RTC
89 *
90 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
91 * The DS1743 code assumes this condition (i.e. -- it assumes the base
92 * address for the RTC registers is:
93 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
wdenkacea76a2002-09-20 09:17:33 +000095 *
96 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
wdenkacea76a2002-09-20 09:17:33 +000098#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
99
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200100#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200101#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
102#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200104#endif /* CONFIG_ENV_IS_IN_NVRAM */
Stefan Roese8a316c92005-08-01 16:49:12 +0200105
wdenkacea76a2002-09-20 09:17:33 +0000106/*-----------------------------------------------------------------------
107 * FLASH related
108 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
110#define CONFIG_SYS_MAX_FLASH_SECT 32 /* sectors per device */
wdenkacea76a2002-09-20 09:17:33 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
113#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkacea76a2002-09-20 09:17:33 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese8a316c92005-08-01 16:49:12 +0200116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH_ADDR0 0x5555
118#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
119#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese8a316c92005-08-01 16:49:12 +0200120
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200121#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200122#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200124#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200125
126/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200127#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
128#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200129#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese8a316c92005-08-01 16:49:12 +0200130
wdenkacea76a2002-09-20 09:17:33 +0000131/*-----------------------------------------------------------------------
132 * DDR SDRAM
133 *----------------------------------------------------------------------*/
Stefan Roese8423e5e2007-03-16 21:11:42 +0100134#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
135#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
136#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
wdenkacea76a2002-09-20 09:17:33 +0000137
138/*-----------------------------------------------------------------------
139 * I2C
140 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
Stefan Roese4f92ed52006-08-07 14:33:32 +0200142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_I2C_MULTI_EEPROMS
144#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
145#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
146#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
147#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenkacea76a2002-09-20 09:17:33 +0000148
Stefan Roese490f2042008-06-06 15:55:03 +0200149/*
150 * Default environment variables
151 */
Stefan Roese8a316c92005-08-01 16:49:12 +0200152#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200153 CONFIG_AMCC_DEF_ENV \
154 CONFIG_AMCC_DEF_ENV_POWERPC \
155 CONFIG_AMCC_DEF_ENV_PPC_OLD \
156 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese8a316c92005-08-01 16:49:12 +0200157 "kernel_addr=ff800000\0" \
158 "ramdisk_addr=ff810000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200159 ""
wdenkacea76a2002-09-20 09:17:33 +0000160
wdenkacea76a2002-09-20 09:17:33 +0000161#define CONFIG_PHY_ADDR 8 /* PHY address */
Stefan Roesea00eccf2008-05-08 11:05:15 +0200162#define CONFIG_HAS_ETH0
Stefan Roese4a3cd9e2005-09-07 16:21:12 +0200163#define CONFIG_HAS_ETH1
164#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
wdenkacea76a2002-09-20 09:17:33 +0000165
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500166/*
Stefan Roese490f2042008-06-06 15:55:03 +0200167 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500168 */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500169#define CONFIG_CMD_DATE
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500170#define CONFIG_CMD_PCI
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500171#define CONFIG_CMD_SDRAM
172#define CONFIG_CMD_SNTP
173
wdenkacea76a2002-09-20 09:17:33 +0000174/*-----------------------------------------------------------------------
175 * PCI stuff
176 *-----------------------------------------------------------------------
177 */
178/* General PCI */
179#define CONFIG_PCI /* include pci support */
180#define CONFIG_PCI_PNP /* do pci plug-and-play */
181#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
wdenkacea76a2002-09-20 09:17:33 +0000183
184/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
wdenkacea76a2002-09-20 09:17:33 +0000186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
188#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
wdenkacea76a2002-09-20 09:17:33 +0000189
wdenkacea76a2002-09-20 09:17:33 +0000190#endif /* __CONFIG_H */